insns.dat: reformat

Reformat insns.dat with standard formatting

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

diff --git a/insns.dat b/insns.dat
index 6426f7a..ce7df5a 100644 (file)
--- a/insns.dat
+++ b/insns.dat
@@ -3089,149 +3089,149 @@ XSHA256               void                            \336\3\x0F\xA6\xD0                              PENT,CYRIX
 ;
 ; based on pub number 43479 revision 3.03 date May 2009
 ;
-VCVTPH2PS      xmmreg,xmmrm*,imm               [rmi:   xop.m8.w0.l0 a0 /r ib]  AMD,SSE5,SQ
-VCVTPH2PS      ymmreg,xmmrm,imm                [rmi:   xop.m8.w0.l1 a0 /r ib]  AMD,SSE5,SO
-VCVTPH2PS      ymmreg,ymmrm*,imm               [rmi:   xop.m8.w0.l1 a0 /r ib]  AMD,SSE5,SO
+VCVTPH2PS      xmmreg,xmmrm*,imm               [rmi:   xop.m8.w0.l0 a0 /r ib]                  AMD,SSE5,SQ
+VCVTPH2PS      ymmreg,xmmrm,imm                [rmi:   xop.m8.w0.l1 a0 /r ib]                  AMD,SSE5,SO
+VCVTPH2PS      ymmreg,ymmrm*,imm               [rmi:   xop.m8.w0.l1 a0 /r ib]                  AMD,SSE5,SO
 
-VCVTPS2PH      xmmrm,xmmreg*,imm               [mri:   xop.m8.w0.l0 a1 /r ib]  AMD,SSE5,SQ
-VCVTPS2PH      xmmrm,ymmreg,imm                [mri:   xop.m8.w0.l1 a1 /r ib]  AMD,SSE5,SO
-VCVTPS2PH      ymmrm,ymmreg*,imm               [mri:   xop.m8.w0.l1 a1 /r ib]  AMD,SSE5,SO
+VCVTPS2PH      xmmrm,xmmreg*,imm               [mri:   xop.m8.w0.l0 a1 /r ib]                  AMD,SSE5,SQ
+VCVTPS2PH      xmmrm,ymmreg,imm                [mri:   xop.m8.w0.l1 a1 /r ib]                  AMD,SSE5,SO
+VCVTPS2PH      ymmrm,ymmreg*,imm               [mri:   xop.m8.w0.l1 a1 /r ib]                  AMD,SSE5,SO
 
-VFMADDPD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 69 /r /is4] AMD,SSE5,SO
-VFMADDPD       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 69 /r /is4] AMD,SSE5,SY
-VFMADDPD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 69 /r /is4] AMD,SSE5,SO
-VFMADDPD       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 69 /r /is4] AMD,SSE5,SY
+VFMADDPD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 69 /r /is4]         AMD,SSE5,SO
+VFMADDPD       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 69 /r /is4]         AMD,SSE5,SY
+VFMADDPD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 69 /r /is4]         AMD,SSE5,SO
+VFMADDPD       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 69 /r /is4]         AMD,SSE5,SY
 
-VFMADDPS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 68 /r /is4] AMD,SSE5,SO
-VFMADDPS       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 68 /r /is4] AMD,SSE5,SY
-VFMADDPS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 68 /r /is4] AMD,SSE5,SO
-VFMADDPS       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 68 /r /is4] AMD,SSE5,SY
+VFMADDPS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 68 /r /is4]         AMD,SSE5,SO
+VFMADDPS       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 68 /r /is4]         AMD,SSE5,SY
+VFMADDPS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 68 /r /is4]         AMD,SSE5,SO
+VFMADDPS       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 68 /r /is4]         AMD,SSE5,SY
 
-VFMADDSD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6b /r /is4] AMD,SSE5,SQ
-VFMADDSD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6b /r /is4] AMD,SSE5,SQ
+VFMADDSD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6b /r /is4]         AMD,SSE5,SQ
+VFMADDSD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6b /r /is4]         AMD,SSE5,SQ
 
-VFMADDSS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6a /r /is4] AMD,SSE5,SD
-VFMADDSS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6a /r /is4] AMD,SSE5,SD
+VFMADDSS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6a /r /is4]         AMD,SSE5,SD
+VFMADDSS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6a /r /is4]         AMD,SSE5,SD
 
-VFMADDSUBPD    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5d /r /is4] AMD,SSE5,SO
-VFMADDSUBPD    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5d /r /is4] AMD,SSE5,SY
-VFMADDSUBPD    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5d /r /is4] AMD,SSE5,SO
-VFMADDSUBPD    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5d /r /is4] AMD,SSE5,SY
+VFMADDSUBPD    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5d /r /is4]         AMD,SSE5,SO
+VFMADDSUBPD    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5d /r /is4]         AMD,SSE5,SY
+VFMADDSUBPD    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5d /r /is4]         AMD,SSE5,SO
+VFMADDSUBPD    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5d /r /is4]         AMD,SSE5,SY
 
-VFMADDSUBPS    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5c /r /is4] AMD,SSE5,SO
-VFMADDSUBPS    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5c /r /is4] AMD,SSE5,SY
-VFMADDSUBPS    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5c /r /is4] AMD,SSE5,SO
-VFMADDSUBPS    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5c /r /is4] AMD,SSE5,SY
+VFMADDSUBPS    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5c /r /is4]         AMD,SSE5,SO
+VFMADDSUBPS    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5c /r /is4]         AMD,SSE5,SY
+VFMADDSUBPS    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5c /r /is4]         AMD,SSE5,SO
+VFMADDSUBPS    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5c /r /is4]         AMD,SSE5,SY
 
-VFMSUBADDPD    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5f /r /is4] AMD,SSE5,SO
-VFMSUBADDPD    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5f /r /is4] AMD,SSE5,SY
-VFMSUBADDPD    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5f /r /is4] AMD,SSE5,SO
-VFMSUBADDPD    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5f /r /is4] AMD,SSE5,SY
+VFMSUBADDPD    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5f /r /is4]         AMD,SSE5,SO
+VFMSUBADDPD    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5f /r /is4]         AMD,SSE5,SY
+VFMSUBADDPD    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5f /r /is4]         AMD,SSE5,SO
+VFMSUBADDPD    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5f /r /is4]         AMD,SSE5,SY
 
-VFMSUBADDPS    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5e /r /is4] AMD,SSE5,SO
-VFMSUBADDPS    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5e /r /is4] AMD,SSE5,SY
-VFMSUBADDPS    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5e /r /is4] AMD,SSE5,SO
-VFMSUBADDPS    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5e /r /is4] AMD,SSE5,SY
+VFMSUBADDPS    xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 5e /r /is4]         AMD,SSE5,SO
+VFMSUBADDPS    ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 5e /r /is4]         AMD,SSE5,SY
+VFMSUBADDPS    xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 5e /r /is4]         AMD,SSE5,SO
+VFMSUBADDPS    ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 5e /r /is4]         AMD,SSE5,SY
 
-VFMSUBPD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6d /r /is4] AMD,SSE5,SO
-VFMSUBPD       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 6d /r /is4] AMD,SSE5,SY
-VFMSUBPD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6d /r /is4] AMD,SSE5,SO
-VFMSUBPD       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 6d /r /is4] AMD,SSE5,SY
+VFMSUBPD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6d /r /is4]         AMD,SSE5,SO
+VFMSUBPD       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 6d /r /is4]         AMD,SSE5,SY
+VFMSUBPD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6d /r /is4]         AMD,SSE5,SO
+VFMSUBPD       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 6d /r /is4]         AMD,SSE5,SY
 
-VFMSUBPS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6c /r /is4] AMD,SSE5,SO
-VFMSUBPS       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 6c /r /is4] AMD,SSE5,SY
-VFMSUBPS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6c /r /is4] AMD,SSE5,SO
-VFMSUBPS       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 6c /r /is4] AMD,SSE5,SY
+VFMSUBPS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6c /r /is4]         AMD,SSE5,SO
+VFMSUBPS       ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 6c /r /is4]         AMD,SSE5,SY
+VFMSUBPS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6c /r /is4]         AMD,SSE5,SO
+VFMSUBPS       ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 6c /r /is4]         AMD,SSE5,SY
 
-VFMSUBSD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6f /r /is4] AMD,SSE5,SQ
-VFMSUBSD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6f /r /is4] AMD,SSE5,SQ
+VFMSUBSD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6f /r /is4]         AMD,SSE5,SQ
+VFMSUBSD       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6f /r /is4]         AMD,SSE5,SQ
 
-VFMSUBSS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6e /r /is4] AMD,SSE5,SD
-VFMSUBSS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6e /r /is4] AMD,SSE5,SD
+VFMSUBSS       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 6e /r /is4]         AMD,SSE5,SD
+VFMSUBSS       xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 6e /r /is4]         AMD,SSE5,SD
 
-VFNMADDPD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 79 /r /is4] AMD,SSE5,SO
-VFNMADDPD      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 79 /r /is4] AMD,SSE5,SY
-VFNMADDPD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 79 /r /is4] AMD,SSE5,SO
-VFNMADDPD      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 79 /r /is4] AMD,SSE5,SY
+VFNMADDPD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 79 /r /is4]         AMD,SSE5,SO
+VFNMADDPD      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 79 /r /is4]         AMD,SSE5,SY
+VFNMADDPD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 79 /r /is4]         AMD,SSE5,SO
+VFNMADDPD      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 79 /r /is4]         AMD,SSE5,SY
 
-VFNMADDPS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 78 /r /is4] AMD,SSE5,SO
-VFNMADDPS      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 78 /r /is4] AMD,SSE5,SY
-VFNMADDPS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 78 /r /is4] AMD,SSE5,SO
-VFNMADDPS      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 78 /r /is4] AMD,SSE5,SY
+VFNMADDPS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 78 /r /is4]         AMD,SSE5,SO
+VFNMADDPS      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 78 /r /is4]         AMD,SSE5,SY
+VFNMADDPS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 78 /r /is4]         AMD,SSE5,SO
+VFNMADDPS      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 78 /r /is4]         AMD,SSE5,SY
 
-VFNMADDSD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7b /r /is4] AMD,SSE5,SQ
-VFNMADDSD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvms:  vex.m3.w1.nds.l0.p1 7b /r /is4] AMD,SSE5,SQ
+VFNMADDSD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7b /r /is4]         AMD,SSE5,SQ
+VFNMADDSD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvms:  vex.m3.w1.nds.l0.p1 7b /r /is4]         AMD,SSE5,SQ
 
-VFNMADDSS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7a /r /is4] AMD,SSE5,SD
-VFNMADDSS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvms:  vex.m3.w1.nds.l0.p1 7a /r /is4] AMD,SSE5,SD
+VFNMADDSS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7a /r /is4]         AMD,SSE5,SD
+VFNMADDSS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvms:  vex.m3.w1.nds.l0.p1 7a /r /is4]         AMD,SSE5,SD
 
-VFNMSUBPD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7d /r /is4] AMD,SSE5,SO
-VFNMSUBPD      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 7d /r /is4] AMD,SSE5,SY
-VFNMSUBPD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7d /r /is4] AMD,SSE5,SO
-VFNMSUBPD      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 7d /r /is4] AMD,SSE5,SY
+VFNMSUBPD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7d /r /is4]         AMD,SSE5,SO
+VFNMSUBPD      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 7d /r /is4]         AMD,SSE5,SY
+VFNMSUBPD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7d /r /is4]         AMD,SSE5,SO
+VFNMSUBPD      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 7d /r /is4]         AMD,SSE5,SY
 
-VFNMSUBPS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7c /r /is4] AMD,SSE5,SO
-VFNMSUBPS      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 7c /r /is4] AMD,SSE5,SY
-VFNMSUBPS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7c /r /is4] AMD,SSE5,SO
-VFNMSUBPS      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 7c /r /is4] AMD,SSE5,SY
+VFNMSUBPS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7c /r /is4]         AMD,SSE5,SO
+VFNMSUBPS      ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  vex.m3.w0.nds.l1.p1 7c /r /is4]         AMD,SSE5,SY
+VFNMSUBPS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7c /r /is4]         AMD,SSE5,SO
+VFNMSUBPS      ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  vex.m3.w1.nds.l1.p1 7c /r /is4]         AMD,SSE5,SY
 
-VFNMSUBSD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7f /r /is4] AMD,SSE5,SQ
-VFNMSUBSD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7f /r /is4] AMD,SSE5,SQ
+VFNMSUBSD      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7f /r /is4]         AMD,SSE5,SQ
+VFNMSUBSD      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7f /r /is4]         AMD,SSE5,SQ
 
-VFNMSUBSS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7e /r /is4] AMD,SSE5,SD
-VFNMSUBSS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7e /r /is4] AMD,SSE5,SD
+VFNMSUBSS      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  vex.m3.w0.nds.l0.p1 7e /r /is4]         AMD,SSE5,SD
+VFNMSUBSS      xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  vex.m3.w1.nds.l0.p1 7e /r /is4]         AMD,SSE5,SD
 
-VFRCZPD                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 81 /r]          AMD,SSE5,SO
-VFRCZPD                ymmreg,ymmrm*                   [rm:    xop.m9.w0.l1.p0 81 /r]          AMD,SSE5,SY
+VFRCZPD                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 81 /r]                  AMD,SSE5,SO
+VFRCZPD                ymmreg,ymmrm*                   [rm:    xop.m9.w0.l1.p0 81 /r]                  AMD,SSE5,SY
 
-VFRCZPS                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 80 /r]          AMD,SSE5,SO
-VFRCZPS                ymmreg,ymmrm*                   [rm:    xop.m9.w0.l1.p0 80 /r]          AMD,SSE5,SY
+VFRCZPS                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 80 /r]                  AMD,SSE5,SO
+VFRCZPS                ymmreg,ymmrm*                   [rm:    xop.m9.w0.l1.p0 80 /r]                  AMD,SSE5,SY
 
-VFRCZSD                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 83 /r]          AMD,SSE5,SQ
+VFRCZSD                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 83 /r]                  AMD,SSE5,SQ
 
-VFRCZSS                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 82 /r]          AMD,SSE5,SD
+VFRCZSS                xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 82 /r]                  AMD,SSE5,SD
 ;
 ; fixed: spec mention imm[7:4] though it should be /is4 even in spec
-VPCMOV         xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  xop.m8.w0.nds.l0.p0 a2 /r /is4] AMD,SSE5,SO
-VPCMOV         ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  xop.m8.w0.nds.l1.p0 a2 /r /is4] AMD,SSE5,SY
-VPCMOV         xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  xop.m8.w1.nds.l0.p0 a2 /r /is4] AMD,SSE5,SO
-VPCMOV         ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  xop.m8.w1.nds.l1.p0 a2 /r /is4] AMD,SSE5,SY
-
-VPCOMB         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 cc /r ib]   AMD,SSE5,SO
-VPCOMD         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ce /r ib]   AMD,SSE5,SO
-VPCOMQ         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 cf /r ib]   AMD,SSE5,SO
+VPCMOV         xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  xop.m8.w0.nds.l0.p0 a2 /r /is4]         AMD,SSE5,SO
+VPCMOV         ymmreg,ymmreg*,ymmrm,ymmreg     [rvms:  xop.m8.w0.nds.l1.p0 a2 /r /is4]         AMD,SSE5,SY
+VPCMOV         xmmreg,xmmreg*,xmmreg,xmmrm     [rvsm:  xop.m8.w1.nds.l0.p0 a2 /r /is4]         AMD,SSE5,SO
+VPCMOV         ymmreg,ymmreg*,ymmreg,ymmrm     [rvsm:  xop.m8.w1.nds.l1.p0 a2 /r /is4]         AMD,SSE5,SY
+
+VPCOMB         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 cc /r ib]           AMD,SSE5,SO
+VPCOMD         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ce /r ib]           AMD,SSE5,SO
+VPCOMQ         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 cf /r ib]           AMD,SSE5,SO
 ;
 ; fixed: spec mention only 3 operands in mnemonics
-VPCOMUB                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ec /r ib]   AMD,SSE5,SO
-VPCOMUD                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ee /r ib]   AMD,SSE5,SO
-VPCOMUQ                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ef /r ib]   AMD,SSE5,SO
+VPCOMUB                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ec /r ib]           AMD,SSE5,SO
+VPCOMUD                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ee /r ib]           AMD,SSE5,SO
+VPCOMUQ                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ef /r ib]           AMD,SSE5,SO
 ;
 ; fixed: spec point wrong VPCOMB in mnemonic
-VPCOMUW                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ed /r ib]   AMD,SSE5,SO
-VPCOMW         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 cd /r ib]   AMD,SSE5,SO
+VPCOMUW                xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 ed /r ib]           AMD,SSE5,SO
+VPCOMW         xmmreg,xmmreg*,xmmrm,imm        [rvmi:  xop.m8.w0.nds.l0.p0 cd /r ib]           AMD,SSE5,SO
 
-VPHADDBD       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c2 /r]          AMD,SSE5,SO
-VPHADDBQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c3 /r]          AMD,SSE5,SO
-VPHADDBW       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c1 /r]          AMD,SSE5,SO
-VPHADDDQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 cb /r]          AMD,SSE5,SO
+VPHADDBD       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c2 /r]                  AMD,SSE5,SO
+VPHADDBQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c3 /r]                  AMD,SSE5,SO
+VPHADDBW       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c1 /r]                  AMD,SSE5,SO
+VPHADDDQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 cb /r]                  AMD,SSE5,SO
 ;
 ; fixed: spec has ymmreg for l0
-VPHADDUBD      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d2 /r]          AMD,SSE5,SO
-VPHADDUBQ      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d3 /r]          AMD,SSE5,SO
-VPHADDUBWD     xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d1 /r]          AMD,SSE5,SO
+VPHADDUBD      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d2 /r]                  AMD,SSE5,SO
+VPHADDUBQ      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d3 /r]                  AMD,SSE5,SO
+VPHADDUBWD     xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d1 /r]                  AMD,SSE5,SO
 ;
 ; fixed: opcode db
-VPHADDUDQ      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 db /r]          AMD,SSE5,SO
-VPHADDUWD      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d6 /r]          AMD,SSE5,SO
-VPHADDUWQ      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d7 /r]          AMD,SSE5,SO
+VPHADDUDQ      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 db /r]                  AMD,SSE5,SO
+VPHADDUWD      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d6 /r]                  AMD,SSE5,SO
+VPHADDUWQ      xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d7 /r]                  AMD,SSE5,SO
 ;
 ; fixed: spec has ymmreg for l0
-VPHADDWD       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c6 /r]          AMD,SSE5,SO
-VPHADDWQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d7 /r]          AMD,SSE5,SO
+VPHADDWD       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 c6 /r]                  AMD,SSE5,SO
+VPHADDWQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 d7 /r]                  AMD,SSE5,SO
 
-VPHSUBBW       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 e1 /r]          AMD,SSE5,SO
-VPHSUBDQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 e3 /r]          AMD,SSE5,SO
-VPHSUBWD       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 e2 /r]          AMD,SSE5,SO
+VPHSUBBW       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 e1 /r]                  AMD,SSE5,SO
+VPHSUBDQ       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 e3 /r]                  AMD,SSE5,SO
+VPHSUBWD       xmmreg,xmmrm*                   [rm:    xop.m9.w0.l0.p0 e2 /r]                  AMD,SSE5,SO
 
 VPMACSDD       xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  xop.m8.w0.nds.l0.p0 9e /r /is4]         AMD,SSE5,SO
 VPMACSDQH      xmmreg,xmmreg*,xmmrm,xmmreg     [rvms:  xop.m8.w0.nds.l0.p0 97 /r /is4]         AMD,SSE5,SO