brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
+ /* From gen10 workaround table in h/w specs:
+ *
+ * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
+ * a value of 0xFFFF"
+ *
+ * This means that we end up setting the entire 3D_MODE state. Bits
+ * in this register control things such as slice hashing and we want
+ * the default values of zero at the moment.
+ */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_3D_MODE << 16 | (2 - 2));
+ OUT_BATCH(0xFFFF << 16);
+ ADVANCE_BATCH();
}
if (devinfo->gen == 9) {