arm: dts: split mtk-reset.h into per-chip header
authorRyder Lee <ryder.lee@mediatek.com>
Thu, 22 Aug 2019 10:26:52 +0000 (12:26 +0200)
committerTom Rini <trini@konsulko.com>
Fri, 11 Oct 2019 14:10:18 +0000 (10:10 -0400)
This follows the linux header rules to avoid conflict bitfields.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
arch/arm/dts/mt7623.dtsi
arch/arm/dts/mt7629.dtsi
include/dt-bindings/reset/mt7623-reset.h [moved from include/dt-bindings/reset/mtk-reset.h with 88% similarity]
include/dt-bindings/reset/mt7629-reset.h [new file with mode: 0644]

index 3a868ea..1135b1e 100644 (file)
@@ -11,7 +11,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt7623-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7623-reset.h>
 #include "skeleton.dtsi"
 
 / {
index 8ff1916..b0c843b 100644 (file)
@@ -10,7 +10,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/mt7629-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7629-reset.h>
 #include "skeleton.dtsi"
 
 / {
similarity index 88%
rename from include/dt-bindings/reset/mtk-reset.h
rename to include/dt-bindings/reset/mt7623-reset.h
index 78fcdab..a859a5b 100644 (file)
@@ -6,11 +6,9 @@
 #ifndef _DT_BINDINGS_MTK_RESET_H_
 #define _DT_BINDINGS_MTK_RESET_H_
 
-/* ETHSYS */
+/* ETHSYS resets */
 #define ETHSYS_PPE_RST                 31
-#define ETHSYS_EPHY_RST                        24
 #define ETHSYS_GMAC_RST                        23
-#define ETHSYS_ESW_RST                 16
 #define ETHSYS_FE_RST                  6
 #define ETHSYS_MCM_RST                 2
 #define ETHSYS_SYS_RST                 0
diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h
new file mode 100644 (file)
index 0000000..8f1634f
--- /dev/null
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* PCIe Subsystem resets */
+#define PCIE1_CORE_RST                 19
+#define PCIE1_MMIO_RST                 20
+#define PCIE1_HRST                     21
+#define PCIE1_USER_RST                 22
+#define PCIE1_PIPE_RST                 23
+#define PCIE0_CORE_RST                 27
+#define PCIE0_MMIO_RST                 28
+#define PCIE0_HRST                     29
+#define PCIE0_USER_RST                 30
+#define PCIE0_PIPE_RST                 31
+
+/* SSUSB Subsystem resets */
+#define SSUSB_PHY_PWR_RST              3
+#define SSUSB_MAC_PWR_RST              4
+
+/* ETH Subsystem resets */
+#define ETHSYS_SYS_RST                 0
+#define ETHSYS_MCM_RST                 2
+#define ETHSYS_HSDMA_RST               5
+#define ETHSYS_FE_RST                  6
+#define ETHSYS_ESW_RST                 16
+#define ETHSYS_GMAC_RST                        23
+#define ETHSYS_EPHY_RST                        24
+#define ETHSYS_CRYPTO_RST              29
+#define ETHSYS_PPE_RST                 31
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */