f.fprclass, m>;
}
+// Narrowing instructions like vnsrl/vnsra/vnclip(u) don't need @earlyclobber
+// if the source and destination have an LMUL<=1. This matches this overlap
+// exception from the spec.
+// "The destination EEW is smaller than the source EEW and the overlap is in the
+// lowest-numbered part of the source register group."
multiclass VPseudoBinaryV_WV {
foreach m = MxListW.m in
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
- "@earlyclobber $rd">;
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
multiclass VPseudoBinaryV_WX {
foreach m = MxListW.m in
defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
- "@earlyclobber $rd">;
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
multiclass VPseudoBinaryV_WI {
foreach m = MxListW.m in
defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
- "@earlyclobber $rd">;
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
// For vadc and vsbc, the instruction encoding is reserved if the destination
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8>
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i16>
store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i8>
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i16>
store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v26, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
; CHECK-NEXT: vsetivli zero, 2, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i32> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z
; CHECK-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <4 x i32> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
+; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v27, 4
+; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vse8.v v26, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i32_v8i8:
; LMULMAX4-NEXT: vsetivli zero, 8, e16,m1,ta,mu
; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX4-NEXT: vse8.v v26, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX4-NEXT: vse8.v v25, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
+; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v27, v25
-; LMULMAX1-NEXT: vslideup.vi v27, v26, 0
+; LMULMAX1-NEXT: vmv1r.v v27, v26
+; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v28, 4
+; LMULMAX1-NEXT: vslideup.vi v27, v25, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8,m1,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v26, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v25, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v26, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v28, 4
+; LMULMAX1-NEXT: vslideup.vi v26, v27, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 8
+; LMULMAX1-NEXT: vslideup.vi v25, v26, 8
; LMULMAX1-NEXT: vsetvli zero, zero, e8,m1,ta,mu
-; LMULMAX1-NEXT: vse8.v v26, (a0)
+; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i32_v16i8:
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i8>
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i16>
store <2 x i16> %y, <2 x i16>* %z
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
; LMULMAX4-NEXT: vsetivli zero, 4, e32,m1,ta,mu
; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX4-NEXT: vse8.v v25, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i8>
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
+; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v27, 2
+; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vse16.v v26, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v4i64_v4i16:
; LMULMAX4-NEXT: vsetivli zero, 4, e32,m1,ta,mu
; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX4-NEXT: vse16.v v26, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX4-NEXT: vse16.v v25, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
; LMULMAX1-NEXT: vslideup.vi v27, v25, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v27, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
; LMULMAX4-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX4-NEXT: vse8.v v26, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX4-NEXT: vse8.v v25, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
+; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v27, v25
-; LMULMAX1-NEXT: vslideup.vi v27, v26, 0
+; LMULMAX1-NEXT: vmv1r.v v27, v26
+; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v27, v25, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v26, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v25, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v26, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v26, v27, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e16,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v25, v26, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e16,m1,ta,mu
-; LMULMAX1-NEXT: vse16.v v26, (a0)
+; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i64_v8i16:
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v28, v25
-; LMULMAX1-NEXT: vslideup.vi v28, v27, 0
+; LMULMAX1-NEXT: vmv1r.v v27, v25
+; LMULMAX1-NEXT: vslideup.vi v27, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v26, 2
+; LMULMAX1-NEXT: vslideup.vi v27, v26, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v27, v26
-; LMULMAX1-NEXT: vslideup.vi v27, v28, 0
+; LMULMAX1-NEXT: vmv1r.v v28, v26
+; LMULMAX1-NEXT: vslideup.vi v28, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
; LMULMAX1-NEXT: vmv1r.v v29, v25
-; LMULMAX1-NEXT: vslideup.vi v29, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v30, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v30, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v29, v27, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v29, 4
+; LMULMAX1-NEXT: vslideup.vi v28, v29, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8,m1,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v28, 0
+; LMULMAX1-NEXT: vmv.v.i v27, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v27, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v12, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
; LMULMAX1-NEXT: vmv1r.v v29, v25
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v29, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v13, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v13, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v30, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v30, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 2
+; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v29, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v14, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v14, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v25, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v15, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v15, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v27, 2
+; LMULMAX1-NEXT: vslideup.vi v25, v28, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v26, 8
+; LMULMAX1-NEXT: vslideup.vi v27, v26, 8
; LMULMAX1-NEXT: vsetvli zero, zero, e8,m1,ta,mu
-; LMULMAX1-NEXT: vse8.v v28, (a0)
+; LMULMAX1-NEXT: vse8.v v27, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i64_v16i8:
; LMULMAX4-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e8,m1,ta,mu
-; LMULMAX4-NEXT: vmv.v.i v25, 0
+; LMULMAX4-NEXT: vmv.v.i v26, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e8,m1,tu,mu
-; LMULMAX4-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX4-NEXT: vslideup.vi v26, v25, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e32,m2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v12, 0
+; LMULMAX4-NEXT: vnsrl.wi v28, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16,m1,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v28, v26, 0
+; LMULMAX4-NEXT: vnsrl.wi v25, v28, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v28, 0
+; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e8,m1,tu,mu
-; LMULMAX4-NEXT: vslideup.vi v25, v26, 8
+; LMULMAX4-NEXT: vslideup.vi v26, v25, 8
; LMULMAX4-NEXT: vsetvli zero, zero, e8,m1,ta,mu
-; LMULMAX4-NEXT: vse8.v v25, (a0)
+; LMULMAX4-NEXT: vse8.v v26, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v27, 2
+; LMULMAX1-NEXT: vslideup.vi v28, v26, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,m1,tu,mu
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v28, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v28, v25
-; LMULMAX1-NEXT: vslideup.vi v28, v29, 0
+; LMULMAX1-NEXT: vmv1r.v v29, v25
+; LMULMAX1-NEXT: vslideup.vi v29, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v30, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v30, 2
+; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e16,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v28, 4
+; LMULMAX1-NEXT: vslideup.vi v27, v29, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v28, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v28, v25
-; LMULMAX1-NEXT: vslideup.vi v28, v29, 0
+; LMULMAX1-NEXT: vmv1r.v v29, v25
+; LMULMAX1-NEXT: vslideup.vi v29, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v13, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v13, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v30, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v30, 2
+; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
; LMULMAX1-NEXT: vsetivli zero, 4, e16,m1,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v26, v29, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v28, v14, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v29, 0
+; LMULMAX1-NEXT: vslideup.vi v25, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v28, v15, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v28, v28, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v25, v29, 2
+; LMULMAX1-NEXT: vslideup.vi v25, v28, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e16,m1,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
; LMULMAX1-NEXT: addi a1, a0, 16
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v26, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%d = fptosi <2 x double> %a to <2 x i8>
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v26, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1)
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vse8.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%d = fptoui <2 x double> %a to <2 x i8>
; LMULMAX8-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX8-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX8-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX8-NEXT: vse8.v v26, (a1)
+; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX8-NEXT: vse8.v v25, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2si_v8f64_v8i8:
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
+; LMULMAX1-NEXT: vmv.v.i v29, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v30, v27
-; LMULMAX1-NEXT: vslideup.vi v30, v29, 0
+; LMULMAX1-NEXT: vmv1r.v v30, v29
+; LMULMAX1-NEXT: vslideup.vi v30, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v29, v28
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v28
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v30, v29, 2
+; LMULMAX1-NEXT: vslideup.vi v30, v27, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v28, 0
+; LMULMAX1-NEXT: vmv.v.i v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v30, 0
+; LMULMAX1-NEXT: vslideup.vi v27, v30, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v29, v26
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v28, v26
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v28, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v29, 0
+; LMULMAX1-NEXT: vslideup.vi v29, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v25
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v26, 2
+; LMULMAX1-NEXT: vslideup.vi v29, v25, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v27, 4
+; LMULMAX1-NEXT: vslideup.vi v27, v29, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vse8.v v28, (a1)
+; LMULMAX1-NEXT: vse8.v v27, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%d = fptosi <8 x double> %a to <8 x i8>
; LMULMAX8-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX8-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX8-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX8-NEXT: vse8.v v26, (a1)
+; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX8-NEXT: vse8.v v25, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2ui_v8f64_v8i8:
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
+; LMULMAX1-NEXT: vmv.v.i v29, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vmv1r.v v30, v27
-; LMULMAX1-NEXT: vslideup.vi v30, v29, 0
+; LMULMAX1-NEXT: vmv1r.v v30, v29
+; LMULMAX1-NEXT: vslideup.vi v30, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v29, v28
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v28
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v28, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v28, 0
+; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v30, v29, 2
+; LMULMAX1-NEXT: vslideup.vi v30, v27, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vmv.v.i v28, 0
+; LMULMAX1-NEXT: vmv.v.i v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v30, 0
+; LMULMAX1-NEXT: vslideup.vi v27, v30, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v29, v26
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v28, v26
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v28, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v29, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v29, 0
+; LMULMAX1-NEXT: vslideup.vi v29, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v25
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf4,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v26, 2
+; LMULMAX1-NEXT: vslideup.vi v29, v25, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v28, v27, 4
+; LMULMAX1-NEXT: vslideup.vi v27, v29, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX1-NEXT: vse8.v v28, (a1)
+; LMULMAX1-NEXT: vse8.v v27, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%d = fptoui <8 x double> %a to <8 x i8>
; CHECK-NEXT: vsetivli zero, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vse8.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
; LMULMAX8-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX8-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX8-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX8-NEXT: vse8.v v26, (a1)
+; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX8-NEXT: vse8.v v25, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: trunc_v8i8_v8i32:
; LMULMAX2-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; LMULMAX2-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX2-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
-; LMULMAX2-NEXT: vnsrl.wi v26, v25, 0
-; LMULMAX2-NEXT: vse8.v v26, (a1)
+; LMULMAX2-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX2-NEXT: vse8.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: trunc_v8i8_v8i32:
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v26, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
; LMULMAX1-NEXT: vmv.v.i v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
; LMULMAX1-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8,mf2,tu,mu
-; LMULMAX1-NEXT: vslideup.vi v27, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v27, v25, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
; LMULMAX1-NEXT: vse8.v v27, (a1)
; LMULMAX1-NEXT: ret
; RV32-NEXT: vsetivli zero, 2, e16,mf4,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; RV32-NEXT: vnsrl.wi v26, v25, 0
-; RV32-NEXT: vsoxei32.v v26, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV64-NEXT: vsetivli zero, 2, e16,mf4,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; RV64-NEXT: vnsrl.wi v26, v25, 0
-; RV64-NEXT: vsoxei64.v v26, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
; RV32-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; RV32-NEXT: vnsrl.wi v26, v25, 0
+; RV32-NEXT: vnsrl.wi v25, v25, 0
; RV32-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; RV32-NEXT: vnsrl.wi v25, v26, 0
+; RV32-NEXT: vnsrl.wi v25, v25, 0
; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; RV64-NEXT: vnsrl.wi v26, v25, 0
+; RV64-NEXT: vnsrl.wi v25, v25, 0
; RV64-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; RV64-NEXT: vnsrl.wi v25, v26, 0
+; RV64-NEXT: vnsrl.wi v25, v25, 0
; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i8>
; RV32-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; RV32-NEXT: vnsrl.wi v26, v25, 0
-; RV32-NEXT: vsoxei32.v v26, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i16:
; RV64-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; RV64-NEXT: vnsrl.wi v26, v25, 0
-; RV64-NEXT: vsoxei64.v v26, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i16>
call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
; CHECK-LABEL: vnsra_v8i16_v8i8_scalar:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
%insert = insertelement <8 x i16> undef, i16 %y, i16 0
%splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
; CHECK-LABEL: vnsra_v4i32_v4i16_scalar:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
%insert = insertelement <4 x i32> undef, i32 %y, i32 0
%splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-LABEL: vnsra_v2i64_v2i32_scalar:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
; RV32-LABEL: vnsra_v2i64_v2i32_scalar:
; RV32: # %bb.0:
; CHECK-LABEL: vnsra_v8i16_v8i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: ret
%a = ashr <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8,i16 8, i16 8, i16 8, i16 8>
%b = trunc <8 x i16> %a to <8 x i8>
; CHECK-LABEL: vnsra_v4i32_v4i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 16
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 16
; CHECK-NEXT: ret
%a = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
%b = trunc <4 x i32> %a to <4 x i16>
; CHECK-LABEL: vnsra_v2i64_v2i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 31
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 31
; CHECK-NEXT: ret
%a = ashr <2 x i64> %x, <i64 31, i64 31>
%b = trunc <2 x i64> %a to <2 x i32>
; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
%insert = insertelement <8 x i16> undef, i16 %y, i16 0
%splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
%insert = insertelement <4 x i32> undef, i32 %y, i32 0
%splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
; RV32-LABEL: vnsrl_v2i64_v2i32_scalar:
; RV32: # %bb.0:
; CHECK-LABEL: vnsrl_v8i16_v8i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: ret
%a = lshr <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8,i16 8, i16 8, i16 8, i16 8>
%b = trunc <8 x i16> %a to <8 x i8>
; CHECK-LABEL: vnsrl_v4i32_v4i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 16
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 16
; CHECK-NEXT: ret
%a = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
%b = trunc <4 x i32> %a to <4 x i16>
; CHECK-LABEL: vnsrl_v2i64_v2i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 31
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 31
; CHECK-NEXT: ret
%a = lshr <2 x i64> %x, <i64 31, i64 31>
%b = trunc <2 x i64> %a to <2 x i32>
; RV32-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; RV32-NEXT: vnsrl.wi v26, v25, 0
-; RV32-NEXT: vsoxei32.v v26, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i8:
; RV64-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; RV64-NEXT: vnsrl.wi v26, v25, 0
-; RV64-NEXT: vsoxei64.v v26, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
; RV32-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; RV32-NEXT: vnsrl.wi v26, v25, 0
+; RV32-NEXT: vnsrl.wi v25, v25, 0
; RV32-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; RV32-NEXT: vnsrl.wi v25, v26, 0
+; RV32-NEXT: vnsrl.wi v25, v25, 0
; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; RV64-NEXT: vnsrl.wi v26, v25, 0
+; RV64-NEXT: vnsrl.wi v25, v25, 0
; RV64-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; RV64-NEXT: vnsrl.wi v25, v26, 0
+; RV64-NEXT: vnsrl.wi v25, v25, 0
; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
; RV32-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; RV32-NEXT: vnsrl.wi v26, v25, 0
-; RV32-NEXT: vsoxei32.v v26, (zero), v10, v0.t
+; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i16:
; RV64-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; RV64-NEXT: vnsrl.wi v26, v25, 0
-; RV64-NEXT: vsoxei64.v v26, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m)
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclip.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.nxv1i16(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %tvec
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %tvec
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %tvec
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %tvec
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %tvec
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %tvec
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vnsrl.wi v26, v25, 0
+; CHECK-NEXT: vnsrl.wi v25, v25, 0
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v25, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec