const MachineInstr &MI1,
const MachineRegisterInfo *MRI) const {
unsigned Opcode = MI0.getOpcode();
- if (Opcode == ARM::t2LDRpci ||
- Opcode == ARM::t2LDRpci_pic ||
- Opcode == ARM::tLDRpci ||
- Opcode == ARM::tLDRpci_pic ||
- Opcode == ARM::LDRLIT_ga_pcrel ||
- Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
- Opcode == ARM::tLDRLIT_ga_pcrel ||
- Opcode == ARM::MOV_ga_pcrel ||
- Opcode == ARM::MOV_ga_pcrel_ldr ||
+ if (Opcode == ARM::t2LDRpci || Opcode == ARM::t2LDRpci_pic ||
+ Opcode == ARM::tLDRpci || Opcode == ARM::tLDRpci_pic ||
+ Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
+ Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
+ Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
Opcode == ARM::t2MOV_ga_pcrel) {
if (MI1.getOpcode() != Opcode)
return false;
if (MO0.getOffset() != MO1.getOffset())
return false;
- if (Opcode == ARM::LDRLIT_ga_pcrel ||
- Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
- Opcode == ARM::tLDRLIT_ga_pcrel ||
- Opcode == ARM::MOV_ga_pcrel ||
- Opcode == ARM::MOV_ga_pcrel_ldr ||
+ if (Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
+ Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
+ Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
Opcode == ARM::t2MOV_ga_pcrel)
// Ignore the PC labels.
return MO0.getGlobal() == MO1.getGlobal();
case ARM::LDRLIT_ga_pcrel:
case ARM::LDRLIT_ga_pcrel_ldr:
case ARM::tLDRLIT_ga_abs:
+ case ARM::t2LDRLIT_ga_pcrel:
case ARM::tLDRLIT_ga_pcrel: {
Register DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
const MachineOperand &MO1 = MI.getOperand(1);
auto Flags = MO1.getTargetFlags();
const GlobalValue *GV = MO1.getGlobal();
- bool IsARM =
- Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
+ bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
+ Opcode != ARM::tLDRLIT_ga_abs &&
+ Opcode != ARM::t2LDRLIT_ga_pcrel;
bool IsPIC =
Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
+ if (Opcode == ARM::t2LDRLIT_ga_pcrel)
+ LDRLITOpc = ARM::t2LDRpci;
unsigned PICAddOpc =
IsARM
? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
+let hasNoSchedulingInfo = 1 in {
+def t2LDRLIT_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
+ IIC_iLoadiALU,
+ [(set rGPR:$dst,
+ (ARMWrapperPIC tglobaladdr:$addr))]>,
+ Requires<[IsThumb, HasV8MBaseline, DontUseMovtInPic]>;
+}
+
+// TLS globals
+def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
+ (t2LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
+ Requires<[IsThumb, HasV8MBaseline, DontUseMovtInPic]>;
+
// Pseudo instruction that combines ldr from constpool and add pc. This should
// be expanded into two instructions late to allow if-conversion and
// scheduling.
cast<GlobalValue>((*MI->memoperands_begin())->getValue());
if (MF.getSubtarget<ARMSubtarget>().isGVInGOT(GV))
- expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::t2LDRi12);
+ expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12);
else if (MF.getTarget().isPositionIndependent())
expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
else
--- /dev/null
+; RUN: llc -filetype=obj -relocation-model=pic %s --verify-machineinstrs -print-after=postrapseudos 2>&1 | FileCheck -check-prefix=CHECK-POST-RA %s
+; RUN: llc -filetype=obj -relocation-model=pic %s --verify-machineinstrs -print-after=arm-pseudo 2>&1 | FileCheck -check-prefix=CHECK-POST-AP %s
+
+; CHECK-POST-RA: $r12 = t2LDRLIT_ga_pcrel target-flags(arm-got) @__stack_chk_guard
+; CHECK-POST-AP: $r12 = t2LDRpci %const.0, 14, $noreg
+
+target triple = "thumbv7-unknown-linux-android23"
+
+%"class.v8::internal::Assembler" = type {}
+%"class.v8::internal::Operand" = type { %"class.v8::internal::Register", %"class.v8::internal::Register", i32, i32, %"union.v8::internal::Operand::Value" }
+%"class.v8::internal::Register" = type {}
+%"union.v8::internal::Operand::Value" = type { i32, [20 x i8] }
+%"class.v8::internal::wasm::LiftoffAssembler" = type {}
+
+declare void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(%"class.v8::internal::Assembler"*, [1 x i32], [1 x i32], %"class.v8::internal::Operand"*, i32, i32)
+
+; Function Attrs: ssp
+define void @_ZN2v88internal4wasm16LiftoffAssembler13emit_i32_addiENS0_8RegisterES3_i(%"class.v8::internal::wasm::LiftoffAssembler"* %0, [1 x i32] %1, [1 x i32] %2, i32 %3) #0 {
+ %5 = alloca %"class.v8::internal::Operand", align 8
+ %6 = bitcast %"class.v8::internal::wasm::LiftoffAssembler"* %0 to %"class.v8::internal::Assembler"*
+ %7 = bitcast %"class.v8::internal::Operand"* %5 to i8*
+ %8 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
+ %9 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
+ %10 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
+ %11 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
+ %12 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5, i32 0, i32 4, i32 0
+ store i32 %3, i32* %12, align 4
+ call void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(%"class.v8::internal::Assembler"* %6, [1 x i32] %1, [1 x i32] %2, %"class.v8::internal::Operand"* %5, i32 0, i32 2)
+ ret void
+}
+
+attributes #0 = { ssp }