intel/fs/xe2+: Update BS payload setup for Xe2 reg size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 8ccabc8..2f7f50c 100644 (file)
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7368,7 +7368,7 @@ fs_visitor::run_bs(bool allow_spilling)
 {
    assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
 
-   payload_ = new bs_thread_payload();
+   payload_ = new bs_thread_payload(*this);
 
    emit_nir_code();
 

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index fc8f0ed..7239f42 100644 (file)
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -167,7 +167,7 @@ struct task_mesh_thread_payload : public cs_thread_payload {
 };
 
 struct bs_thread_payload : public thread_payload {
-   bs_thread_payload();
+   bs_thread_payload(const fs_visitor &v);
 
    fs_reg global_arg_ptr;
    fs_reg local_arg_ptr;

diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index 89acc4a..172fdbc 100644 (file)
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -468,17 +468,22 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
    num_regs = r;
 }
 
-bs_thread_payload::bs_thread_payload()
+bs_thread_payload::bs_thread_payload(const fs_visitor &v)
 {
+   unsigned r = 0;
+
    /* R0: Thread header. */
+   r += reg_unit(v.devinfo);
 
    /* R1: Stack IDs. */
+   r += reg_unit(v.devinfo);
 
-   /* R2: Argument addresses. */
-   global_arg_ptr = brw_ud1_grf(2, 0);
-   local_arg_ptr = brw_ud1_grf(2, 2);
+   /* R2: Inline Parameter.  Used for argument addresses. */
+   global_arg_ptr = brw_ud1_grf(r, 0);
+   local_arg_ptr = brw_ud1_grf(r, 2);
+   r += reg_unit(v.devinfo);
 
-   num_regs = 3;
+   num_regs = r;
 }
 
 void