},
};
-const char *gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
+static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
static struct clk_regmap gxbb_vid_pll_sel = {
.data = &(struct clk_regmap_mux_data){
},
};
-const char *gxbb_vclk_parent_names[] = {
+static const char * const gxbb_vclk_parent_names[] = {
"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
"fclk_div7", "mpll1",
};
};
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-const char *gxbb_cts_parent_names[] = {
+static const char * const gxbb_cts_parent_names[] = {
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
"vclk2_div6", "vclk2_div12"
/* TOFIX: add support for cts_tcon */
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-const char *gxbb_cts_hdmi_tx_parent_names[] = {
+static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
"vclk2_div6", "vclk2_div12"
#define to_meson_vid_pll_div(_hw) \
container_of(_hw, struct meson_vid_pll_div, hw)
-const struct vid_pll_div *_get_table_val(unsigned int shift_val,
- unsigned int shift_sel)
+static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
+ unsigned int shift_sel)
{
int i;