debug("%s: count=%d\n", __func__, count);
for (i = 0; i < count; i++) {
debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
- if (!ofnode_is_available(nodes[i]))
+ if (!ofnode_is_enabled(nodes[i]))
continue;
padctl.socdata = socdata;
continue;
/* skip if hart is marked as not available */
- if (!ofnode_is_available(node))
+ if (!ofnode_is_enabled(node))
continue;
/* read hart ID of CPU */
ofnode_for_each_subnode(node, cpus) {
/* skip if hart is marked as not available in the device tree */
- if (!ofnode_is_available(node))
+ if (!ofnode_is_enabled(node))
continue;
/* read hart ID of CPU */
propname, lenp);
}
-bool ofnode_is_available(ofnode node)
-{
- if (ofnode_is_np(node))
- return of_device_is_available(ofnode_to_np(node));
- else
- return fdtdec_get_is_enabled(gd->fdt_blob,
- ofnode_to_offset(node));
-}
-
fdt_addr_t ofnode_get_addr_size(ofnode node, const char *property,
fdt_size_t *sizep)
{
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
const char *device_type;
- if (!ofnode_is_available(node))
+ if (!ofnode_is_enabled(node))
continue;
device_type = ofnode_read_string(node, "device_type");
const char *device_type;
/* skip if hart is marked as not available in the device tree */
- if (!ofnode_is_available(node))
+ if (!ofnode_is_enabled(node))
continue;
device_type = ofnode_read_string(node, "device_type");
/* Check for enabled job ring node */
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
- if (!ofnode_is_available(node))
+ if (!ofnode_is_enabled(node))
continue;
jr_node = ofnode_read_u32_default(node, "reg", -1);
struct driver *drv = NULL;
u32 protocol_id;
- if (!ofnode_is_available(node))
+ if (!ofnode_is_enabled(node))
continue;
if (ofnode_read_u32(node, "reg", &protocol_id))
else
parts = ofnode_find_subnode(master->flash_node, "partitions");
- if (!ofnode_valid(parts) || !ofnode_is_available(parts) ||
+ if (!ofnode_valid(parts) || !ofnode_is_enabled(parts) ||
!ofnode_device_is_compatible(parts, "fixed-partitions"))
return 0;
fdt_addr_t offset;
fdt_size_t size;
- if (!ofnode_is_available(child))
+ if (!ofnode_is_enabled(child))
continue;
offset = ofnode_get_addr_size_index_notrans(child, 0, &size);
}
}
- if (!ofnode_is_available(of_nand)) {
+ if (!ofnode_is_enabled(of_nand)) {
debug("Nand node in dt disabled\n");
return dm_scan_fdt_dev(dev);
}
return ret;
}
- if (!ofnode_is_available(phandle_args.node))
+ if (!ofnode_is_enabled(phandle_args.node))
return -ENOENT;
priv->phy_of_node = phandle_args.node;
struct enetc_priv *priv = dev_get_priv(dev);
int res;
- if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) {
+ if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_enabled(dev_ofnode(dev))) {
enetc_dbg(dev, "interface disabled\n");
return -ENODEV;
}
int err;
if (ofnode_valid(dev_ofnode(dev)) &&
- !ofnode_is_available(dev_ofnode(dev))) {
+ !ofnode_is_enabled(dev_ofnode(dev))) {
dev_dbg(dev, "switch disabled\n");
return -ENODEV;
}
int rc;
if (ofnode_valid(dev_ofnode(dev)) &&
- !ofnode_is_available(dev_ofnode(dev))) {
+ !ofnode_is_enabled(dev_ofnode(dev))) {
dev_dbg(dev, "switch disabled\n");
return -ENODEV;
}
node_name = ofnode_get_name(node);
- disabled = !ofnode_is_available(node);
+ disabled = !ofnode_is_enabled(node);
ret = ofnode_read_u32(node, "reg", &port_id);
if (ret) {
if (ofnode_valid(dev_ofnode(parent)))
pci_dev_find_ofnode(parent, bdf, &node);
- if (ofnode_valid(node) && !ofnode_is_available(node)) {
+ if (ofnode_valid(node) && !ofnode_is_enabled(node)) {
debug("%s: Ignoring disabled device\n", __func__);
return log_msg_ret("dis", -EPERM);
}
/* First phase: Fill mvebu_pcie struct for each port */
ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
- if (!ofnode_is_available(subnode))
+ if (!ofnode_is_enabled(subnode))
continue;
pcie = calloc(1, sizeof(*pcie));
lanes |= num_lanes << (index << 3);
- if (!ofnode_is_available(subnode))
+ if (!ofnode_is_enabled(subnode))
continue;
port = malloc(sizeof(*port));
struct fdt_pci_addr addr;
u32 slot = 0;
- if (!ofnode_is_available(subnode))
+ if (!ofnode_is_enabled(subnode))
continue;
err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
pcie->priv = dev;
dev_for_each_subnode(subnode, dev) {
- if (!ofnode_is_available(subnode))
+ if (!ofnode_is_enabled(subnode))
continue;
err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
const char **propname, int *lenp);
/**
- * ofnode_is_available() - check if a node is marked available
- *
- * @node: node to check
- * Return: true if node's 'status' property is "okay" (or is missing)
- */
-bool ofnode_is_available(ofnode node);
-
-/**
* ofnode_get_addr_size() - get address and size from a property
*
* This does no address translation. It simply reads an property that contains
{
do {
mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
- } while (!ofnode_is_available(mem));
+ } while (!ofnode_is_enabled(mem));
return mem;
}
* skip registration if port id not found or if the port
* is explicitly disabled in DT
*/
- if (!ofnode_valid(pnode) || !ofnode_is_available(pnode))
+ if (!ofnode_valid(pnode) || !ofnode_is_enabled(pnode))
continue;
err = device_bind_driver_to_node(dev, DSA_PORT_CHILD_DRV_NAME,