select SAMSUNG_CLKSRC
select SAMSUNG_GPIOLIB_4BIT
select SAMSUNG_IRQ_VIC_TIMER
+ select SAMSUNG_WDT_RESET
select USB_ARCH_HAS_OHCI
help
Samsung S3C64XX series based systems
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_GPIO_H
+ select SAMSUNG_WDT_RESET
help
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_GPIO_H
+ select SAMSUNG_WDT_RESET
help
Samsung S5PC100 series based systems
select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
select S3C2410_PM if PM
select SAMSUNG_HRT
+ select SAMSUNG_WDT_RESET
help
Support for S3C2410 and S3C2410A family from the S3C24XX line
of Samsung Mobile CPUs.
config CPU_S3C244X
def_bool y
depends on CPU_S3C2440 || CPU_S3C2442
+ select SAMSUNG_WDT_RESET
config CPU_S3C2443
bool "SAMSUNG S3C2443"
s3c2410_baseclk_add();
s3c24xx_register_clock(&s3c2410_armclk);
clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
+ samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
}
struct bus_type s3c2410_subsys = {
soft_restart(0);
}
- arch_wdt_reset();
+ samsung_wdt_reset();
/* we'll take a jump through zero as a poor second */
soft_restart(0);
s3c24xx_register_baseclocks(xtal);
s3c244x_setup_clocks();
s3c2410_baseclk_add();
+ samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
}
/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
if (mode == 's')
soft_restart(0);
- arch_wdt_reset();
+ samsung_wdt_reset();
/* we'll take a jump through zero as a poor second */
soft_restart(0);
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
+ /*
+ * FIXME: there is no better place to put this at the moment
+ * (samsung_wdt_reset_init needs clocks)
+ */
+ samsung_wdt_reset_init(S3C_VA_WATCHDOG);
+
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
void s3c64xx_restart(char mode, const char *cmd)
{
if (mode != 's')
- arch_wdt_reset();
+ samsung_wdt_reset();
/* if all else fails, or mode was for soft, jump to 0 */
soft_restart(0);
s5p_init_cpu(S5P64X0_SYS_ID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+ samsung_wdt_reset_init(S3C_VA_WATCHDOG);
+
}
void __init s5p6440_map_io(void)
void s5p64x0_restart(char mode, const char *cmd)
{
if (mode != 's')
- arch_wdt_reset();
+ samsung_wdt_reset();
soft_restart(0);
}
s5p_register_clocks(xtal);
s5pc100_register_clocks();
s5pc100_setup_clocks();
+ samsung_wdt_reset_init(S3C_VA_WATCHDOG);
}
void __init s5pc100_init_irq(void)
void s5pc100_restart(char mode, const char *cmd)
{
if (mode != 's')
- arch_wdt_reset();
+ samsung_wdt_reset();
soft_restart(0);
}