drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode

The DP PHY vswing/pre-emphasis level programming the driver does is
related to the DPTX -> first LTTPR link segment only. Accordingly it
should be only programmed when link training the first LTTPR and kept
as-is when training subsequent LTTPRs and the DPRX. For these latter
PHYs the vs/pe levels will be set in response to writing the
DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR
TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY).
The above is also described in DP Standard v2.0 under 3.6.6.1.

While at it simplify and add the LTTPR that is link trained to the debug
message in intel_dp_set_signal_levels().

Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201229172201.4155327-2-imre.deak@intel.com
(cherry picked from commit 67fba3f1c73b83569d171ae1fa463a537bbfe0a8)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f6eec5c206d8c81a05490a20d289e4bab3b50119..8a26307c48960110b678af7075db41ad3e65de6f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5685,7 +5685,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
 
        intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
 
-       intel_dp_set_signal_levels(intel_dp, crtc_state);
+       intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
 
        intel_dp_phy_pattern_update(intel_dp, crtc_state);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 7876e781f69893f59c3e662b639fcd11af8ab3a3..d8c6d7054d11d929ff8d4170b10b96dcd2c6dcda 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 }
 
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
-                               const struct intel_crtc_state *crtc_state)
+                               const struct intel_crtc_state *crtc_state,
+                               enum drm_dp_phy dp_phy)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        u8 train_set = intel_dp->train_set[0];
+       char phy_name[10];
 
-       drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
+       drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
                    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
-                   train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
-       drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
+                   train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
                    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
                    DP_TRAIN_PRE_EMPHASIS_SHIFT,
                    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
-                   " (max)" : "");
+                   " (max)" : "",
+                   intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
 
-       intel_dp->set_signal_levels(intel_dp, crtc_state);
+       if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
+               intel_dp->set_signal_levels(intel_dp, crtc_state);
 }
 
 static bool
@@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
                          u8 dp_train_pat)
 {
        memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
-       intel_dp_set_signal_levels(intel_dp, crtc_state);
+       intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
        return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
 }
 
@@ -373,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
                            DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
        int ret;
 
-       intel_dp_set_signal_levels(intel_dp, crtc_state);
+       intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 
        ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
                                intel_dp->train_set, crtc_state->lane_count);

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index c3110c032bc2e6eabf7cca36fadca827cae1249c..6a1f76bd8c7586a6f40fea2e4b8b61cb30e97225 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
                               enum drm_dp_phy dp_phy,
                               const u8 link_status[DP_LINK_STATUS_SIZE]);
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
-                               const struct intel_crtc_state *crtc_state);
+                               const struct intel_crtc_state *crtc_state,
+                               enum drm_dp_phy dp_phy);
 void intel_dp_start_link_train(struct intel_dp *intel_dp,
                               const struct intel_crtc_state *crtc_state);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp,