}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector signed __int128 __a, vector signed __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+#endif
+
#ifdef __POWER9_VECTOR__
/* vec_cmpne */
(vector int)__b);
}
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b));
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector signed __int128 __a, vector signed __int128 __b) {
+ return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b));
+}
+#endif
+
/* vec_cmpnez */
static __inline__ vector bool char __ATTRS_o_ai
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpgt(vector signed __int128 __a, vector signed __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpgtsq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpgt(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpgtuq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+#endif
+
/* vec_cmpge */
static __inline__ vector bool char __ATTRS_o_ai
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpge(vector signed __int128 __a, vector signed __int128 __b) {
+ return ~(vec_cmpgt(__b, __a));
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpge(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return ~(vec_cmpgt(__b, __a));
+}
+#endif
+
/* vec_vcmpgefp */
static __inline__ vector bool int __attribute__((__always_inline__))
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmple(vector signed __int128 __a, vector signed __int128 __b) {
+ return vec_cmpge(__b, __a);
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmple(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return vec_cmpge(__b, __a);
+}
+#endif
+
/* vec_cmplt */
static __inline__ vector bool char __ATTRS_o_ai
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmplt(vector signed __int128 __a, vector signed __int128 __b) {
+ return vec_cmpgt(__b, __a);
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmplt(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return vec_cmpgt(__b, __a);
+}
+#endif
+
#ifdef __POWER8_VECTOR__
static __inline__ vector bool long long __ATTRS_o_ai
vec_cmplt(vector signed long long __a, vector signed long long __b) {
// CHECK-NEXT: ret <1 x i128>
return vec_mod(vsi128a, vsi128b);
}
+
+vector bool __int128 test_vec_cmpeq_s128(void) {
+ // CHECK-LABEL: @test_vec_cmpeq_s128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpeq(vsi128a, vsi128b);
+}
+
+vector bool __int128 test_vec_cmpeq_u128(void) {
+ // CHECK-LABEL: @test_vec_cmpeq_u128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpeq(vui128a, vui128b);
+}
+
+vector bool __int128 test_vec_cmpne_s128(void) {
+ // CHECK-LABEL: @test_vec_cmpne_s128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+ // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1>
+ // CHECK-NEXT: ret <1 x i128> %neg.i
+ return vec_cmpne(vsi128a, vsi128b);
+}
+
+vector bool __int128 test_vec_cmpne_u128(void) {
+ // CHECK-LABEL: @test_vec_cmpne_u128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+ // CHECK-NEXT: %neg.i = xor <1 x i128> %4, <i128 -1>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpne(vui128a, vui128b);
+}
+
+vector bool __int128 test_vec_cmpgt_s128(void) {
+ // CHECK-LABEL: @test_vec_cmpgt_s128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpgt(vsi128a, vsi128b);
+}
+
+vector bool __int128 test_vec_cmpgt_u128(void) {
+ // CHECK-LABEL: @test_vec_cmpgt_u128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpgt(vui128a, vui128b);
+}
+
+vector bool __int128 test_vec_cmplt_s128(void) {
+ // CHECK-LABEL: @test_vec_cmplt_s128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmplt(vsi128a, vsi128b);
+}
+
+vector bool __int128 test_vec_cmplt_u128(void) {
+ // CHECK-LABEL: @test_vec_cmplt_u128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmplt(vui128a, vui128b);
+}
+
+vector bool __int128 test_vec_cmpge_s128(void) {
+ // CHECK-LABEL: @test_vec_cmpge_s128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
+ // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpge(vsi128a, vsi128b);
+}
+
+vector bool __int128 test_vec_cmpge_u128(void) {
+ // CHECK-LABEL: @test_vec_cmpge_u128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>
+ // CHECK-NEXT: %neg.i = xor <1 x i128> %6, <i128 -1>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmpge(vui128a, vui128b);
+}
+
+vector bool __int128 test_vec_cmple_s128(void) {
+ // CHECK-LABEL: @test_vec_cmple_s128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
+ // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmple(vsi128a, vsi128b);
+}
+
+vector bool __int128 test_vec_cmple_u128(void) {
+ // CHECK-LABEL: @test_vec_cmple_u128(
+ // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>
+ // CHECK-NEXT: %neg.i.i = xor <1 x i128> %8, <i128 -1>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_cmple(vui128a, vui128b);
+}
--- /dev/null
+; Test the quadword comparison instructions that were added in POWER10.
+;
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
+define <1 x i128> @v1si128_cmp(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+ %cmp = icmp eq <1 x i128> %x, %y
+ %result = sext <1 x i1> %cmp to <1 x i128>
+ ret <1 x i128> %result
+; CHECK-LABEL: v1si128_cmp:
+; CHECK: vcmpequq 2, 2, 3
+}
+
+define <2 x i128> @v2si128_cmp(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
+ %cmp = icmp eq <2 x i128> %x, %y
+ %result = sext <2 x i1> %cmp to <2 x i128>
+ ret <2 x i128> %result
+; CHECK-LABEL: v2si128_cmp
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <4 x i128> @v4si128_cmp(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
+ %cmp = icmp eq <4 x i128> %x, %y
+ %result = sext <4 x i1> %cmp to <4 x i128>
+ ret <4 x i128> %result
+; CHECK-LABEL: v4si128_cmp
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <8 x i128> @v8si128_cmp(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
+ %cmp = icmp eq <8 x i128> %x, %y
+ %result = sext <8 x i1> %cmp to <8 x i128>
+ ret <8 x i128> %result
+; CHECK-LABEL: v8si128_cmp
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <16 x i128> @v16si128_cmp(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
+ %cmp = icmp eq <16 x i128> %x, %y
+ %result = sext <16 x i1> %cmp to <16 x i128>
+ ret <16 x i128> %result
+; CHECK-LABEL: v16si128_cmp
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+; Greater than signed
+define <1 x i128> @v1si128_cmp_gt(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+ %cmp = icmp sgt <1 x i128> %x, %y
+ %result = sext <1 x i1> %cmp to <1 x i128>
+ ret <1 x i128> %result
+; CHECK-LABEL: v1si128_cmp_gt
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <2 x i128> @v2si128_cmp_gt(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
+ %cmp = icmp sgt <2 x i128> %x, %y
+ %result = sext <2 x i1> %cmp to <2 x i128>
+ ret <2 x i128> %result
+; CHECK-LABEL: v2si128_cmp_gt
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <4 x i128> @v4si128_cmp_gt(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
+ %cmp = icmp sgt <4 x i128> %x, %y
+ %result = sext <4 x i1> %cmp to <4 x i128>
+ ret <4 x i128> %result
+; CHECK-LABEL: v4si128_cmp_gt
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <8 x i128> @v8si128_cmp_gt(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
+ %cmp = icmp sgt <8 x i128> %x, %y
+ %result = sext <8 x i1> %cmp to <8 x i128>
+ ret <8 x i128> %result
+; CHECK-LABEL: v8si128_cmp_gt
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <16 x i128> @v16si128_cmp_gt(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
+ %cmp = icmp sgt <16 x i128> %x, %y
+ %result = sext <16 x i1> %cmp to <16 x i128>
+ ret <16 x i128> %result
+; CHECK-LABEL: v16si128_cmp_gt
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+; Greater than unsigned
+define <1 x i128> @v1ui128_cmp_gt(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+ %cmp = icmp ugt <1 x i128> %x, %y
+ %result = sext <1 x i1> %cmp to <1 x i128>
+ ret <1 x i128> %result
+; CHECK-LABEL: v1ui128_cmp_gt
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <2 x i128> @v2ui128_cmp_gt(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
+ %cmp = icmp ugt <2 x i128> %x, %y
+ %result = sext <2 x i1> %cmp to <2 x i128>
+ ret <2 x i128> %result
+; CHECK-LABEL: v2ui128_cmp_gt
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <4 x i128> @v4ui128_cmp_gt(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
+ %cmp = icmp ugt <4 x i128> %x, %y
+ %result = sext <4 x i1> %cmp to <4 x i128>
+ ret <4 x i128> %result
+; CHECK-LABEL: v4ui128_cmp_gt
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <8 x i128> @v8ui128_cmp_gt(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
+ %cmp = icmp ugt <8 x i128> %x, %y
+ %result = sext <8 x i1> %cmp to <8 x i128>
+ ret <8 x i128> %result
+; CHECK-LABEL: v8ui128_cmp_gt
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <16 x i128> @v16ui128_cmp_gt(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
+ %cmp = icmp ugt <16 x i128> %x, %y
+ %result = sext <16 x i1> %cmp to <16 x i128>
+ ret <16 x i128> %result
+; CHECK-LABEL: v16ui128_cmp_gt
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+; Check the intrinsics also
+declare <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>, <1 x i128>) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>, <1 x i128>) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>, <1 x i128>) nounwind readnone
+
+define <1 x i128> @test_vcmpequq(<1 x i128> %x, <1 x i128> %y) {
+ %tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> %x, <1 x i128> %y)
+ ret <1 x i128> %tmp
+; CHECK-LABEL: test_vcmpequq:
+; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <1 x i128> @test_vcmpgtsq(<1 x i128> %x, <1 x i128> %y) {
+ %tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> %x, <1 x i128> %y)
+ ret <1 x i128> %tmp
+; CHECK-LABEL: test_vcmpgtsq
+; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}
+
+define <1 x i128> @test_vcmpgtuq(<1 x i128> %x, <1 x i128> %y) {
+ %tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> %x, <1 x i128> %y)
+ ret <1 x i128> %tmp
+; CHECK-LABEL: test_vcmpgtuq
+; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+}