[PowerPC][test] Add explicit dso_local to definitions in ELF static relocation model...

TargetMachine::shouldAssumeDSOLocal currently implies dso_local for such definitions.

Adding explicit dso_local makes these tests align with the clang -fpic behavior
and allow the removal of the TargetMachine::shouldAssumeDSOLocal special case.

Rewrite preemption.ll to dsolocal-static.ll and dsolocal-pic.ll, and add
"PIC Level" metadata.

diff --git a/llvm/test/CodeGen/PowerPC/alias.ll b/llvm/test/CodeGen/PowerPC/alias.ll
index b8136ef..4cc8883 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/alias.ll
+++ b/llvm/test/CodeGen/PowerPC/alias.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -code-model=medium| FileCheck --check-prefix=CHECK --check-prefix=MEDIUM %s
 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -code-model=large | FileCheck --check-prefix=CHECK --check-prefix=LARGE %s
 
-@foo = global i32 42
-@fooa = alias i32, i32* @foo
+@foo = dso_local global i32 42
+@fooa = dso_local alias i32, i32* @foo
 
-@foo2 = global i64 42
-@foo2a = alias i64, i64* @foo2
+@foo2 = dso_local global i64 42
+@foo2a = dso_local alias i64, i64* @foo2
 
 ; CHECK-LABEL: bar:
-define i32 @bar() {
+define dso_local i32 @bar() {
 ; MEDIUM: addis 3, 2, fooa@toc@ha
 ; LARGE: addis 3, 2, .L[[L0:.*]]@toc@ha
   %a = load i32, i32* @fooa

diff --git a/llvm/test/CodeGen/PowerPC/atomics-constant.ll b/llvm/test/CodeGen/PowerPC/atomics-constant.ll
index cc44289..80f84d8 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/atomics-constant.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-constant.ll
@@ -3,7 +3,7 @@
 
 target triple = "powerpc64le-unknown-linux-gnu"
 
-@a = constant i64 zeroinitializer
+@a = dso_local constant i64 zeroinitializer
 
 define i64 @foo() {
 ; CHECK-LABEL: foo:

diff --git a/llvm/test/CodeGen/PowerPC/dsolocal-pic.ll b/llvm/test/CodeGen/PowerPC/dsolocal-pic.ll
new file mode 100644 (file)
index 0000000..0a85d5b
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/dsolocal-pic.ll
@@ -0,0 +1,124 @@
+; RUN: llc -mtriple=ppc64le -relocation-model=pic < %s | FileCheck %s
+
+@default = global i32 55
+define dso_local i32* @get_default_global() {
+; CHECK-LABEL: get_default_global:
+; CHECK:         addis 3, 2, .LC{{.*}}@toc@ha
+; CHECK-NEXT:    ld 3, .LC{{.*}}@toc@l(3)
+; CHECK-NEXT:    blr
+  ret i32* @default
+}
+
+@local_global = dso_local global i32 55
+define dso_local i32* @get_local_global() {
+; CHECK-LABEL: get_local_global:
+; CHECK:         addis 3, 2, local_global@toc@ha
+; CHECK-NEXT:    addi 3, 3, local_global@toc@l
+; CHECK-NEXT:    blr
+  ret i32* @local_global
+}
+
+@preemptable_global = dso_preemptable global i32 42
+define dso_local i32* @get_preemptable_global() {
+; CHECK-LABEL: get_preemptable_global:
+; CHECK:         addis 3, 2, .LC{{.*}}@toc@ha
+; CHECK-NEXT:    ld 3, .LC{{.*}}@toc@l(3)
+; CHECK-NEXT:    blr
+  ret i32* @preemptable_global
+}
+
+
+@external_default_global = external global i32
+define dso_local i32* @get_external_default_global() {
+; CHECK-LABEL: get_external_default_global:
+; CHECK:         addis 3, 2, .LC{{.*}}@toc@ha
+; CHECK-NEXT:    ld 3, .LC{{.*}}@toc@l(3)
+; CHECK-NEXT:    blr
+  ret i32* @external_default_global
+}
+
+@external_local_global = external dso_local global i32
+define dso_local i32* @get_external_local_global() {
+; CHECK-LABEL: get_external_local_global:
+; CHECK:       addis 3, 2, external_local_global@toc@ha
+; CHECK:       addi 3, 3, external_local_global@toc@l
+; CHECK:       blr
+  ret i32* @external_local_global
+}
+
+@external_preemptable_global = external dso_preemptable global i32
+define dso_local i32* @get_external_preemptable_global() {
+; CHECK-LABEL: get_external_preemptable_global:
+; CHECK:         addis 3, 2, .LC{{.*}}@toc@ha
+; CHECK-NEXT:    ld 3, .LC{{.*}}@toc@l(3)
+; CHECK-NEXT:    blr
+  ret i32* @external_preemptable_global
+}
+
+
+; functions
+define signext i32 @default_function(i32 %i) {
+  ret i32 %i
+}
+define dso_local signext i32 @default_function_caller(i32 %i) {
+; CHECK-LABEL: default_function_caller:
+; CHECK:         bl default_function
+; CHECK-NEXT:    nop
+  %call = notail call signext i32 @default_function(i32 signext %i)
+  ret i32 %call
+}
+
+define dso_local signext i32 @local_function(i32 %i) {
+  ret i32 %i
+}
+define dso_local signext i32 @local_function_caller(i32 %i) {
+; CHECK-LABEL: local_function_caller:
+; CHECK:         bl local_function
+; CHECK-NOT:     nop
+; CHECK:         blr
+  %call = notail call signext i32 @local_function(i32 signext %i)
+  ret i32 %call
+}
+
+define dso_preemptable signext i32 @preemptable_function(i32 %i) {
+  ret i32 %i
+}
+define dso_local signext i32 @preemptable_function_caller(i32 %i) {
+; CHECK-LABEL: preemptable_function_caller:
+; CHECK:         bl preemptable_function
+; CHECK-NEXT:    nop
+  %call = notail call signext i32 @preemptable_function(i32 signext %i)
+  ret i32 %call
+}
+
+
+declare i32 @external_default_function(i32 %i)
+define dso_local i32 @external_default_function_caller(i32 %i) {
+; CHECK-LABEL: external_default_function_caller:
+; CHECK:         bl external_default_function
+; CHECK-NEXT:    nop
+; CHECK:         blr
+  %call = notail call signext i32 @external_default_function(i32 signext %i)
+  ret i32 %call
+}
+
+declare dso_local i32 @external_local_function(i32 %i)
+define dso_local i32 @external_local_function_caller(i32 %i) {
+; CHECK-LABEL: external_local_function_caller:
+; CHECK:         bl external_local_function
+; CHECK-NEXT:    nop
+  %call = notail call signext i32 @external_local_function(i32 signext %i)
+  ret i32 %call
+}
+
+declare dso_preemptable i32 @external_preemptable_function(i32 %i)
+define dso_local i32 @external_preemptable_function_caller(i32 %i) {
+; CHECK-LABEL: external_preemptable_function_caller:
+; CHECK:         bl external_preemptable_function
+; CHECK-NEXT:    nop
+  %call = notail call signext i32 @external_preemptable_function(i32 signext %i)
+  ret i32 %call
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"PIC Level", i32 1}

diff --git a/llvm/test/CodeGen/PowerPC/dsolocal-static.ll b/llvm/test/CodeGen/PowerPC/dsolocal-static.ll
new file mode 100644 (file)
index 0000000..a4ef632
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/dsolocal-static.ll
@@ -0,0 +1,123 @@
+; RUN: llc -mtriple=ppc64le -relocation-model=static < %s | FileCheck %s
+
+@default = global i32 55
+define dso_local i32* @get_default_global() {
+; CHECK-LABEL: get_default_global:
+; CHECK:         addis 3, 2, default@toc@ha
+; CHECK-NEXT:    addi 3, 3, default@toc@l
+; CHECK-NEXT:    blr
+  ret i32* @default
+}
+
+@local_global = dso_local global i32 55
+define dso_local i32* @get_local_global() {
+; CHECK-LABEL: get_local_global:
+; CHECK:         addis 3, 2, local_global@toc@ha
+; CHECK-NEXT:    addi 3, 3, local_global@toc@l
+; CHECK-NEXT:    blr
+  ret i32* @local_global
+}
+
+@preemptable_global = dso_preemptable global i32 42
+define dso_local i32* @get_preemptable_global() {
+; CHECK-LABEL: get_preemptable_global:
+; CHECK:         addis 3, 2, preemptable_global@toc@ha
+; CHECK-NEXT:    addi 3, 3, preemptable_global@toc@l
+; CHECK-NEXT:    blr
+  ret i32* @preemptable_global
+}
+
+
+@external_default_global = external global i32
+define dso_local i32* @get_external_default_global() {
+; CHECK-LABEL: get_external_default_global:
+; CHECK:         addis 3, 2, .LC{{.*}}@toc@ha
+; CHECK-NEXT:    ld 3, .LC{{.*}}@toc@l(3)
+; CHECK-NEXT:    blr
+  ret i32* @external_default_global
+}
+
+@external_local_global = external dso_local global i32
+define dso_local i32* @get_external_local_global() {
+; CHECK-LABEL: get_external_local_global:
+; CHECK:         addis 3, 2, external_local_global@toc@ha
+; CHECK-NEXT:    addi 3, 3, external_local_global@toc@l
+; CHECK-NEXT:    blr
+  ret i32* @external_local_global
+}
+
+@external_preemptable_global = external dso_preemptable global i32
+define dso_local i32* @get_external_preemptable_global() {
+; CHECK-LABEL: get_external_preemptable_global:
+; CHECK:         addis 3, 2, .LC{{.*}}@toc@ha
+; CHECK-NEXT:    ld 3, .LC{{.*}}@toc@l(3)
+; CHECK-NEXT:    blr
+  ret i32* @external_preemptable_global
+}
+
+
+; functions
+define signext i32 @default_function(i32 %i) {
+  ret i32 %i
+}
+define dso_local signext i32 @default_function_caller(i32 %i) {
+; CHECK-LABEL: default_function_caller:
+; CHECK:         bl default_function
+; CHECK-NOT:     nop
+; CHECK:         blr
+  %call = notail call signext i32 @default_function(i32 signext %i)
+  ret i32 %call
+}
+
+define dso_local signext i32 @local_function(i32 %i) {
+  ret i32 %i
+}
+define dso_local signext i32 @local_function_caller(i32 %i) {
+; CHECK-LABEL: local_function_caller:
+; CHECK:         bl local_function
+; CHECK-NOT:     nop
+; CHECK:         blr
+  %call = notail call signext i32 @local_function(i32 signext %i)
+  ret i32 %call
+}
+
+define dso_preemptable signext i32 @preemptable_function(i32 %i) {
+  ret i32 %i
+}
+define dso_local signext i32 @preemptable_function_caller(i32 %i) {
+; CHECK-LABEL: preemptable_function_caller:
+; CHECK:         bl preemptable_function
+; CHECK-NOT:     nop
+; CHECK:         blr
+  %call = notail call signext i32 @preemptable_function(i32 signext %i)
+  ret i32 %call
+}
+
+
+declare i32 @external_default_function(i32 %i)
+define dso_local i32 @external_default_function_caller(i32 %i) {
+; CHECK-LABEL: external_default_function_caller:
+; CHECK:         bl external_default_function
+; CHECK-NEXT:    nop
+; CHECK:         blr
+  %call = notail call signext i32 @external_default_function(i32 signext %i)
+  ret i32 %call
+}
+
+declare dso_local i32 @external_local_function(i32 %i)
+define dso_local i32 @external_local_function_caller(i32 %i) {
+; CHECK-LABEL: external_local_function_caller:
+; CHECK:         bl external_local_function
+; CHECK-NEXT:    nop
+  %call = notail call signext i32 @external_local_function(i32 signext %i)
+  ret i32 %call
+}
+
+declare dso_preemptable i32 @external_preemptable_function(i32 %i)
+define dso_local i32 @external_preemptable_function_caller(i32 %i) {
+; CHECK-LABEL: external_preemptable_function_caller:
+; CHECK:         bl external_preemptable_function
+; CHECK-NEXT:    nop
+  %call = notail call signext i32 @external_preemptable_function(i32 signext %i)
+  ret i32 %call
+}

diff --git a/llvm/test/CodeGen/PowerPC/elf-common.ll b/llvm/test/CodeGen/PowerPC/elf-common.ll
index 722b480..3adeabb 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/elf-common.ll
+++ b/llvm/test/CodeGen/PowerPC/elf-common.ll
@@ -3,14 +3,12 @@
 ; RUN:    | FileCheck -check-prefix=NOOPT %s
 ; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 < %s | FileCheck -check-prefix=STATIC %s
-; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:     -mcpu=pwr8 < %s | FileCheck -check-prefix=PIC %s
 
-; Test correct code generation for static and pic for loading and storing a common symbol
+;; Test loading and storing a common symbol for static relocation model.
 
-@comm_glob = common global i32 0, align 4
+@comm_glob = common dso_local global i32 0, align 4
 
-define signext i32 @test_comm() nounwind {
+define dso_local signext i32 @test_comm() nounwind {
 ; NOOPT-LABEL: test_comm:
 ; NOOPT:       # %bb.0: # %entry
 ; NOOPT-NEXT:    addis 3, 2, comm_glob@toc@ha
@@ -28,15 +26,6 @@ define signext i32 @test_comm() nounwind {
 ; STATIC-NEXT:    addi 5, 3, 1
 ; STATIC-NEXT:    stw 5, comm_glob@toc@l(4)
 ; STATIC-NEXT:    blr
-;
-; PIC-LABEL: test_comm:
-; PIC:       # %bb.0: # %entry
-; PIC-NEXT:    addis 3, 2, .LC0@toc@ha
-; PIC-NEXT:    ld 4, .LC0@toc@l(3)
-; PIC-NEXT:    lwa 3, 0(4)
-; PIC-NEXT:    addi 5, 3, 1
-; PIC-NEXT:    stw 5, 0(4)
-; PIC-NEXT:    blr
 entry:
   %0 = load i32, i32* @comm_glob, align 4
   %inc = add nsw i32 %0, 1

diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll
index 587cf32..fa8463f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/f128-arith.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll
@@ -6,7 +6,7 @@
 ; RUN:   -check-prefix=CHECK-P8
 
 ; Function Attrs: norecurse nounwind
-define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpAdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -42,7 +42,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @qpSub(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpSub(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpSub:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -78,7 +78,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @qpMul(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpMul(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpMul:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -114,7 +114,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @qpDiv(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpDiv(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpDiv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -149,7 +149,7 @@ entry:
   ret void
 }
 
-define void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
+define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
 ; CHECK-LABEL: testLdNSt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r3, r3, 4
@@ -176,7 +176,7 @@ entry:
   ret void
 }
 
-define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpSqrt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -212,7 +212,7 @@ entry:
 }
 declare fp128 @llvm.sqrt.f128(fp128 %Val)
 
-define void @qpCpsgn(fp128* nocapture readonly %a, fp128* nocapture readonly %b,
+define dso_local void @qpCpsgn(fp128* nocapture readonly %a, fp128* nocapture readonly %b,
 ; CHECK-LABEL: qpCpsgn:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -247,7 +247,7 @@ entry:
 }
 declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
 
-define void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpAbs:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -275,7 +275,7 @@ entry:
 }
 declare fp128 @llvm.fabs.f128(fp128 %Val)
 
-define void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpNAbs:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -309,7 +309,7 @@ entry:
 
 }
 
-define void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpNeg:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -718,7 +718,7 @@ entry:
 }
 declare fp128     @llvm.exp2.f128(fp128 %Val)
 
-define void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b,
+define dso_local void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b,
 ; CHECK-LABEL: qp_powi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
@@ -771,8 +771,8 @@ entry:
 }
 declare fp128 @llvm.powi.f128(fp128 %Val, i32 %power)
 
-@a = common global fp128 0xL00000000000000000000000000000000, align 16
-@b = common global fp128 0xL00000000000000000000000000000000, align 16
+@a = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
+@b = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
 
 define fp128 @qp_frem() #0 {
 ; CHECK-LABEL: qp_frem:
@@ -821,7 +821,7 @@ entry:
   ret fp128 %rem
 }
 
-define void @qpCeil(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpCeil(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpCeil:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -856,7 +856,7 @@ entry:
 }
 declare fp128 @llvm.ceil.f128(fp128 %Val)
 
-define void @qpFloor(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpFloor(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpFloor:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -891,7 +891,7 @@ entry:
 }
 declare fp128 @llvm.floor.f128(fp128 %Val)
 
-define void @qpTrunc(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpTrunc(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpTrunc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -926,7 +926,7 @@ entry:
 }
 declare fp128 @llvm.trunc.f128(fp128 %Val)
 
-define void @qpRound(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpRound(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpRound:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -961,7 +961,7 @@ entry:
 }
 declare fp128 @llvm.round.f128(fp128 %Val)
 
-define void @qpLRound(fp128* nocapture readonly %a, i32* nocapture %res) {
+define dso_local void @qpLRound(fp128* nocapture readonly %a, i32* nocapture %res) {
 ; CHECK-LABEL: qpLRound:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
@@ -1009,7 +1009,7 @@ entry:
 }
 declare i32 @llvm.lround.f128(fp128 %Val)
 
-define void @qpLLRound(fp128* nocapture readonly %a, i64* nocapture %res) {
+define dso_local void @qpLLRound(fp128* nocapture readonly %a, i64* nocapture %res) {
 ; CHECK-LABEL: qpLLRound:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
@@ -1057,7 +1057,7 @@ entry:
 }
 declare i64 @llvm.llround.f128(fp128 %Val)
 
-define void @qpRint(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpRint(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpRint:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -1092,7 +1092,7 @@ entry:
 }
 declare fp128 @llvm.rint.f128(fp128 %Val)
 
-define void @qpLRint(fp128* nocapture readonly %a, i32* nocapture %res) {
+define dso_local void @qpLRint(fp128* nocapture readonly %a, i32* nocapture %res) {
 ; CHECK-LABEL: qpLRint:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
@@ -1140,7 +1140,7 @@ entry:
 }
 declare i32 @llvm.lrint.f128(fp128 %Val)
 
-define void @qpLLRint(fp128* nocapture readonly %a, i64* nocapture %res) {
+define dso_local void @qpLLRint(fp128* nocapture readonly %a, i64* nocapture %res) {
 ; CHECK-LABEL: qpLLRint:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
@@ -1188,7 +1188,7 @@ entry:
 }
 declare i64 @llvm.llrint.f128(fp128 %Val)
 
-define void @qpNearByInt(fp128* nocapture readonly %a, fp128* nocapture %res) {
+define dso_local void @qpNearByInt(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpNearByInt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
@@ -1223,7 +1223,7 @@ entry:
 }
 declare fp128 @llvm.nearbyint.f128(fp128 %Val)
 
-define void @qpFMA(fp128* %a, fp128* %b, fp128* %c, fp128* %res) {
+define dso_local void @qpFMA(fp128* %a, fp128* %b, fp128* %c, fp128* %res) {
 ; CHECK-LABEL: qpFMA:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)

diff --git a/llvm/test/CodeGen/PowerPC/f128-compare.ll b/llvm/test/CodeGen/PowerPC/f128-compare.ll
index e8170b4..36b0720 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/f128-compare.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-compare.ll
@@ -5,11 +5,11 @@
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
-@a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
-@b_qp = common global fp128 0xL00000000000000000000000000000000, align 16
+@a_qp = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
+@b_qp = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @greater_qp() {
+define dso_local signext i32 @greater_qp() {
 ; CHECK-LABEL: greater_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -57,7 +57,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @less_qp() {
+define dso_local signext i32 @less_qp() {
 ; CHECK-LABEL: less_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -103,7 +103,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @greater_eq_qp() {
+define dso_local signext i32 @greater_eq_qp() {
 ; CHECK-LABEL: greater_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -150,7 +150,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @less_eq_qp() {
+define dso_local signext i32 @less_eq_qp() {
 ; CHECK-LABEL: less_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -199,7 +199,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @equal_qp() {
+define dso_local signext i32 @equal_qp() {
 ; CHECK-LABEL: equal_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -246,7 +246,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @not_greater_qp() {
+define dso_local signext i32 @not_greater_qp() {
 ; CHECK-LABEL: not_greater_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -295,7 +295,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @not_less_qp() {
+define dso_local signext i32 @not_less_qp() {
 ; CHECK-LABEL: not_less_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -342,7 +342,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @not_greater_eq_qp() {
+define dso_local signext i32 @not_greater_eq_qp() {
 ; CHECK-LABEL: not_greater_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -389,7 +389,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @not_less_eq_qp() {
+define dso_local signext i32 @not_less_eq_qp() {
 ; CHECK-LABEL: not_less_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
@@ -438,7 +438,7 @@ entry:
 }
 
 ; Function Attrs: noinline nounwind optnone
-define signext i32 @not_equal_qp() {
+define dso_local signext i32 @not_equal_qp() {
 ; CHECK-LABEL: not_equal_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha

diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
index cb9e1c9..652f145 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
@@ -5,20 +5,20 @@
 ; This test verifies that load/store instructions are properly generated,
 ; and that they pass MI verification.
 
-@a = global i8 1, align 1
-@b = global i16 2, align 2
-@c = global i32 4, align 4
-@d = global i64 8, align 8
-@e = global float 1.25, align 4
-@f = global double 3.5, align 8
+@a = dso_local global i8 1, align 1
+@b = dso_local global i16 2, align 2
+@c = dso_local global i32 4, align 4
+@d = dso_local global i64 8, align 8
+@e = dso_local global float 1.25, align 4
+@f = dso_local global double 3.5, align 8
 
 %struct.s = type<{ i8, i32 }>
 %struct.t = type<{ i8, i64 }>
 
-@g = global %struct.s <{ i8 1, i32 2 }>, align 1
-@h = global %struct.t <{ i8 1, i64 2 }>, align 1
+@g = dso_local global %struct.s <{ i8 1, i32 2 }>, align 1
+@h = dso_local global %struct.t <{ i8 1, i64 2 }>, align 1
 
-@i = common global [8192 x i64] zeroinitializer, align 8
+@i = common dso_local global [8192 x i64] zeroinitializer, align 8
 
 ; load
 
@@ -40,7 +40,7 @@ define i16 @t2() nounwind {
   ret i16 %2
 }
 
-define i32 @t3() nounwind {
+define dso_local i32 @t3() nounwind {
 ; ELF64: t3
   %1 = load i32, i32* @c, align 4
 ; ELF64: lwz
@@ -58,7 +58,7 @@ define i64 @t4() nounwind {
   ret i64 %2
 }
 
-define float @t5() nounwind {
+define dso_local float @t5() nounwind {
 ; ELF64: t5
 ; SPE: t5
   %1 = load float, float* @e, align 4
@@ -70,7 +70,7 @@ define float @t5() nounwind {
   ret float %2
 }
 
-define double @t6() nounwind {
+define dso_local double @t6() nounwind {
 ; ELF64: t6
 ; SPE: t6
   %1 = load double, double* @f, align 8
@@ -86,7 +86,7 @@ define double @t6() nounwind {
 
 ; store
 
-define void @t7(i8 %v) nounwind {
+define dso_local void @t7(i8 %v) nounwind {
 ; ELF64: t7
   %1 = add nsw i8 %v, 1
   store i8 %1, i8* @a, align 1
@@ -97,7 +97,7 @@ define void @t7(i8 %v) nounwind {
   ret void
 }
 
-define void @t8(i16 %v) nounwind {
+define dso_local void @t8(i16 %v) nounwind {
 ; ELF64: t8
   %1 = add nsw i16 %v, 1
   store i16 %1, i16* @b, align 2
@@ -108,7 +108,7 @@ define void @t8(i16 %v) nounwind {
   ret void
 }
 
-define void @t9(i32 %v) nounwind {
+define dso_local void @t9(i32 %v) nounwind {
 ; ELF64: t9
   %1 = add nsw i32 %v, 1
   store i32 %1, i32* @c, align 4
@@ -119,7 +119,7 @@ define void @t9(i32 %v) nounwind {
   ret void
 }
 
-define void @t10(i64 %v) nounwind {
+define dso_local void @t10(i64 %v) nounwind {
 ; ELF64: t10
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* @d, align 4
@@ -130,7 +130,7 @@ define void @t10(i64 %v) nounwind {
   ret void
 }
 
-define void @t11(float %v) nounwind {
+define dso_local void @t11(float %v) nounwind {
 ; ELF64: t11
 ; SPE: t11
   %1 = fadd float %v, 1.0
@@ -142,7 +142,7 @@ define void @t11(float %v) nounwind {
   ret void
 }
 
-define void @t12(double %v) nounwind {
+define dso_local void @t12(double %v) nounwind {
 ; ELF64: t12
 ; SPE: t12
   %1 = fadd double %v, 1.0
@@ -180,7 +180,7 @@ define i64 @t14() nounwind {
 }
 
 ;; std requires an offset divisible by 4, so we need stdx here.
-define void @t15(i64 %v) nounwind {
+define dso_local void @t15(i64 %v) nounwind {
 ; ELF64: t15
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
@@ -205,7 +205,7 @@ define i64 @t16() nounwind {
 }
 
 ;; std requires an offset that fits in 16 bits, so we need stdx here.
-define void @t17(i64 %v) nounwind {
+define dso_local void @t17(i64 %v) nounwind {
 ; ELF64: t17
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8

diff --git a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
index 0953617..351f13c 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
+++ b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
@@ -5,27 +5,27 @@
 ; if the load value isn't used by any other operations,
 ; then consider transforming the pair to integer load / store operations
 
-@a1 = local_unnamed_addr global double 0.000000e+00, align 8
-@a2 = local_unnamed_addr global double 0.000000e+00, align 8
-@a3 = local_unnamed_addr global double 0.000000e+00, align 8
-@a4 = local_unnamed_addr global double 0.000000e+00, align 8
-@a5 = local_unnamed_addr global double 0.000000e+00, align 8
-@a6 = local_unnamed_addr global double 0.000000e+00, align 8
-@a7 = local_unnamed_addr global double 0.000000e+00, align 8
-@a8 = local_unnamed_addr global double 0.000000e+00, align 8
-@a9 = local_unnamed_addr global double 0.000000e+00, align 8
-@a10 = local_unnamed_addr global double 0.000000e+00, align 8
-@a11 = local_unnamed_addr global double 0.000000e+00, align 8
-@a12 = local_unnamed_addr global double 0.000000e+00, align 8
-@a13 = local_unnamed_addr global double 0.000000e+00, align 8
-@a14 = local_unnamed_addr global double 0.000000e+00, align 8
-@a15 = local_unnamed_addr global double 0.000000e+00, align 8
-@a16 = local_unnamed_addr global ppc_fp128 0xM00000000000000000000000000000000, align 16
-@a17 = local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16
+@a1 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a2 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a3 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a4 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a5 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a6 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a7 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a8 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a9 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a10 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a11 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a12 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a13 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a14 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a15 = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@a16 = dso_local local_unnamed_addr global ppc_fp128 0xM00000000000000000000000000000000, align 16
+@a17 = dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16
 
 ; Because this test function is trying to pass float argument by stack,
 ; so the fpr is only used to load/store float argument
-define signext i32 @test() nounwind {
+define dso_local signext i32 @test() nounwind {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0

diff --git a/llvm/test/CodeGen/PowerPC/fma-combine.ll b/llvm/test/CodeGen/PowerPC/fma-combine.ll
index c07cb1c..097d794 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/fma-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/fma-combine.ll
@@ -5,7 +5,7 @@
 ; RUN:     -enable-unsafe-fp-math -mattr=-vsx < %s | FileCheck -check-prefix=CHECK-FAST-NOVSX %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
-define double @fma_combine1(double %a, double %b, double %c) {
+define dso_local double @fma_combine1(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine1:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
@@ -29,7 +29,7 @@ entry:
   ret double %add
 }
 
-define double @fma_combine2(double %a, double %b, double %c) {
+define dso_local double @fma_combine2(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine2:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xsnmaddadp 1, 2, 3
@@ -53,9 +53,9 @@ entry:
   ret double %add
 }
 
-@v = common local_unnamed_addr global double 0.000000e+00, align 8
-@z = common local_unnamed_addr global double 0.000000e+00, align 8
-define double @fma_combine_two_uses(double %a, double %b, double %c) {
+@v = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
+@z = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
+define dso_local double @fma_combine_two_uses(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine_two_uses:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xsnegdp 0, 1
@@ -101,7 +101,7 @@ entry:
   ret double %add
 }
 
-define double @fma_combine_one_use(double %a, double %b, double %c) {
+define dso_local double @fma_combine_one_use(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine_one_use:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xsnegdp 0, 1
@@ -138,7 +138,7 @@ entry:
   ret double %add
 }
 
-define float @fma_combine_no_ice() {
+define dso_local float @fma_combine_no_ice() {
 ; CHECK-FAST-LABEL: fma_combine_no_ice:
 ; CHECK-FAST:       # %bb.0:
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
@@ -198,7 +198,7 @@ define float @fma_combine_no_ice() {
 }
 
 ; This would crash while trying getNegatedExpression().
-define double @getNegatedExpression_crash(double %x, double %y) {
+define dso_local double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK-FAST-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST:       # %bb.0:
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
@@ -240,7 +240,7 @@ define double @getNegatedExpression_crash(double %x, double %y) {
   ret double %fma1
 }
 
-define double @fma_flag_propagation(double %a) {
+define dso_local double @fma_flag_propagation(double %a) {
 ; CHECK-FAST-LABEL: fma_flag_propagation:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xxlxor 1, 1, 1
@@ -262,7 +262,7 @@ entry:
   ret double %1
 }
 
-define double @neg_fma_flag_propagation(double %a) {
+define dso_local double @neg_fma_flag_propagation(double %a) {
 ; CHECK-FAST-LABEL: neg_fma_flag_propagation:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xxlxor 1, 1, 1
@@ -313,7 +313,7 @@ entry:
   ret <2 x double> %0
 }
 
-define double @fma_combine_const(double %a, double %b) {
+define dso_local double @fma_combine_const(double %a, double %b) {
 ; CHECK-FAST-LABEL: fma_combine_const:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI9_0@toc@ha

diff --git a/llvm/test/CodeGen/PowerPC/func-addr.ll b/llvm/test/CodeGen/PowerPC/func-addr.ll
index ec7045d..2556a53 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/func-addr.ll
+++ b/llvm/test/CodeGen/PowerPC/func-addr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple powerpc64-linux < %s | FileCheck %s
 ; RUN: llc -relocation-model=static -verify-machineinstrs -O0 -mtriple powerpc64-linux < %s | FileCheck %s
 
-define void @foo()  {
+define dso_local void @foo()  {
   ret void
 }
 declare i32 @bar(i8*)

diff --git a/llvm/test/CodeGen/PowerPC/macro-fusion.ll b/llvm/test/CodeGen/PowerPC/macro-fusion.ll
index 0e9ac85..0225204 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/macro-fusion.ll
+++ b/llvm/test/CodeGen/PowerPC/macro-fusion.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-misched -debug-only=machine-scheduler \
 ; RUN:  -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-P8
 
-@m = local_unnamed_addr global i64 0, align 8
+@m = dso_local local_unnamed_addr global i64 0, align 8
 
 define i64 @fuse_addis_ld() {
 entry:

diff --git a/llvm/test/CodeGen/PowerPC/mcm-11.ll b/llvm/test/CodeGen/PowerPC/mcm-11.ll
index ecab7e1..e83c7b2 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/mcm-11.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-11.ll
@@ -6,9 +6,9 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-@gi = global i32 5, align 4
+@gi = dso_local global i32 5, align 4
 
-define signext i32 @test_file_static() nounwind {
+define dso_local signext i32 @test_file_static() nounwind {
 entry:
   %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1

diff --git a/llvm/test/CodeGen/PowerPC/mcm-3.ll b/llvm/test/CodeGen/PowerPC/mcm-3.ll
index 562cbff..27ea250 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/mcm-3.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-3.ll
@@ -7,9 +7,9 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-@gi = global i32 5, align 4
+@gi = dso_local global i32 5, align 4
 
-define signext i32 @test_file_static() nounwind {
+define dso_local signext i32 @test_file_static() nounwind {
 entry:
   %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1

diff --git a/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll b/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll
index ce30580..302b421 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-obj-2.ll
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 @test_fn_static.si = internal global i32 0, align 4
 
-define signext i32 @test_fn_static() nounwind {
+define dso_local signext i32 @test_fn_static() nounwind {
 entry:
   %0 = load i32, i32* @test_fn_static.si, align 4
   %inc = add nsw i32 %0, 1
@@ -25,9 +25,9 @@ entry:
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
 
-@gi = global i32 5, align 4
+@gi = dso_local global i32 5, align 4
 
-define signext i32 @test_file_static() nounwind {
+define dso_local signext i32 @test_file_static() nounwind {
 entry:
   %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1

diff --git a/llvm/test/CodeGen/PowerPC/mcm-obj.ll b/llvm/test/CodeGen/PowerPC/mcm-obj.ll
index 452aa83..e7422ab 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/mcm-obj.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-obj.ll
@@ -16,7 +16,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 @ei = external global i32
 
-define signext i32 @test_external() nounwind {
+define dso_local signext i32 @test_external() nounwind {
 entry:
   %0 = load i32, i32* @ei, align 4
   %inc = add nsw i32 %0, 1
@@ -29,8 +29,8 @@ entry:
 ;
 ; MEDIUM:      Relocations [
 ; MEDIUM:        Section {{.*}} .rela.text {
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc 0x0
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc 0x0
 ;
 ; LARGE:       Relocations [
 ; LARGE:         Section {{.*}} .rela.text {
@@ -39,7 +39,7 @@ entry:
 
 @test_fn_static.si = internal global i32 0, align 4
 
-define signext i32 @test_fn_static() nounwind {
+define dso_local signext i32 @test_fn_static() nounwind {
 entry:
   %0 = load i32, i32* @test_fn_static.si, align 4
   %inc = add nsw i32 %0, 1
@@ -50,8 +50,8 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing function-scoped variable si.
 ;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .bss 0x0
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO .bss 0x0
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing function-scoped variable si.
@@ -59,9 +59,9 @@ entry:
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
 
-@gi = global i32 5, align 4
+@gi = dso_local global i32 5, align 4
 
-define signext i32 @test_file_static() nounwind {
+define dso_local signext i32 @test_file_static() nounwind {
 entry:
   %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1
@@ -72,8 +72,8 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing file-scope variable gi.
 ;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA gi 0x0
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO gi 0x0
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing file-scope variable gi.
@@ -81,7 +81,7 @@ entry:
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
 
-define double @test_double_const() nounwind {
+define dso_local double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
@@ -89,8 +89,8 @@ entry:
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
 ; accessing a constant.
 ;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .rodata.cst8
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO .rodata.cst8
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a constant.
@@ -98,9 +98,9 @@ entry:
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
 
-@ti = common global i32 0, align 4
+@ti = common dso_local global i32 0, align 4
 
-define signext i32 @test_tentative() nounwind {
+define dso_local signext i32 @test_tentative() nounwind {
 entry:
   %0 = load i32, i32* @ti, align 4
   %inc = add nsw i32 %0, 1
@@ -110,8 +110,8 @@ entry:
 
 ; Verify generation of relocations foraccessing variable ti.
 ;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM6]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA ti 0x0
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO ti 0x0
 ;
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
@@ -130,14 +130,14 @@ declare signext i32 @foo(i32 signext)
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing function address foo.
 ;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA .toc 0x8
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS .toc 0x8
 ;
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
 
 
-define signext i32 @test_jump_table(i32 signext %i) nounwind {
+define dso_local signext i32 @test_jump_table(i32 signext %i) nounwind {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4

diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
index 99e731c..b152c1a 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -6,10 +6,10 @@
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=BE-PAIRED
 
-@f = common local_unnamed_addr global <512 x i1> zeroinitializer, align 16
-@g = common local_unnamed_addr global <256 x i1> zeroinitializer, align 16
+@f = common dso_local local_unnamed_addr global <512 x i1> zeroinitializer, align 16
+@g = common dso_local local_unnamed_addr global <256 x i1> zeroinitializer, align 16
 
-define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
+define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testLdSt:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv vs1, f@PCREL+96(0), 1
@@ -24,8 +24,8 @@ define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ;
 ; BE-PAIRED-LABEL: testLdSt:
 ; BE-PAIRED:       # %bb.0: # %entry
-; BE-PAIRED-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-PAIRED-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-PAIRED-NEXT:    addis r3, r2, f@toc@ha
+; BE-PAIRED-NEXT:    addi r3, r3, f@toc@l
 ; BE-PAIRED-NEXT:    lxv vs1, 80(r3)
 ; BE-PAIRED-NEXT:    lxv vs0, 64(r3)
 ; BE-PAIRED-NEXT:    lxv vs3, 112(r3)
@@ -43,7 +43,7 @@ entry:
   ret void
 }
 
-define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
+define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testXLdSt:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    sldi r3, r3, 6
@@ -63,9 +63,9 @@ define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ;
 ; BE-PAIRED-LABEL: testXLdSt:
 ; BE-PAIRED:       # %bb.0: # %entry
-; BE-PAIRED-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-PAIRED-NEXT:    addis r5, r2, f@toc@ha
 ; BE-PAIRED-NEXT:    sldi r3, r3, 6
-; BE-PAIRED-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-PAIRED-NEXT:    addi r5, r5, f@toc@l
 ; BE-PAIRED-NEXT:    add r6, r5, r3
 ; BE-PAIRED-NEXT:    lxvx vs0, r5, r3
 ; BE-PAIRED-NEXT:    sldi r3, r4, 6
@@ -86,7 +86,7 @@ entry:
   ret void
 }
 
-define void @testUnalignedLdSt() {
+define dso_local void @testUnalignedLdSt() {
 ; LE-PAIRED-LABEL: testUnalignedLdSt:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv vs1, f@PCREL+43(0), 1
@@ -101,9 +101,9 @@ define void @testUnalignedLdSt() {
 ;
 ; BE-PAIRED-LABEL: testUnalignedLdSt:
 ; BE-PAIRED:       # %bb.0: # %entry
-; BE-PAIRED-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-PAIRED-NEXT:    addis r3, r2, f@toc@ha
 ; BE-PAIRED-NEXT:    li r4, 11
-; BE-PAIRED-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-PAIRED-NEXT:    addi r3, r3, f@toc@l
 ; BE-PAIRED-NEXT:    lxvx vs0, r3, r4
 ; BE-PAIRED-NEXT:    li r4, 27
 ; BE-PAIRED-NEXT:    lxvx vs1, r3, r4
@@ -131,7 +131,7 @@ entry:
   ret void
 }
 
-define void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
+define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv vs1, g@PCREL+32(0), 1
@@ -142,8 +142,8 @@ define void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ;
 ; BE-PAIRED-LABEL: testLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
-; BE-PAIRED-NEXT:    addis r3, r2, .LC1@toc@ha
-; BE-PAIRED-NEXT:    ld r3, .LC1@toc@l(r3)
+; BE-PAIRED-NEXT:    addis r3, r2, g@toc@ha
+; BE-PAIRED-NEXT:    addi r3, r3, g@toc@l
 ; BE-PAIRED-NEXT:    lxv vs1, 48(r3)
 ; BE-PAIRED-NEXT:    lxv vs0, 32(r3)
 ; BE-PAIRED-NEXT:    stxv vs1, 80(r3)
@@ -157,7 +157,7 @@ entry:
   ret void
 }
 
-define void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
+define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testXLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    sldi r3, r3, 5
@@ -173,9 +173,9 @@ define void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ;
 ; BE-PAIRED-LABEL: testXLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
-; BE-PAIRED-NEXT:    addis r5, r2, .LC1@toc@ha
+; BE-PAIRED-NEXT:    addis r5, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    sldi r3, r3, 5
-; BE-PAIRED-NEXT:    ld r5, .LC1@toc@l(r5)
+; BE-PAIRED-NEXT:    addi r5, r5, g@toc@l
 ; BE-PAIRED-NEXT:    add r6, r5, r3
 ; BE-PAIRED-NEXT:    lxvx vs0, r5, r3
 ; BE-PAIRED-NEXT:    sldi r3, r4, 5
@@ -192,7 +192,7 @@ entry:
   ret void
 }
 
-define void @testUnalignedLdStPair() {
+define dso_local void @testUnalignedLdStPair() {
 ; LE-PAIRED-LABEL: testUnalignedLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv vs1, g@PCREL+11(0), 1
@@ -203,9 +203,9 @@ define void @testUnalignedLdStPair() {
 ;
 ; BE-PAIRED-LABEL: testUnalignedLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
-; BE-PAIRED-NEXT:    addis r3, r2, .LC1@toc@ha
+; BE-PAIRED-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    li r4, 11
-; BE-PAIRED-NEXT:    ld r3, .LC1@toc@l(r3)
+; BE-PAIRED-NEXT:    addi r3, r3, g@toc@l
 ; BE-PAIRED-NEXT:    lxvx vs0, r3, r4
 ; BE-PAIRED-NEXT:    li r4, 27
 ; BE-PAIRED-NEXT:    lxvx vs1, r3, r4

diff --git a/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll
index 72b4353..76fd43b 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setbc1(i8 %a) {
+define dso_local signext i32 @setbc1(i8 %a) {
 ; CHECK-LABEL: setbc1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb r3, r3
@@ -30,7 +30,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc2(i32 %a) {
+define dso_local signext i32 @setbc2(i32 %a) {
 ; CHECK-LABEL: setbc2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -42,7 +42,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc3(i64 %a) {
+define dso_local signext i32 @setbc3(i64 %a) {
 ; CHECK-LABEL: setbc3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -54,7 +54,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc4(i16 %a) {
+define dso_local signext i32 @setbc4(i16 %a) {
 ; CHECK-LABEL: setbc4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsh r3, r3
@@ -117,7 +117,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setbc9(i8 %a) {
+define dso_local void @setbc9(i8 %a) {
 ; CHECK-LE-LABEL: setbc9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsb r3, r3
@@ -128,12 +128,11 @@ define void @setbc9(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setbc9:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, 1
@@ -142,7 +141,7 @@ entry:
   ret void
 }
 
-define void @setbc10(i32 %a) {
+define dso_local void @setbc10(i32 %a) {
 ; CHECK-LE-LABEL: setbc10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -152,11 +151,10 @@ define void @setbc10(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setbc10:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, 1
@@ -165,7 +163,7 @@ entry:
   ret void
 }
 
-define void @setbc11(i64 %a) {
+define dso_local void @setbc11(i64 %a) {
 ; CHECK-LE-LABEL: setbc11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -175,11 +173,10 @@ define void @setbc11(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setbc11:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 1
@@ -188,7 +185,7 @@ entry:
   ret void
 }
 
-define void @setbc12(i16 %a) {
+define dso_local void @setbc12(i16 %a) {
 ; CHECK-LE-LABEL: setbc12:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsh r3, r3
@@ -199,12 +196,11 @@ define void @setbc12(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setbc12:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, 1
@@ -213,7 +209,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbc13(i8 %a) {
+define dso_local signext i32 @setbc13(i8 %a) {
 ; CHECK-LABEL: setbc13:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb r3, r3
@@ -226,7 +222,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc14(i32 %a) {
+define dso_local signext i32 @setbc14(i32 %a) {
 ; CHECK-LABEL: setbc14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -238,7 +234,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc15(i64 %a) {
+define dso_local signext i32 @setbc15(i64 %a) {
 ; CHECK-LABEL: setbc15:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -250,7 +246,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc16(i16 %a) {
+define dso_local signext i32 @setbc16(i16 %a) {
 ; CHECK-LABEL: setbc16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsh r3, r3
@@ -313,7 +309,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setbc21(i8 %a) {
+define dso_local void @setbc21(i8 %a) {
 ; CHECK-LE-LABEL: setbc21:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsb r3, r3
@@ -324,12 +320,11 @@ define void @setbc21(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setbc21:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, 1
@@ -338,7 +333,7 @@ entry:
   ret void
 }
 
-define void @setbc22(i32 %a) {
+define dso_local void @setbc22(i32 %a) {
 ; CHECK-LE-LABEL: setbc22:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -348,11 +343,10 @@ define void @setbc22(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setbc22:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 1
@@ -361,7 +355,7 @@ entry:
   ret void
 }
 
-define void @setbc23(i64 %a) {
+define dso_local void @setbc23(i64 %a) {
 ; CHECK-LE-LABEL: setbc23:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -371,11 +365,10 @@ define void @setbc23(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setbc23:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 1
@@ -384,7 +377,7 @@ entry:
   ret void
 }
 
-define void @setbc24(i16 %a) {
+define dso_local void @setbc24(i16 %a) {
 ; CHECK-LE-LABEL: setbc24:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsh r3, r3
@@ -395,12 +388,11 @@ define void @setbc24(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setbc24:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, 1
@@ -409,7 +401,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbc25(i8 %a) {
+define dso_local signext i32 @setbc25(i8 %a) {
 ; CHECK-LABEL: setbc25:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 24
@@ -422,7 +414,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc26(i32 %a) {
+define dso_local signext i32 @setbc26(i32 %a) {
 ; CHECK-LABEL: setbc26:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -434,7 +426,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc27(i64 %a) {
+define dso_local signext i32 @setbc27(i64 %a) {
 ; CHECK-LABEL: setbc27:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -446,7 +438,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc28(i16 %a) {
+define dso_local signext i32 @setbc28(i16 %a) {
 ; CHECK-LABEL: setbc28:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 16
@@ -509,7 +501,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setbc33(i8 %a) {
+define dso_local void @setbc33(i8 %a) {
 ; CHECK-LE-LABEL: setbc33:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 24
@@ -520,12 +512,11 @@ define void @setbc33(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setbc33:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 24
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 1
@@ -534,7 +525,7 @@ entry:
   ret void
 }
 
-define void @setbc34(i32 %a) {
+define dso_local void @setbc34(i32 %a) {
 ; CHECK-LE-LABEL: setbc34:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -544,11 +535,10 @@ define void @setbc34(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setbc34:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 1
@@ -557,7 +547,7 @@ entry:
   ret void
 }
 
-define void @setbc35(i64 %a) {
+define dso_local void @setbc35(i64 %a) {
 ; CHECK-LE-LABEL: setbc35:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -567,11 +557,10 @@ define void @setbc35(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setbc35:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 1
@@ -580,7 +569,7 @@ entry:
   ret void
 }
 
-define void @setbc36(i16 %a) {
+define dso_local void @setbc36(i16 %a) {
 ; CHECK-LE-LABEL: setbc36:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 16
@@ -591,12 +580,11 @@ define void @setbc36(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setbc36:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 16
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 1
@@ -605,7 +593,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbc37(i64 %a) {
+define dso_local signext i32 @setbc37(i64 %a) {
 ; CHECK-LABEL: setbc37:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpldi r3, 1
@@ -629,7 +617,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setbc39(i64 %a) {
+define dso_local void @setbc39(i64 %a) {
 ; CHECK-LE-LABEL: setbc39:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpldi r3, 1
@@ -639,11 +627,10 @@ define void @setbc39(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setbc39:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpldi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i64 %a, 1

diff --git a/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll
index 8b14553..5ec4012 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setbc1(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbc1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbc1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -29,7 +29,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc2(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbc2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbc2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -41,7 +41,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc3(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbc3(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbc3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -53,7 +53,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbc4(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setbc4(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setbc4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -65,7 +65,7 @@ entry:
   ret i32 %conv2
 }
 
-define void @setbc5(i8 signext %a, i8 signext %b) {
+define dso_local void @setbc5(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbc5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -76,10 +76,9 @@ define void @setbc5(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbc5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -88,7 +87,7 @@ entry:
   ret void
 }
 
-define void @setbc6(i32 signext %a, i32 signext %b) {
+define dso_local void @setbc6(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbc6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -99,10 +98,9 @@ define void @setbc6(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbc6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -111,7 +109,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbc7(i64 %a, i64 %b) {
+define dso_local signext i32 @setbc7(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbc7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -136,7 +134,7 @@ entry:
 }
 
 
-define void @setbc9(i64 %a, i64 %b) {
+define dso_local void @setbc9(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbc9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -147,10 +145,9 @@ define void @setbc9(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbc9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -160,7 +157,7 @@ entry:
 }
 
 
-define signext i32 @setbc10(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setbc10(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setbc10:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -173,7 +170,7 @@ entry:
 }
 
 
-define void @setbc11(i16 signext %a, i16 signext %b) {
+define dso_local void @setbc11(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbc11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -184,10 +181,9 @@ define void @setbc11(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbc11:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -197,7 +193,7 @@ entry:
 }
 
 
-define signext i32 @setbc12(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setbc12(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setbc12:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -210,7 +206,7 @@ entry:
 }
 
 
-define void @setbc13(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setbc13(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setbc13:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -221,10 +217,9 @@ define void @setbc13(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setbc13:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -234,7 +229,7 @@ entry:
 }
 
 
-define signext i32 @setbc14(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setbc14(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setbc14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -247,7 +242,7 @@ entry:
 }
 
 
-define void @setbc15(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setbc15(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setbc15:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -258,10 +253,9 @@ define void @setbc15(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setbc15:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -271,7 +265,7 @@ entry:
 }
 
 
-define signext i32 @setbc16(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setbc16(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setbc16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -284,7 +278,7 @@ entry:
 }
 
 
-define void @setbc17(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setbc17(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setbc17:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -295,10 +289,9 @@ define void @setbc17(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setbc17:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -308,7 +301,7 @@ entry:
 }
 
 
-define signext i32 @setbc18(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setbc18(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setbc18:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -321,7 +314,7 @@ entry:
 }
 
 
-define void @setbc19(i8 signext %a, i8 signext %b) {
+define dso_local void @setbc19(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbc19:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -332,10 +325,9 @@ define void @setbc19(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbc19:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
@@ -345,7 +337,7 @@ entry:
 }
 
 
-define void @setbc20(i32 signext %a, i32 signext %b) {
+define dso_local void @setbc20(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbc20:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -356,10 +348,9 @@ define void @setbc20(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbc20:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
@@ -369,7 +360,7 @@ entry:
 }
 
 
-define signext i32 @setbc21(i64 %a, i64 %b) {
+define dso_local signext i32 @setbc21(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbc21:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -382,7 +373,7 @@ entry:
 }
 
 
-define void @setbc22(i64 %a, i64 %b) {
+define dso_local void @setbc22(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbc22:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -393,10 +384,9 @@ define void @setbc22(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbc22:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -406,7 +396,7 @@ entry:
 }
 
 
-define signext i32 @setbc23(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setbc23(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setbc23:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -419,7 +409,7 @@ entry:
 }
 
 
-define void @setbc24(i16 signext %a, i16 signext %b) {
+define dso_local void @setbc24(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbc24:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -430,10 +420,9 @@ define void @setbc24(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbc24:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
@@ -443,7 +432,7 @@ entry:
 }
 
 
-define signext i32 @setbc25(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setbc25(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setbc25:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -456,7 +445,7 @@ entry:
 }
 
 
-define void @setbc26(i8 signext %a, i8 signext %b) {
+define dso_local void @setbc26(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbc26:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -467,10 +456,9 @@ define void @setbc26(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbc26:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
@@ -480,7 +468,7 @@ entry:
 }
 
 
-define void @setbc27(i32 signext %a, i32 signext %b) {
+define dso_local void @setbc27(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbc27:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -491,10 +479,9 @@ define void @setbc27(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbc27:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
@@ -504,7 +491,7 @@ entry:
 }
 
 
-define signext i32 @setbc28(i64 %a, i64 %b) {
+define dso_local signext i32 @setbc28(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbc28:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -530,7 +517,7 @@ entry:
 }
 
 
-define void @setbc30(i64 %a, i64 %b) {
+define dso_local void @setbc30(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbc30:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -541,10 +528,9 @@ define void @setbc30(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbc30:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -554,7 +540,7 @@ entry:
 }
 
 
-define signext i32 @setbc31(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setbc31(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setbc31:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -567,7 +553,7 @@ entry:
 }
 
 
-define void @setbc32(i16 signext %a, i16 signext %b) {
+define dso_local void @setbc32(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbc32:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -578,10 +564,9 @@ define void @setbc32(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbc32:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
@@ -604,7 +589,7 @@ entry:
 }
 
 
-define void @setbc34(i8 signext %a, i8 signext %b) {
+define dso_local void @setbc34(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbc34:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -615,10 +600,9 @@ define void @setbc34(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbc34:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -641,7 +625,7 @@ entry:
 }
 
 
-define void @setbc36(i32 signext %a, i32 signext %b) {
+define dso_local void @setbc36(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbc36:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -652,10 +636,9 @@ define void @setbc36(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbc36:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -665,7 +648,7 @@ entry:
 }
 
 
-define void @setbc37(i64 %a, i64 %b) {
+define dso_local void @setbc37(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbc37:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -676,10 +659,9 @@ define void @setbc37(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbc37:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -702,7 +684,7 @@ entry:
 }
 
 
-define void @setbc39(i16 signext %a, i16 signext %b) {
+define dso_local void @setbc39(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbc39:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -713,10 +695,9 @@ define void @setbc39(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbc39:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -739,7 +720,7 @@ entry:
 }
 
 
-define void @setbc41(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setbc41(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setbc41:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -750,10 +731,9 @@ define void @setbc41(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setbc41:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -776,7 +756,7 @@ entry:
 }
 
 
-define void @setbc43(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setbc43(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setbc43:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -787,10 +767,9 @@ define void @setbc43(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setbc43:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -813,7 +792,7 @@ entry:
 }
 
 
-define void @setbc45(i64 %a, i64 %b) {
+define dso_local void @setbc45(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbc45:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -824,10 +803,9 @@ define void @setbc45(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbc45:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -850,7 +828,7 @@ entry:
 }
 
 
-define void @setbc47(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setbc47(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setbc47:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -861,10 +839,9 @@ define void @setbc47(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setbc47:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -887,7 +864,7 @@ entry:
 }
 
 
-define void @setbc49(i64 %a, i64 %b) {
+define dso_local void @setbc49(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbc49:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -898,10 +875,9 @@ define void @setbc49(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbc49:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -924,7 +900,7 @@ entry:
 }
 
 
-define void @setnbc51(i64 %a, i64 %b) {
+define dso_local void @setnbc51(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc51:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -935,10 +911,9 @@ define void @setnbc51(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc51:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbc r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b

diff --git a/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll
index 9287e8e..17ac933 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setbcr1(i8 %a) {
+define dso_local signext i32 @setbcr1(i8 %a) {
 ; CHECK-LABEL: setbcr1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 24
@@ -30,7 +30,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbcr2(i32 %a) {
+define dso_local signext i32 @setbcr2(i32 %a) {
 ; CHECK-LABEL: setbcr2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -42,7 +42,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbcr3(i64 %a) {
+define dso_local signext i32 @setbcr3(i64 %a) {
 ; CHECK-LABEL: setbcr3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -54,7 +54,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setbcr4(i16 %a) {
+define dso_local signext i32 @setbcr4(i16 %a) {
 ; CHECK-LABEL: setbcr4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 16
@@ -117,7 +117,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setbcr9(i8 %a) {
+define dso_local void @setbcr9(i8 %a) {
 ; CHECK-LE-LABEL: setbcr9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 24
@@ -128,12 +128,11 @@ define void @setbcr9(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setbcr9:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 24
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 1
@@ -142,7 +141,7 @@ entry:
   ret void
 }
 
-define void @setbcr10(i32 %a) {
+define dso_local void @setbcr10(i32 %a) {
 ; CHECK-LE-LABEL: setbcr10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -152,11 +151,10 @@ define void @setbcr10(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setbcr10:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, 1
@@ -165,7 +163,7 @@ entry:
   ret void
 }
 
-define void @setbcr11(i64 %a) {
+define dso_local void @setbcr11(i64 %a) {
 ; CHECK-LE-LABEL: setbcr11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -175,11 +173,10 @@ define void @setbcr11(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setbcr11:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, 1
@@ -188,7 +185,7 @@ entry:
   ret void
 }
 
-define void @setbcr12(i16 %a) {
+define dso_local void @setbcr12(i16 %a) {
 ; CHECK-LE-LABEL: setbcr12:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 16
@@ -199,12 +196,11 @@ define void @setbcr12(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setbcr12:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 16
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, 1

diff --git a/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll
index 06d8831..2cc7091 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll
@@ -12,13 +12,13 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
 
-define signext i32 @setbcr1(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbcr1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbcr1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -31,7 +31,7 @@ entry:
 }
 
 
-define signext i32 @setbcr2(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbcr2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbcr2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -44,7 +44,7 @@ entry:
 }
 
 
-define signext i32 @setbcr3(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbcr3(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbcr3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -57,7 +57,7 @@ entry:
 }
 
 
-define signext i32 @setbcr4(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setbcr4(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setbcr4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -70,7 +70,7 @@ entry:
 }
 
 
-define void @setbcr5(i8 signext %a, i8 signext %b) {
+define dso_local void @setbcr5(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbcr5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -81,10 +81,9 @@ define void @setbcr5(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbcr5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
@@ -94,7 +93,7 @@ entry:
 }
 
 
-define void @setbcr6(i32 signext %a, i32 signext %b) {
+define dso_local void @setbcr6(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbcr6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -105,10 +104,9 @@ define void @setbcr6(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbcr6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
@@ -118,7 +116,7 @@ entry:
 }
 
 
-define signext i32 @setbcr7(i64 %a, i64 %b) {
+define dso_local signext i32 @setbcr7(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbcr7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -144,7 +142,7 @@ entry:
 }
 
 
-define void @setbcr9(i64 %a, i64 %b) {
+define dso_local void @setbcr9(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -155,10 +153,9 @@ define void @setbcr9(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i64 %a, %b
@@ -168,7 +165,7 @@ entry:
 }
 
 
-define signext i32 @setbcr10(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setbcr10(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setbcr10:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -181,7 +178,7 @@ entry:
 }
 
 
-define void @setbcr11(i16 signext %a, i16 signext %b) {
+define dso_local void @setbcr11(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbcr11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -192,10 +189,9 @@ define void @setbcr11(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbcr11:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
@@ -205,7 +201,7 @@ entry:
 }
 
 
-define signext i32 @setbcr12(i64 %a, i64 %b) {
+define dso_local signext i32 @setbcr12(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbcr12:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpld r3, r4
@@ -218,7 +214,7 @@ entry:
 }
 
 
-define void @setbcr13(i64 %a, i64 %b) {
+define dso_local void @setbcr13(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr13:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -229,10 +225,9 @@ define void @setbcr13(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr13:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
@@ -242,7 +237,7 @@ entry:
 }
 
 
-define signext i32 @setbcr14(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setbcr14(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setbcr14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -255,7 +250,7 @@ entry:
 }
 
 
-define void @setbcr15(i8 signext %a, i8 signext %b) {
+define dso_local void @setbcr15(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbcr15:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -266,10 +261,9 @@ define void @setbcr15(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbcr15:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
@@ -279,7 +273,7 @@ entry:
 }
 
 
-define signext i32 @setbcr16(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setbcr16(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setbcr16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -292,7 +286,7 @@ entry:
 }
 
 
-define void @setbcr17(i32 signext %a, i32 signext %b) {
+define dso_local void @setbcr17(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbcr17:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -303,10 +297,9 @@ define void @setbcr17(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbcr17:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
@@ -316,7 +309,7 @@ entry:
 }
 
 
-define signext i32 @setbcr18(i64 %a, i64 %b) {
+define dso_local signext i32 @setbcr18(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbcr18:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -329,7 +322,7 @@ entry:
 }
 
 
-define void @setbcr19(i64 %a, i64 %b) {
+define dso_local void @setbcr19(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr19:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -340,10 +333,9 @@ define void @setbcr19(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr19:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i64 %a, %b
@@ -353,7 +345,7 @@ entry:
 }
 
 
-define signext i32 @setbcr20(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setbcr20(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setbcr20:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -366,7 +358,7 @@ entry:
 }
 
 
-define void @setbcr21(i16 signext %a, i16 signext %b) {
+define dso_local void @setbcr21(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbcr21:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -377,10 +369,9 @@ define void @setbcr21(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbcr21:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
@@ -390,7 +381,7 @@ entry:
 }
 
 
-define signext i32 @setbcr22(i64 %a, i64 %b) {
+define dso_local signext i32 @setbcr22(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbcr22:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpld r3, r4
@@ -403,7 +394,7 @@ entry:
 }
 
 
-define void @setbcr23(i64 %a, i64 %b) {
+define dso_local void @setbcr23(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr23:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -414,10 +405,9 @@ define void @setbcr23(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr23:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
@@ -426,7 +416,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbcr24(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setbcr24(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setbcr24:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -438,7 +428,7 @@ entry:
   ret i32 %conv2
 }
 
-define void @setbcr25(i8 signext %a, i8 signext %b) {
+define dso_local void @setbcr25(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbcr25:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -449,10 +439,9 @@ define void @setbcr25(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbcr25:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, %b
@@ -461,7 +450,7 @@ entry:
   ret void
 }
 
-define void @setbcr26(i32 signext %a, i32 signext %b) {
+define dso_local void @setbcr26(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbcr26:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -472,10 +461,9 @@ define void @setbcr26(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbcr26:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, %b
@@ -484,7 +472,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbcr27(i64 %a, i64 %b) {
+define dso_local signext i32 @setbcr27(i64 %a, i64 %b) {
 ; CHECK-LABEL: setbcr27:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -496,7 +484,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setbcr28(i64 %a, i64 %b) {
+define dso_local void @setbcr28(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr28:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -507,10 +495,9 @@ define void @setbcr28(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr28:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, %b
@@ -519,7 +506,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbcr29(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setbcr29(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setbcr29:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -531,7 +518,7 @@ entry:
   ret i32 %conv2
 }
 
-define void @setbcr30(i16 signext %a, i16 signext %b) {
+define dso_local void @setbcr30(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbcr30:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -542,10 +529,9 @@ define void @setbcr30(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbcr30:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, %b
@@ -554,7 +540,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbcr31(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setbcr31(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setbcr31:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -566,7 +552,7 @@ entry:
   ret i32 %conv2
 }
 
-define void @setbcr32(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setbcr32(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setbcr32:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -577,10 +563,9 @@ define void @setbcr32(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setbcr32:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, %b
@@ -589,7 +574,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbcr33(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setbcr33(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setbcr33:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -601,7 +586,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setbcr34(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setbcr34(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setbcr34:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -612,10 +597,9 @@ define void @setbcr34(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setbcr34:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, %b
@@ -624,7 +608,7 @@ entry:
   ret void
 }
 
-define signext i32 @setbcr35(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setbcr35(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setbcr35:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -636,7 +620,7 @@ entry:
   ret i32 %conv2
 }
 
-define void @setbcr36(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setbcr36(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setbcr36:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -647,10 +631,9 @@ define void @setbcr36(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setbcr36:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, %b
@@ -671,7 +654,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setbcr38(i8 signext %a, i8 signext %b) {
+define dso_local void @setbcr38(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbcr38:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -682,10 +665,9 @@ define void @setbcr38(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbcr38:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
@@ -706,7 +688,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setbcr40(i32 signext %a, i32 signext %b) {
+define dso_local void @setbcr40(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbcr40:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -717,10 +699,9 @@ define void @setbcr40(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbcr40:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
@@ -741,7 +722,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setbcr42(i64 %a, i64 %b) {
+define dso_local void @setbcr42(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr42:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -752,10 +733,9 @@ define void @setbcr42(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr42:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i64 %a, %b
@@ -776,7 +756,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setbcr44(i16 signext %a, i16 signext %b) {
+define dso_local void @setbcr44(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbcr44:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -787,10 +767,9 @@ define void @setbcr44(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbcr44:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
@@ -813,7 +792,7 @@ entry:
 }
 
 
-define void @setbcr46(i64 %a, i64 %b) {
+define dso_local void @setbcr46(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr46:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -824,10 +803,9 @@ define void @setbcr46(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr46:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
@@ -848,7 +826,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setbcr48(i8 signext %a, i8 signext %b) {
+define dso_local void @setbcr48(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setbcr48:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -859,10 +837,9 @@ define void @setbcr48(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setbcr48:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
@@ -883,7 +860,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setbcr50(i32 signext %a, i32 signext %b) {
+define dso_local void @setbcr50(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setbcr50:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -894,10 +871,9 @@ define void @setbcr50(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setbcr50:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
@@ -920,7 +896,7 @@ entry:
 }
 
 
-define void @setbcr52(i64 %a, i64 %b) {
+define dso_local void @setbcr52(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr52:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -931,10 +907,9 @@ define void @setbcr52(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr52:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i64 %a, %b
@@ -955,7 +930,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setbcr54(i16 signext %a, i16 signext %b) {
+define dso_local void @setbcr54(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setbcr54:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -966,10 +941,9 @@ define void @setbcr54(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setbcr54:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
@@ -992,7 +966,7 @@ entry:
 }
 
 
-define void @setbcr56(i64 %a, i64 %b) {
+define dso_local void @setbcr56(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr56:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -1003,10 +977,9 @@ define void @setbcr56(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr56:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
@@ -1027,7 +1000,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setbcr58(i64 %a, i64 %b) {
+define dso_local void @setbcr58(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr58:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -1038,10 +1011,9 @@ define void @setbcr58(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr58:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, %b
@@ -1062,7 +1034,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setbcr60(i64 %a, i64 %b) {
+define dso_local void @setbcr60(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setbcr60:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -1073,10 +1045,9 @@ define void @setbcr60(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setbcr60:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, %b

diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll
index 67093bc..c6b5fc3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setnbc1(i8 %a) {
+define dso_local signext i32 @setnbc1(i8 %a) {
 ; CHECK-LABEL: setnbc1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb r3, r3
@@ -30,7 +30,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc2(i32 %a) {
+define dso_local signext i32 @setnbc2(i32 %a) {
 ; CHECK-LABEL: setnbc2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -42,7 +42,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc3(i64 %a) {
+define dso_local signext i32 @setnbc3(i64 %a) {
 ; CHECK-LABEL: setnbc3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -54,7 +54,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc4(i16 %a) {
+define dso_local signext i32 @setnbc4(i16 %a) {
 ; CHECK-LABEL: setnbc4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsh r3, r3
@@ -117,7 +117,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc9(i8 %a) {
+define dso_local void @setnbc9(i8 %a) {
 ; CHECK-LE-LABEL: setnbc9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsb r3, r3
@@ -128,12 +128,11 @@ define void @setnbc9(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc9:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, 1
@@ -142,7 +141,7 @@ entry:
   ret void
 }
 
-define void @setnbc10(i32 %a) {
+define dso_local void @setnbc10(i32 %a) {
 ; CHECK-LE-LABEL: setnbc10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -152,11 +151,10 @@ define void @setnbc10(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc10:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, 1
@@ -165,7 +163,7 @@ entry:
   ret void
 }
 
-define void @setnbc11(i64 %a) {
+define dso_local void @setnbc11(i64 %a) {
 ; CHECK-LE-LABEL: setnbc11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -175,11 +173,10 @@ define void @setnbc11(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc11:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 1
@@ -188,7 +185,7 @@ entry:
   ret void
 }
 
-define void @setnbc12(i16 %a) {
+define dso_local void @setnbc12(i16 %a) {
 ; CHECK-LE-LABEL: setnbc12:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsh r3, r3
@@ -199,12 +196,11 @@ define void @setnbc12(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc12:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, 1
@@ -213,7 +209,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc13(i8 %a) {
+define dso_local signext i32 @setnbc13(i8 %a) {
 ; CHECK-LABEL: setnbc13:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb r3, r3
@@ -226,7 +222,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc14(i32 %a) {
+define dso_local signext i32 @setnbc14(i32 %a) {
 ; CHECK-LABEL: setnbc14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -238,7 +234,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc15(i64 %a) {
+define dso_local signext i32 @setnbc15(i64 %a) {
 ; CHECK-LABEL: setnbc15:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -250,7 +246,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc16(i16 %a) {
+define dso_local signext i32 @setnbc16(i16 %a) {
 ; CHECK-LABEL: setnbc16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsh r3, r3
@@ -313,7 +309,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc21(i8 %a) {
+define dso_local void @setnbc21(i8 %a) {
 ; CHECK-LE-LABEL: setnbc21:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsb r3, r3
@@ -324,12 +320,11 @@ define void @setnbc21(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc21:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, 1
@@ -338,7 +333,7 @@ entry:
   ret void
 }
 
-define void @setnbc22(i32 %a) {
+define dso_local void @setnbc22(i32 %a) {
 ; CHECK-LE-LABEL: setnbc22:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -348,11 +343,10 @@ define void @setnbc22(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc22:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 1
@@ -361,7 +355,7 @@ entry:
   ret void
 }
 
-define void @setnbc23(i64 %a) {
+define dso_local void @setnbc23(i64 %a) {
 ; CHECK-LE-LABEL: setnbc23:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -371,11 +365,10 @@ define void @setnbc23(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc23:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 1
@@ -384,7 +377,7 @@ entry:
   ret void
 }
 
-define void @setnbc24(i16 %a) {
+define dso_local void @setnbc24(i16 %a) {
 ; CHECK-LE-LABEL: setnbc24:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsh r3, r3
@@ -395,12 +388,11 @@ define void @setnbc24(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc24:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, 1
@@ -409,7 +401,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc25(i8 %a) {
+define dso_local signext i32 @setnbc25(i8 %a) {
 ; CHECK-LABEL: setnbc25:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 24
@@ -422,7 +414,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc26(i32 %a) {
+define dso_local signext i32 @setnbc26(i32 %a) {
 ; CHECK-LABEL: setnbc26:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -434,7 +426,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc27(i64 %a) {
+define dso_local signext i32 @setnbc27(i64 %a) {
 ; CHECK-LABEL: setnbc27:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -446,7 +438,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc28(i16 %a) {
+define dso_local signext i32 @setnbc28(i16 %a) {
 ; CHECK-LABEL: setnbc28:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 16
@@ -509,7 +501,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc33(i8 %a) {
+define dso_local void @setnbc33(i8 %a) {
 ; CHECK-LE-LABEL: setnbc33:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 24
@@ -520,12 +512,11 @@ define void @setnbc33(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc33:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 24
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 1
@@ -534,7 +525,7 @@ entry:
   ret void
 }
 
-define void @setnbc34(i32 %a) {
+define dso_local void @setnbc34(i32 %a) {
 ; CHECK-LE-LABEL: setnbc34:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -544,11 +535,10 @@ define void @setnbc34(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc34:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 1
@@ -557,7 +547,7 @@ entry:
   ret void
 }
 
-define void @setnbc35(i64 %a) {
+define dso_local void @setnbc35(i64 %a) {
 ; CHECK-LE-LABEL: setnbc35:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -567,11 +557,10 @@ define void @setnbc35(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc35:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 1
@@ -580,7 +569,7 @@ entry:
   ret void
 }
 
-define void @setnbc36(i16 %a) {
+define dso_local void @setnbc36(i16 %a) {
 ; CHECK-LE-LABEL: setnbc36:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 16
@@ -591,12 +580,11 @@ define void @setnbc36(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc36:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 16
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 1
@@ -605,7 +593,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc37(i64 %a) {
+define dso_local signext i32 @setnbc37(i64 %a) {
 ; CHECK-LABEL: setnbc37:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpldi r3, 1
@@ -629,7 +617,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc39(i64 %a) {
+define dso_local void @setnbc39(i64 %a) {
 ; CHECK-LE-LABEL: setnbc39:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpldi r3, 1
@@ -639,11 +627,10 @@ define void @setnbc39(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc39:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpldi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i64 %a, 1
@@ -652,7 +639,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc40(i8 %a) {
+define dso_local signext i32 @setnbc40(i8 %a) {
 ; CHECK-LABEL: setnbc40:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb. r3, r3
@@ -664,7 +651,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc41(i32 %a) {
+define dso_local signext i32 @setnbc41(i32 %a) {
 ; CHECK-LABEL: setnbc41:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 0
@@ -676,7 +663,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc42(i16 %a) {
+define dso_local signext i32 @setnbc42(i16 %a) {
 ; CHECK-LABEL: setnbc42:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsh. r3, r3
@@ -724,7 +711,7 @@ entry:
   ret i64 %conv
 }
 
-define signext i32 @setnbc46(i8 %a) {
+define dso_local signext i32 @setnbc46(i8 %a) {
 ; CHECK-LABEL: setnbc46:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb. r3, r3
@@ -736,7 +723,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc47(i32 %a) {
+define dso_local signext i32 @setnbc47(i32 %a) {
 ; CHECK-LABEL: setnbc47:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 0
@@ -748,7 +735,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc48(i64 %a) {
+define dso_local signext i32 @setnbc48(i64 %a) {
 ; CHECK-LABEL: setnbc48:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 0
@@ -760,7 +747,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc49(i16 %a) {
+define dso_local signext i32 @setnbc49(i16 %a) {
 ; CHECK-LABEL: setnbc49:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsh. r3, r3
@@ -820,7 +807,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc54(i8 %a) {
+define dso_local void @setnbc54(i8 %a) {
 ; CHECK-LE-LABEL: setnbc54:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsb. r3, r3
@@ -830,11 +817,10 @@ define void @setnbc54(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc54:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    extsb. r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, 0
@@ -843,7 +829,7 @@ entry:
   ret void
 }
 
-define void @setnbc55(i32 %a) {
+define dso_local void @setnbc55(i32 %a) {
 ; CHECK-LE-LABEL: setnbc55:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 0
@@ -853,11 +839,10 @@ define void @setnbc55(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc55:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
@@ -866,7 +851,7 @@ entry:
   ret void
 }
 
-define void @setnbc56(i64 %a) {
+define dso_local void @setnbc56(i64 %a) {
 ; CHECK-LE-LABEL: setnbc56:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 0
@@ -876,11 +861,10 @@ define void @setnbc56(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc56:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
@@ -889,7 +873,7 @@ entry:
   ret void
 }
 
-define void @setnbc57(i16 %a) {
+define dso_local void @setnbc57(i16 %a) {
 ; CHECK-LE-LABEL: setnbc57:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    extsh. r3, r3
@@ -899,11 +883,10 @@ define void @setnbc57(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc57:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    extsh. r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, 0
@@ -912,7 +895,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc58(i8 %a) {
+define dso_local signext i32 @setnbc58(i8 %a) {
 ; CHECK-LABEL: setnbc58:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andi. r3, r3, 255
@@ -924,7 +907,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc59(i32 %a) {
+define dso_local signext i32 @setnbc59(i32 %a) {
 ; CHECK-LABEL: setnbc59:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 0
@@ -936,7 +919,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc60(i64 %a) {
+define dso_local signext i32 @setnbc60(i64 %a) {
 ; CHECK-LABEL: setnbc60:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 0
@@ -948,7 +931,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc61(i16 %a) {
+define dso_local signext i32 @setnbc61(i16 %a) {
 ; CHECK-LABEL: setnbc61:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andi. r3, r3, 65535
@@ -1008,7 +991,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc66(i8 %a) {
+define dso_local void @setnbc66(i8 %a) {
 ; CHECK-LE-LABEL: setnbc66:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    andi. r3, r3, 255
@@ -1018,11 +1001,10 @@ define void @setnbc66(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc66:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    andi. r3, r3, 255
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
@@ -1031,7 +1013,7 @@ entry:
   ret void
 }
 
-define void @setnbc67(i32 %a) {
+define dso_local void @setnbc67(i32 %a) {
 ; CHECK-LE-LABEL: setnbc67:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 0
@@ -1041,11 +1023,10 @@ define void @setnbc67(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc67:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
@@ -1054,7 +1035,7 @@ entry:
   ret void
 }
 
-define void @setnbc68(i64 %a) {
+define dso_local void @setnbc68(i64 %a) {
 ; CHECK-LE-LABEL: setnbc68:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 0
@@ -1064,11 +1045,10 @@ define void @setnbc68(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc68:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 0
@@ -1077,7 +1057,7 @@ entry:
   ret void
 }
 
-define void @setnbc69(i16 %a) {
+define dso_local void @setnbc69(i16 %a) {
 ; CHECK-LE-LABEL: setnbc69:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    andi. r3, r3, 65535
@@ -1087,11 +1067,10 @@ define void @setnbc69(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbc69:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    andi. r3, r3, 65535
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0

diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll
index 596b320..5fd286e 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setnbc1(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbc1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbc1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -29,7 +29,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc2(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbc2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbc2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -41,7 +41,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc3(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbc3(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbc3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -53,7 +53,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbc4(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setnbc4(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setnbc4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -66,7 +66,7 @@ entry:
 }
 
 ; function attrs: norecurse nounwind
-define void @setnbc5(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbc5(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbc5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -77,10 +77,9 @@ define void @setnbc5(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbc5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -89,7 +88,7 @@ entry:
   ret void
 }
 
-define void @setnbc6(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbc6(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbc6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -100,10 +99,9 @@ define void @setnbc6(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbc6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -112,7 +110,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc7(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbc7(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbc7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -136,7 +134,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbc9(i64 %a, i64 %b) {
+define dso_local void @setnbc9(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -147,10 +145,9 @@ define void @setnbc9(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -159,7 +156,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc10(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setnbc10(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setnbc10:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -171,7 +168,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setnbc11(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbc11(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbc11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -182,10 +179,9 @@ define void @setnbc11(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbc11:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -194,7 +190,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc12(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setnbc12(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setnbc12:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -206,7 +202,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setnbc13(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbc13(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc13:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -217,10 +213,9 @@ define void @setnbc13(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc13:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -229,7 +224,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc14(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setnbc14(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setnbc14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -241,7 +236,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setnbc15(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbc15(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc15:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -252,10 +247,9 @@ define void @setnbc15(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc15:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -264,7 +258,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc16(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setnbc16(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setnbc16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -276,7 +270,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setnbc17(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbc17(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc17:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -287,10 +281,9 @@ define void @setnbc17(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc17:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -299,7 +292,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc18(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setnbc18(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setnbc18:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -311,7 +304,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc19(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbc19(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbc19:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -322,10 +315,9 @@ define void @setnbc19(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbc19:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
@@ -334,7 +326,7 @@ entry:
   ret void
 }
 
-define void @setnbc20(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbc20(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbc20:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -345,10 +337,9 @@ define void @setnbc20(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbc20:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
@@ -357,7 +348,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc21(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbc21(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbc21:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -369,7 +360,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc22(i64 %a, i64 %b) {
+define dso_local void @setnbc22(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc22:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -380,10 +371,9 @@ define void @setnbc22(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc22:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -392,7 +382,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc23(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setnbc23(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setnbc23:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -404,7 +394,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc24(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbc24(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbc24:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -415,10 +405,9 @@ define void @setnbc24(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbc24:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
@@ -427,7 +416,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc25(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setnbc25(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setnbc25:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -439,7 +428,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc26(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbc26(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc26:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -450,10 +439,9 @@ define void @setnbc26(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc26:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -462,7 +450,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc27(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setnbc27(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setnbc27:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -474,7 +462,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc28(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbc28(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc28:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -485,10 +473,9 @@ define void @setnbc28(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc28:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -497,7 +484,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc29(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setnbc29(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setnbc29:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -509,7 +496,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc30(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbc30(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc30:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -520,10 +507,9 @@ define void @setnbc30(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc30:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -532,7 +518,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc31(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setnbc31(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setnbc31:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -544,7 +530,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc32(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbc32(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbc32:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -555,10 +541,9 @@ define void @setnbc32(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbc32:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
@@ -567,7 +552,7 @@ entry:
   ret void
 }
 
-define void @setnbc33(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbc33(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbc33:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -578,10 +563,9 @@ define void @setnbc33(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbc33:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
@@ -590,7 +574,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc34(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbc34(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbc34:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -614,7 +598,7 @@ entry:
   ret i64 %sub
 }
 
-define void @setnbc36(i64 %a, i64 %b) {
+define dso_local void @setnbc36(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc36:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -625,10 +609,9 @@ define void @setnbc36(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc36:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -637,7 +620,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc37(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setnbc37(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setnbc37:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -649,7 +632,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc38(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbc38(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbc38:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -660,10 +643,9 @@ define void @setnbc38(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbc38:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
@@ -672,7 +654,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc39(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setnbc39(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setnbc39:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -684,7 +666,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc40(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbc40(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc40:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -695,10 +677,9 @@ define void @setnbc40(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc40:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -707,7 +688,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc41(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setnbc41(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setnbc41:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -719,7 +700,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc42(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbc42(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc42:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -730,10 +711,9 @@ define void @setnbc42(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc42:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -742,7 +722,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbc43(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setnbc43(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setnbc43:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -754,7 +734,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbc44(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbc44(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc44:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -765,10 +745,9 @@ define void @setnbc44(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc44:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -789,7 +768,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc46(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbc46(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbc46:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -800,10 +779,9 @@ define void @setnbc46(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbc46:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -824,7 +802,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc48(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbc48(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbc48:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -835,10 +813,9 @@ define void @setnbc48(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbc48:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -847,7 +824,7 @@ entry:
   ret void
 }
 
-define void @setnbc49(i64 %a, i64 %b) {
+define dso_local void @setnbc49(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc49:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -858,10 +835,9 @@ define void @setnbc49(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc49:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -882,7 +858,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc51(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbc51(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbc51:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -893,10 +869,9 @@ define void @setnbc51(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbc51:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -917,7 +892,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc53(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbc53(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc53:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -928,10 +903,9 @@ define void @setnbc53(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc53:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
@@ -952,7 +926,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc55(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbc55(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc55:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -963,10 +937,9 @@ define void @setnbc55(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc55:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
@@ -987,7 +960,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc57(i64 %a, i64 %b) {
+define dso_local void @setnbc57(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc57:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -998,10 +971,9 @@ define void @setnbc57(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc57:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -1022,7 +994,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc59(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbc59(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc59:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -1033,10 +1005,9 @@ define void @setnbc59(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc59:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
@@ -1057,7 +1028,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc61(i64 %a, i64 %b) {
+define dso_local void @setnbc61(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc61:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -1068,10 +1039,9 @@ define void @setnbc61(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc61:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -1092,7 +1062,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc63(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbc63(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc63:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1103,10 +1073,9 @@ define void @setnbc63(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc63:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -1127,7 +1096,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc65(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbc65(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc65:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1138,10 +1107,9 @@ define void @setnbc65(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc65:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -1162,7 +1130,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc67(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbc67(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc67:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1173,10 +1141,9 @@ define void @setnbc67(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc67:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -1197,7 +1164,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc69(i64 %a, i64 %b) {
+define dso_local void @setnbc69(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbc69:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -1208,10 +1175,9 @@ define void @setnbc69(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbc69:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -1232,7 +1198,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc71(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbc71(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc71:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1243,10 +1209,9 @@ define void @setnbc71(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc71:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -1267,7 +1232,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbc73(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbc73(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc73:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1278,10 +1243,9 @@ define void @setnbc73(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc73:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -1302,7 +1266,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbc75(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbc75(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbc75:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1313,10 +1277,9 @@ define void @setnbc75(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbc75:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbc r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b

diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll
index c912536..68525ca 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setnbcr1(i8 %a) {
+define dso_local signext i32 @setnbcr1(i8 %a) {
 ; CHECK-LABEL: setnbcr1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andi. r3, r3, 255
@@ -29,7 +29,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbcr2(i32 %a) {
+define dso_local signext i32 @setnbcr2(i32 %a) {
 ; CHECK-LABEL: setnbcr2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 0
@@ -41,7 +41,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbcr3(i64 %a) {
+define dso_local signext i32 @setnbcr3(i64 %a) {
 ; CHECK-LABEL: setnbcr3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 0
@@ -53,7 +53,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbcr4(i16 %a) {
+define dso_local signext i32 @setnbcr4(i16 %a) {
 ; CHECK-LABEL: setnbcr4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andi. r3, r3, 65535
@@ -113,7 +113,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbcr9(i8 %a) {
+define dso_local void @setnbcr9(i8 %a) {
 ; CHECK-LE-LABEL: setnbcr9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    andi. r3, r3, 255
@@ -123,11 +123,10 @@ define void @setnbcr9(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr9:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    andi. r3, r3, 255
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 1
@@ -136,7 +135,7 @@ entry:
   ret void
 }
 
-define void @setnbcr10(i32 %a) {
+define dso_local void @setnbcr10(i32 %a) {
 ; CHECK-LE-LABEL: setnbcr10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 0
@@ -146,11 +145,10 @@ define void @setnbcr10(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr10:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 1
@@ -159,7 +157,7 @@ entry:
   ret void
 }
 
-define void @setnbcr11(i64 %a) {
+define dso_local void @setnbcr11(i64 %a) {
 ; CHECK-LE-LABEL: setnbcr11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 0
@@ -169,11 +167,10 @@ define void @setnbcr11(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr11:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 1
@@ -182,7 +179,7 @@ entry:
   ret void
 }
 
-define void @setnbcr12(i16 %a) {
+define dso_local void @setnbcr12(i16 %a) {
 ; CHECK-LE-LABEL: setnbcr12:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    andi. r3, r3, 65535
@@ -192,11 +189,10 @@ define void @setnbcr12(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr12:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    andi. r3, r3, 65535
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 1
@@ -205,7 +201,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr13(i8 %a) {
+define dso_local signext i32 @setnbcr13(i8 %a) {
 ; CHECK-LABEL: setnbcr13:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 24
@@ -218,7 +214,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbcr14(i32 %a) {
+define dso_local signext i32 @setnbcr14(i32 %a) {
 ; CHECK-LABEL: setnbcr14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
@@ -230,7 +226,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbcr15(i64 %a) {
+define dso_local signext i32 @setnbcr15(i64 %a) {
 ; CHECK-LABEL: setnbcr15:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
@@ -242,7 +238,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @setnbcr16(i16 %a) {
+define dso_local signext i32 @setnbcr16(i16 %a) {
 ; CHECK-LABEL: setnbcr16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 16
@@ -305,7 +301,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbcr21(i8 %a) {
+define dso_local void @setnbcr21(i8 %a) {
 ; CHECK-LE-LABEL: setnbcr21:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 24
@@ -316,12 +312,11 @@ define void @setnbcr21(i8 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr21:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 24
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 1
@@ -330,7 +325,7 @@ entry:
   ret void
 }
 
-define void @setnbcr22(i32 %a) {
+define dso_local void @setnbcr22(i32 %a) {
 ; CHECK-LE-LABEL: setnbcr22:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpwi r3, 1
@@ -340,11 +335,10 @@ define void @setnbcr22(i32 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr22:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, 1
@@ -353,7 +347,7 @@ entry:
   ret void
 }
 
-define void @setnbcr23(i64 %a) {
+define dso_local void @setnbcr23(i64 %a) {
 ; CHECK-LE-LABEL: setnbcr23:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpdi r3, 1
@@ -363,11 +357,10 @@ define void @setnbcr23(i64 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr23:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    cmpdi r3, 1
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, 1
@@ -376,7 +369,7 @@ entry:
   ret void
 }
 
-define void @setnbcr24(i16 %a) {
+define dso_local void @setnbcr24(i16 %a) {
 ; CHECK-LE-LABEL: setnbcr24:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 16
@@ -387,12 +380,11 @@ define void @setnbcr24(i16 %a) {
 ;
 ; CHECK-BE-LABEL: setnbcr24:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 16
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, 1

diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll
index 5e85dcc..d648f52 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll
@@ -12,12 +12,12 @@
 ; This codegen will be re-evaluated at a later time on whether or not it should
 ; be emitted on P10.
 
-@globalVal = common local_unnamed_addr global i8 0, align 1
-@globalVal2 = common local_unnamed_addr global i32 0, align 4
-@globalVal3 = common local_unnamed_addr global i64 0, align 8
-@globalVal4 = common local_unnamed_addr global i16 0, align 2
+@globalVal = common dso_local local_unnamed_addr global i8 0, align 1
+@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 4
+@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 8
+@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @setnbcr1(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbcr1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbcr1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -29,7 +29,7 @@ entry:
   ret i32 %lnot.ext
 }
 
-define signext i32 @setnbcr2(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbcr2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbcr2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -41,7 +41,7 @@ entry:
   ret i32 %lnot.ext
 }
 
-define signext i32 @setnbcr3(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbcr3(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbcr3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -53,7 +53,7 @@ entry:
   ret i32 %lnot.ext
 }
 
-define signext i32 @setnbcr4(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setnbcr4(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setnbcr4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -65,7 +65,7 @@ entry:
   ret i32 %conv
 }
 
-define void @setnbcr5(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbcr5(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbcr5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -76,10 +76,9 @@ define void @setnbcr5(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbcr5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
@@ -88,7 +87,7 @@ entry:
   ret void
 }
 
-define void @setnbcr6(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbcr6(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbcr6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -99,10 +98,9 @@ define void @setnbcr6(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbcr6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
@@ -111,7 +109,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr7(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbcr7(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbcr7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -135,7 +133,7 @@ entry:
   ret i64 %conv
 }
 
-define void @setnbcr9(i64 %a, i64 %b) {
+define dso_local void @setnbcr9(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -146,10 +144,9 @@ define void @setnbcr9(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i64 %a, %b
@@ -158,7 +155,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr10(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setnbcr10(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setnbcr10:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -170,7 +167,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr11(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbcr11(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbcr11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -181,10 +178,9 @@ define void @setnbcr11(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbcr11:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
@@ -193,7 +189,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr12(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setnbcr12(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setnbcr12:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -205,7 +201,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr13(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbcr13(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr13:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -216,10 +212,9 @@ define void @setnbcr13(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr13:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
@@ -228,7 +223,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr14(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setnbcr14(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setnbcr14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -240,7 +235,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr15(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbcr15(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr15:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -251,10 +246,9 @@ define void @setnbcr15(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr15:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
@@ -263,7 +257,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr16(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbcr16(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbcr16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpld r3, r4
@@ -275,7 +269,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr17(i64 %a, i64 %b) {
+define dso_local void @setnbcr17(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr17:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -286,10 +280,9 @@ define void @setnbcr17(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr17:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
@@ -298,7 +291,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr18(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setnbcr18(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setnbcr18:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -310,7 +303,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr19(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbcr19(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr19:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -321,10 +314,9 @@ define void @setnbcr19(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr19:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
@@ -333,7 +325,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr20(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setnbcr20(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setnbcr20:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -345,7 +337,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr21(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbcr21(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbcr21:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -356,10 +348,9 @@ define void @setnbcr21(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbcr21:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
@@ -368,7 +359,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr22(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @setnbcr22(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: setnbcr22:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -380,7 +371,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr23(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbcr23(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbcr23:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -391,10 +382,9 @@ define void @setnbcr23(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbcr23:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
@@ -403,7 +393,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr24(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbcr24(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbcr24:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -415,7 +405,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr25(i64 %a, i64 %b) {
+define dso_local void @setnbcr25(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr25:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -426,10 +416,9 @@ define void @setnbcr25(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr25:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i64 %a, %b
@@ -438,7 +427,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr26(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setnbcr26(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setnbcr26:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -450,7 +439,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr27(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbcr27(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbcr27:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -461,10 +450,9 @@ define void @setnbcr27(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbcr27:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
@@ -473,7 +461,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr28(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setnbcr28(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setnbcr28:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -485,7 +473,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr29(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbcr29(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr29:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -496,10 +484,9 @@ define void @setnbcr29(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr29:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
@@ -508,7 +495,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr30(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setnbcr30(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setnbcr30:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -520,7 +507,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr31(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbcr31(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr31:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -531,10 +518,9 @@ define void @setnbcr31(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr31:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
@@ -543,7 +529,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr32(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbcr32(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbcr32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpld r3, r4
@@ -555,7 +541,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr33(i64 %a, i64 %b) {
+define dso_local void @setnbcr33(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr33:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -566,10 +552,9 @@ define void @setnbcr33(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr33:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
@@ -578,7 +563,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr34(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setnbcr34(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setnbcr34:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplw r3, r4
@@ -590,7 +575,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr35(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbcr35(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr35:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -601,10 +586,9 @@ define void @setnbcr35(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr35:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
@@ -613,7 +597,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr36(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @setnbcr36(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: setnbcr36:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -625,7 +609,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr37(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbcr37(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbcr37:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -636,10 +620,9 @@ define void @setnbcr37(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbcr37:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, %b
@@ -648,7 +631,7 @@ entry:
   ret void
 }
 
-define void @setnbcr38(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbcr38(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbcr38:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -659,10 +642,9 @@ define void @setnbcr38(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbcr38:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, %b
@@ -671,7 +653,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr39(i64 %a, i64 %b) {
+define dso_local signext i32 @setnbcr39(i64 %a, i64 %b) {
 ; CHECK-LABEL: setnbcr39:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd r3, r4
@@ -683,7 +665,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr40(i64 %a, i64 %b) {
+define dso_local void @setnbcr40(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr40:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -694,10 +676,9 @@ define void @setnbcr40(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr40:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, %b
@@ -706,7 +687,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr41(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @setnbcr41(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: setnbcr41:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -718,7 +699,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr42(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbcr42(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbcr42:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -729,10 +710,9 @@ define void @setnbcr42(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbcr42:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, %b
@@ -741,7 +721,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr43(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @setnbcr43(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: setnbcr43:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -753,7 +733,7 @@ entry:
   ret i32 %sub
 }
 
-define void @sernbcr44(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @sernbcr44(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: sernbcr44:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -764,10 +744,9 @@ define void @sernbcr44(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: sernbcr44:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, %b
@@ -776,7 +755,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr45(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @setnbcr45(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: setnbcr45:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -788,7 +767,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr46(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbcr46(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr46:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -799,10 +778,9 @@ define void @setnbcr46(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr46:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, %b
@@ -811,7 +789,7 @@ entry:
   ret void
 }
 
-define signext i32 @setnbcr47(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @setnbcr47(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: setnbcr47:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw r3, r4
@@ -823,7 +801,7 @@ entry:
   ret i32 %sub
 }
 
-define void @setnbcr48(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbcr48(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr48:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -834,10 +812,9 @@ define void @setnbcr48(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr48:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, %b
@@ -858,7 +835,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr50(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbcr50(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbcr50:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -869,10 +846,9 @@ define void @setnbcr50(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbcr50:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
@@ -893,7 +869,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr52(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbcr52(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbcr52:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -904,10 +880,9 @@ define void @setnbcr52(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbcr52:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
@@ -928,7 +903,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr54(i64 %a, i64 %b) {
+define dso_local void @setnbcr54(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr54:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -939,10 +914,9 @@ define void @setnbcr54(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr54:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i64 %a, %b
@@ -963,7 +937,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr56(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbcr56(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbcr56:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -974,10 +948,9 @@ define void @setnbcr56(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbcr56:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
@@ -998,7 +971,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr58(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbcr58(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr58:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1009,10 +982,9 @@ define void @setnbcr58(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr58:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
@@ -1033,7 +1005,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr60(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbcr60(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr60:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1044,10 +1016,9 @@ define void @setnbcr60(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr60:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
@@ -1068,7 +1039,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr62(i64 %a, i64 %b) {
+define dso_local void @setnbcr62(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr62:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -1079,10 +1050,9 @@ define void @setnbcr62(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr62:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
@@ -1103,7 +1073,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr64(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbcr64(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr64:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1114,10 +1084,9 @@ define void @setnbcr64(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr64:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, lt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
@@ -1138,7 +1107,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr66(i8 signext %a, i8 signext %b) {
+define dso_local void @setnbcr66(i8 signext %a, i8 signext %b) {
 ; CHECK-LE-LABEL: setnbcr66:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -1149,10 +1118,9 @@ define void @setnbcr66(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: setnbcr66:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
@@ -1173,7 +1141,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr68(i32 signext %a, i32 signext %b) {
+define dso_local void @setnbcr68(i32 signext %a, i32 signext %b) {
 ; CHECK-LE-LABEL: setnbcr68:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -1184,10 +1152,9 @@ define void @setnbcr68(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: setnbcr68:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
@@ -1208,7 +1175,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr70(i64 %a, i64 %b) {
+define dso_local void @setnbcr70(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr70:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -1219,10 +1186,9 @@ define void @setnbcr70(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr70:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i64 %a, %b
@@ -1243,7 +1209,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr72(i16 signext %a, i16 signext %b) {
+define dso_local void @setnbcr72(i16 signext %a, i16 signext %b) {
 ; CHECK-LE-LABEL: setnbcr72:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpw r3, r4
@@ -1254,10 +1220,9 @@ define void @setnbcr72(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: setnbcr72:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
@@ -1278,7 +1243,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr74(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @setnbcr74(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr74:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1289,10 +1254,9 @@ define void @setnbcr74(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr74:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, globalVal@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
@@ -1313,7 +1277,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr76(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @setnbcr76(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr76:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1324,10 +1288,9 @@ define void @setnbcr76(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr76:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal2@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, globalVal2@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
@@ -1348,7 +1311,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr78(i64 %a, i64 %b) {
+define dso_local void @setnbcr78(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr78:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpld r3, r4
@@ -1359,10 +1322,9 @@ define void @setnbcr78(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr78:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpld r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
@@ -1383,7 +1345,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @setnbcr80(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @setnbcr80(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LE-LABEL: setnbcr80:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmplw r3, r4
@@ -1394,10 +1356,9 @@ define void @setnbcr80(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: setnbcr80:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplw r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal4@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, gt
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, globalVal4@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
@@ -1430,7 +1391,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @setnbcr83(i64 %a, i64 %b) {
+define dso_local void @setnbcr83(i64 %a, i64 %b) {
 ; CHECK-LE-LABEL: setnbcr83:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cmpd r3, r4
@@ -1441,10 +1402,9 @@ define void @setnbcr83(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: setnbcr83:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpd r3, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
-; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, globalVal3@toc@ha
 ; CHECK-BE-NEXT:    setnbcr r3, eq
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, globalVal3@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp = icmp ne i64 %a, %b

diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll b/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
index 3232945..59aa9b9 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
@@ -8,10 +8,10 @@
 ; These test cases are to ensure that when using pc relative memory operations
 ; ABI correct code and relocations are produced for the Local Exec TLS Model.
 
-@x = thread_local global i32 0, align 4
-@y = thread_local global [5 x i32] [i32 0, i32 0, i32 0, i32 0, i32 0], align 4
+@x = dso_local thread_local global i32 0, align 4
+@y = dso_local thread_local global [5 x i32] [i32 0, i32 0, i32 0, i32 0, i32 0], align 4
 
-define i32* @LocalExecAddressLoad() {
+define dso_local i32* @LocalExecAddressLoad() {
 ; CHECK-S-LABEL: LocalExecAddressLoad:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r3, r13, x@TPREL, 0
@@ -24,7 +24,7 @@ entry:
   ret i32* @x
 }
 
-define i32 @LocalExecValueLoad() {
+define dso_local i32 @LocalExecValueLoad() {
 ; CHECK-S-LABEL: LocalExecValueLoad:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r3, r13, x@TPREL, 0
@@ -40,7 +40,7 @@ entry:
   ret i32 %0
 }
 
-define void @LocalExecValueStore(i32 %in) {
+define dso_local void @LocalExecValueStore(i32 %in) {
 ; CHECK-S-LABEL: LocalExecValueStore:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r4, r13, x@TPREL, 0
@@ -56,7 +56,7 @@ entry:
   ret void
 }
 
-define i32 @LocalExecValueLoadOffset() {
+define dso_local i32 @LocalExecValueLoadOffset() {
 ; CHECK-S-LABEL: LocalExecValueLoadOffset:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r3, r13, y@TPREL, 0
@@ -73,7 +73,7 @@ entry:
 }
 
 
-define i32* @LocalExecValueLoadOffsetNoLoad() {
+define dso_local i32* @LocalExecValueLoadOffsetNoLoad() {
 ; CHECK-S-LABEL: LocalExecValueLoadOffsetNoLoad:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r3, r13, y@TPREL, 0

diff --git a/llvm/test/CodeGen/PowerPC/peephole-align.ll b/llvm/test/CodeGen/PowerPC/peephole-align.ll
index e866b3e..3981e94 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/peephole-align.ll
+++ b/llvm/test/CodeGen/PowerPC/peephole-align.ll
@@ -17,15 +17,15 @@ target triple = "powerpc64-unknown-linux-gnu"
 %struct.d2 = type<{ i64, i64 }>
 %struct.misalign = type<{ i8, i64 }>
 
-@b4v = global %struct.b4 <{ i8 1, i8 2, i8 3, i8 4 }>, align 4
-@h2v = global %struct.h2 <{ i16 1, i16 2 }>, align 4
+@b4v = dso_local global %struct.b4 <{ i8 1, i8 2, i8 3, i8 4 }>, align 4
+@h2v = dso_local global %struct.h2 <{ i16 1, i16 2 }>, align 4
 
-@b8v = global %struct.b8 <{ i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8 }>, align 8
-@h4v = global %struct.h4 <{ i16 1, i16 2, i16 3, i16 4 }>, align 8
-@w2v = global %struct.w2 <{ i32 1, i32 2 }>, align 8
+@b8v = dso_local global %struct.b8 <{ i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8 }>, align 8
+@h4v = dso_local global %struct.h4 <{ i16 1, i16 2, i16 3, i16 4 }>, align 8
+@w2v = dso_local global %struct.w2 <{ i32 1, i32 2 }>, align 8
 
-@d2v = global %struct.d2 <{ i64 1, i64 2 }>, align 16
-@misalign_v = global %struct.misalign <{ i8 1, i64 2 }>, align 16
+@d2v = dso_local global %struct.d2 <{ i64 1, i64 2 }>, align 16
+@misalign_v = dso_local global %struct.misalign <{ i8 1, i64 2 }>, align 16
 
 ; CHECK-LABEL: test_b4:
 ; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, b4v@toc@ha
@@ -42,7 +42,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; CHECK-DAG: stb [[REG2_1]], b4v@toc@l+2([[REGSTRUCT]])
 ; CHECK-DAG: stb [[REG3_1]], b4v@toc@l+3([[REGSTRUCT]])
 
-define void @test_b4() nounwind {
+define dso_local void @test_b4() nounwind {
 entry:
   %0 = load i8, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 0), align 1
   %inc0 = add nsw i8 %0, 1
@@ -68,7 +68,7 @@ entry:
 ; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])
 ; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])
 
-define void @test_h2() nounwind {
+define dso_local void @test_h2() nounwind {
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 0), align 2
   %inc0 = add nsw i16 %0, 1
@@ -87,7 +87,7 @@ entry:
 ; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2
 ; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])
 ; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])
-define void @test_h2_optsize() optsize nounwind {
+define dso_local void @test_h2_optsize() optsize nounwind {
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 0), align 2
   %inc0 = add nsw i16 %0, 1
@@ -125,7 +125,7 @@ entry:
 ; CHECK-DAG: stb [[REG6_1]], b8v@toc@l+6([[REGSTRUCT]])
 ; CHECK-DAG: stb [[REG7_1]], b8v@toc@l+7([[REGSTRUCT]])
 
-define void @test_b8() nounwind {
+define dso_local void @test_b8() nounwind {
 entry:
   %0 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 0), align 1
   %inc0 = add nsw i8 %0, 1
@@ -169,7 +169,7 @@ entry:
 ; CHECK-DAG: sth [[REG2_1]], h4v@toc@l+4([[REGSTRUCT]])
 ; CHECK-DAG: sth [[REG3_1]], h4v@toc@l+6([[REGSTRUCT]])
 
-define void @test_h4() nounwind {
+define dso_local void @test_h4() nounwind {
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 0), align 2
   %inc0 = add nsw i16 %0, 1
@@ -195,7 +195,7 @@ entry:
 ; CHECK-DAG: stw [[REG0_1]], w2v@toc@l([[REGSTRUCT]])
 ; CHECK-DAG: stw [[REG1_1]], w2v@toc@l+4([[REGSTRUCT]])
 
-define void @test_w2() nounwind {
+define dso_local void @test_w2() nounwind {
 entry:
   %0 = load i32, i32* getelementptr inbounds (%struct.w2, %struct.w2* @w2v, i32 0, i32 0), align 4
   %inc0 = add nsw i32 %0, 1
@@ -216,7 +216,7 @@ entry:
 ; CHECK-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]])
 ; CHECK-DAG: std [[REG1_1]], 8([[BASEV]])
 
-define void @test_d2() nounwind {
+define dso_local void @test_d2() nounwind {
 entry:
   %0 = load i64, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 0), align 8
   %inc0 = add nsw i64 %0, 1
@@ -244,7 +244,7 @@ entry:
 ; CHECK: ldx [[REG0_0:[0-9]+]], [[REGSTRUCT]], [[OFFSET_REG]]
 ; CHECK: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1
 ; CHECK: stdx [[REG0_1]], [[REGSTRUCT]], [[OFFSET_REG]]
-define void @test_misalign() nounwind {
+define dso_local void @test_misalign() nounwind {
 entry:
   %0 = load i64, i64* getelementptr inbounds (%struct.misalign, %struct.misalign* @misalign_v, i32 0, i32 1), align 1
   %inc0 = add nsw i64 %0, 1

diff --git a/llvm/test/CodeGen/PowerPC/pie.ll b/llvm/test/CodeGen/PowerPC/pie.ll
index e037b76..8cb8a12 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/pie.ll
+++ b/llvm/test/CodeGen/PowerPC/pie.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-pc-linux -relocation-model=pic | FileCheck %s
 
 
-define void @f() {
+define dso_local void @f() {
   ret void
 }
 
-define void @g() {
+define dso_local void @g() {
 ; CHECK: g:
 ; CHECK: bl f{{$}}
   call void @f()

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-calls.ll b/llvm/test/CodeGen/PowerPC/ppc64-calls.ll
index 87a7460..8975c72 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc64-calls.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-calls.ll
@@ -5,7 +5,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "powerpc64-unknown-linux-gnu"
 
 
-define void @foo() nounwind noinline {
+define dso_local void @foo() nounwind noinline {
   ret void
 }
 
@@ -14,7 +14,7 @@ define weak void @foo_weak() nounwind {
 }
 
 ; Calls to local function does not require the TOC restore 'nop'
-define void @test_direct() nounwind readnone {
+define dso_local void @test_direct() nounwind readnone {
 ; CHECK-LABEL: test_direct:
   tail call void @foo() nounwind
 ; Because of tail call optimization, it can be 'b' instruction.
@@ -26,7 +26,7 @@ define void @test_direct() nounwind readnone {
 ; Calls to weak function requires a TOC restore 'nop' with all code models
 ; because the definition that gets choosen at link time may come from a
 ; different compilation unit that was compiled with PC Relative and has no TOC.
-define void @test_weak() nounwind readnone {
+define dso_local void @test_weak() nounwind readnone {
   tail call void @foo_weak() nounwind
 ; CHECK-LABEL: test_weak:
 ; CHECK:       bl foo_weak
@@ -39,7 +39,7 @@ define void @test_weak() nounwind readnone {
 }
 
 ; Indirect calls requires a full stub creation
-define void @test_indirect(void ()* nocapture %fp) nounwind {
+define dso_local void @test_indirect(void ()* nocapture %fp) nounwind {
 ; CHECK-LABEL: test_indirect:
   tail call void %fp() nounwind
 ; CHECK: ld [[FP:[0-9]+]], 0(3)
@@ -54,7 +54,7 @@ define void @test_indirect(void ()* nocapture %fp) nounwind {
 ; Absolute values must use the regular indirect call sequence
 ; The main purpose of this test is to ensure that BLA is not
 ; used on 64-bit SVR4 (as e.g. on Darwin).
-define void @test_abs() nounwind {
+define dso_local void @test_abs() nounwind {
 ; CHECK-LABEL: test_abs:
   tail call void inttoptr (i64 1024 to void ()*)() nounwind
 ; CHECK: ld [[FP:[0-9]+]], 1024(0)
@@ -81,7 +81,7 @@ define double @test_external(double %x) nounwind {
 ; the unwinding code in libgcc happy.
 @g = external global void ()*
 declare void @h(i64)
-define void @test_indir_toc_reload(i64 %x) {
+define dso_local void @test_indir_toc_reload(i64 %x) {
   %1 = load void ()*, void ()** @g
   call void %1()
   call void @h(i64 %x)

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll b/llvm/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll
index 34a9aa9..7d1c235 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll
@@ -4,12 +4,12 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 %struct.cd = type { i64, i64, i64 }
 
-@something = global [33 x i8] c"this is not really code, but...\0A\00", align 1
-@tls_something = thread_local global %struct.cd zeroinitializer, align 8
+@something = dso_local global [33 x i8] c"this is not really code, but...\0A\00", align 1
+@tls_something = dso_local thread_local global %struct.cd zeroinitializer, align 8
 @extern_something = external global %struct.cd
 
 ; Function Attrs: nounwind
-define void @foo() #0 {
+define dso_local void @foo() #0 {
 entry:
   tail call void bitcast ([33 x i8]* @something to void ()*)() #0
   ret void
@@ -28,7 +28,7 @@ entry:
 }
 
 ; Function Attrs: nounwind
-define void @bar() #0 {
+define dso_local void @bar() #0 {
 entry:
   tail call void bitcast (%struct.cd* @tls_something to void ()*)() #0
   ret void
@@ -47,7 +47,7 @@ entry:
 }
 
 ; Function Attrs: nounwind
-define void @ext() #0 {
+define dso_local void @ext() #0 {
 entry:
   tail call void bitcast (%struct.cd* @extern_something to void ()*)() #0
   ret void

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
index 251cd66..82d2ec6 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
@@ -6,7 +6,7 @@
 %"class.clang::NamedDecl" = type { i32 }
 declare void @__assert_fail();
 
-define i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv(
+define dso_local i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv(
     %"class.clang::NamedDecl"* %this) {
 entry:
   %tobool = icmp eq %"class.clang::NamedDecl"* %this, null
@@ -39,7 +39,7 @@ exit:
 ; CHECK-SCO-ONLY: bl __assert_fail
 }
 
-define fastcc i8 @LVComputationKind(
+define dso_local fastcc i8 @LVComputationKind(
     %"class.clang::NamedDecl"* %D,
     i32 %computation) {
   ret i8 0

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll
index f30bd54..6671f79 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll
@@ -11,11 +11,11 @@
 %S_32 = type { [7 x i32], i32 }
 
 ; Function Attrs: noinline nounwind
-define void @callee_56_copy([7 x i64] %a, %S_56* %b) #0 { ret void }
-define void @callee_64_copy([8 x i64] %a, %S_64* %b) #0 { ret void }
+define dso_local void @callee_56_copy([7 x i64] %a, %S_56* %b) #0 { ret void }
+define dso_local void @callee_64_copy([8 x i64] %a, %S_64* %b) #0 { ret void }
 
 ; Function Attrs: nounwind
-define void @caller_56_reorder_copy(%S_56* %b, [7 x i64] %a) #1 {
+define dso_local void @caller_56_reorder_copy(%S_56* %b, [7 x i64] %a) #1 {
   tail call void @callee_56_copy([7 x i64] %a, %S_56* %b)
   ret void
 
@@ -24,7 +24,7 @@ define void @caller_56_reorder_copy(%S_56* %b, [7 x i64] %a) #1 {
 ; CHECK-SCO: TC_RETURNd8 callee_56_copy
 }
 
-define void @caller_64_reorder_copy(%S_64* %b, [8 x i64] %a) #1 {
+define dso_local void @caller_64_reorder_copy(%S_64* %b, [8 x i64] %a) #1 {
   tail call void @callee_64_copy([8 x i64] %a, %S_64* %b)
   ret void
 
@@ -32,8 +32,8 @@ define void @caller_64_reorder_copy(%S_64* %b, [8 x i64] %a) #1 {
 ; CHECK-SCO: bl callee_64_copy
 }
 
-define void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b) #0 { ret void }
-define void @caller_64_64_copy([8 x i64] %a, [8 x i64] %b) #1 {
+define dso_local void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b) #0 { ret void }
+define dso_local void @caller_64_64_copy([8 x i64] %a, [8 x i64] %b) #1 {
   tail call void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b)
   ret void
 
@@ -42,7 +42,7 @@ define void @caller_64_64_copy([8 x i64] %a, [8 x i64] %b) #1 {
 }
 
 define internal fastcc void @callee_64_64_copy_fastcc([8 x i64] %a, [8 x i64] %b) #0 { ret void }
-define void @caller_64_64_copy_ccc([8 x i64] %a, [8 x i64] %b) #1 {
+define dso_local void @caller_64_64_copy_ccc([8 x i64] %a, [8 x i64] %b) #1 {
   tail call fastcc void @callee_64_64_copy_fastcc([8 x i64] %a, [8 x i64] %b)
   ret void
 ; If caller and callee use different calling convensions, we cannot apply TCO.
@@ -50,7 +50,7 @@ define void @caller_64_64_copy_ccc([8 x i64] %a, [8 x i64] %b) #1 {
 ; CHECK-SCO: bl callee_64_64_copy_fastcc
 }
 
-define void @caller_64_64_reorder_copy([8 x i64] %a, [8 x i64] %b) #1 {
+define dso_local void @caller_64_64_reorder_copy([8 x i64] %a, [8 x i64] %b) #1 {
   tail call void @callee_64_64_copy([8 x i64] %b, [8 x i64] %a)
   ret void
 
@@ -58,7 +58,7 @@ define void @caller_64_64_reorder_copy([8 x i64] %a, [8 x i64] %b) #1 {
 ; CHECK-SCO: bl callee_64_64_copy
 }
 
-define void @caller_64_64_undef_copy([8 x i64] %a, [8 x i64] %b) #1 {
+define dso_local void @caller_64_64_undef_copy([8 x i64] %a, [8 x i64] %b) #1 {
   tail call void @callee_64_64_copy([8 x i64] %a, [8 x i64] undef)
   ret void
 
@@ -66,14 +66,14 @@ define void @caller_64_64_undef_copy([8 x i64] %a, [8 x i64] %b) #1 {
 ; CHECK-SCO: b callee_64_64_copy
 }
 
-define void @arg8_callee(
+define dso_local void @arg8_callee(
   float %a, i32 signext %b, float %c, i32* %d,
   i8 zeroext %e, float %f, i32* %g, i32 signext %h)
 {
   ret void
 }
 
-define void @arg8_caller(float %a, i32 signext %b, i8 zeroext %c, i32* %d) {
+define dso_local void @arg8_caller(float %a, i32 signext %b, i8 zeroext %c, i32* %d) {
 entry:
   tail call void @arg8_callee(float undef, i32 signext undef, float undef,
                               i32* %d, i8 zeroext undef, float undef,
@@ -87,11 +87,11 @@ entry:
 ; Struct return test
 
 ; Function Attrs: noinline nounwind
-define void @callee_sret_56(%S_56* noalias sret(%S_56) %agg.result) #0 { ret void }
-define void @callee_sret_32(%S_32* noalias sret(%S_32) %agg.result) #0 { ret void }
+define dso_local void @callee_sret_56(%S_56* noalias sret(%S_56) %agg.result) #0 { ret void }
+define dso_local void @callee_sret_32(%S_32* noalias sret(%S_32) %agg.result) #0 { ret void }
 
 ; Function Attrs: nounwind
-define void @caller_do_something_sret_32(%S_32* noalias sret(%S_32) %agg.result) #1 {
+define dso_local void @caller_do_something_sret_32(%S_32* noalias sret(%S_32) %agg.result) #1 {
   %1 = alloca %S_56, align 4
   %2 = bitcast %S_56* %1 to i8*
   call void @callee_sret_56(%S_56* nonnull sret(%S_56) %1)
@@ -105,7 +105,7 @@ define void @caller_do_something_sret_32(%S_32* noalias sret(%S_32) %agg.result)
 ; CHECK-SCO: TC_RETURNd8 callee_sret_32
 }
 
-define void @caller_local_sret_32(%S_32* %a) #1 {
+define dso_local void @caller_local_sret_32(%S_32* %a) #1 {
   %tmp = alloca %S_32, align 4
   tail call void @callee_sret_32(%S_32* nonnull sret(%S_32) %tmp)
   ret void
@@ -117,8 +117,8 @@ define void @caller_local_sret_32(%S_32* %a) #1 {
 attributes #0 = { noinline nounwind  }
 attributes #1 = { nounwind }
 
-define void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) { ret void }
-define void @f128_caller(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) {
+define dso_local void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) { ret void }
+define dso_local void @f128_caller(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) {
   tail call void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b)
   ret void
 
@@ -130,7 +130,7 @@ define void @f128_caller(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) {
 %class.T = type { [2 x i8] }
 
 define weak_odr hidden void @wo_hcallee(%class.T* %this, i8* %c) { ret void }
-define void @wo_hcaller(%class.T* %this, i8* %c) {
+define dso_local void @wo_hcaller(%class.T* %this, i8* %c) {
   tail call void @wo_hcallee(%class.T* %this, i8* %c)
   ret void
 
@@ -142,7 +142,7 @@ define void @wo_hcaller(%class.T* %this, i8* %c) {
 }
 
 define weak_odr protected void @wo_pcallee(%class.T* %this, i8* %c) { ret void }
-define void @wo_pcaller(%class.T* %this, i8* %c) {
+define dso_local void @wo_pcaller(%class.T* %this, i8* %c) {
   tail call void @wo_pcallee(%class.T* %this, i8* %c)
   ret void
 
@@ -154,7 +154,7 @@ define void @wo_pcaller(%class.T* %this, i8* %c) {
 }
 
 define weak_odr void @wo_callee(%class.T* %this, i8* %c) { ret void }
-define void @wo_caller(%class.T* %this, i8* %c) {
+define dso_local void @wo_caller(%class.T* %this, i8* %c) {
   tail call void @wo_callee(%class.T* %this, i8* %c)
   ret void
 
@@ -166,7 +166,7 @@ define void @wo_caller(%class.T* %this, i8* %c) {
 }
 
 define weak protected void @w_pcallee(i8* %ptr) { ret void }
-define void @w_pcaller(i8* %ptr) {
+define dso_local void @w_pcaller(i8* %ptr) {
   tail call void @w_pcallee(i8* %ptr)
   ret void
 
@@ -178,7 +178,7 @@ define void @w_pcaller(i8* %ptr) {
 }
 
 define weak hidden void @w_hcallee(i8* %ptr) { ret void }
-define void @w_hcaller(i8* %ptr) {
+define dso_local void @w_hcaller(i8* %ptr) {
   tail call void @w_hcallee(i8* %ptr)
   ret void
 
@@ -190,7 +190,7 @@ define void @w_hcaller(i8* %ptr) {
 }
 
 define weak void @w_callee(i8* %ptr) { ret void }
-define void @w_caller(i8* %ptr) {
+define dso_local void @w_caller(i8* %ptr) {
   tail call void @w_callee(i8* %ptr)
   ret void
 
@@ -204,8 +204,8 @@ define void @w_caller(i8* %ptr) {
 %struct.byvalTest = type { [8 x i8] }
 @byval = common global %struct.byvalTest zeroinitializer
 
-define void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) %ptr) { ret void }
-define void @byval_caller() {
+define dso_local void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) %ptr) { ret void }
+define dso_local void @byval_caller() {
   tail call void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) @byval)
   ret void
 

diff --git a/llvm/test/CodeGen/PowerPC/pr32140.ll b/llvm/test/CodeGen/PowerPC/pr32140.ll
index 1a0054b..bd0b267 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/pr32140.ll
+++ b/llvm/test/CodeGen/PowerPC/pr32140.ll
@@ -2,12 +2,12 @@
 ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE
 ; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE
 
-@as = local_unnamed_addr global i16 0, align 2
-@bs = local_unnamed_addr global i16 0, align 2
-@ai = local_unnamed_addr global i32 0, align 4
-@bi = local_unnamed_addr global i32 0, align 4
+@as = dso_local local_unnamed_addr global i16 0, align 2
+@bs = dso_local local_unnamed_addr global i16 0, align 2
+@ai = dso_local local_unnamed_addr global i32 0, align 4
+@bi = dso_local local_unnamed_addr global i32 0, align 4
 
-define void @bswapStorei64Toi32() {
+define dso_local void @bswapStorei64Toi32() {
 ; CHECK-LABEL: bswapStorei64Toi32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, ai@toc@ha
@@ -29,11 +29,10 @@ define void @bswapStorei64Toi32() {
 ;
 ; CHECK-BE-LABEL: bswapStorei64Toi32:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LC0@toc@ha
-; CHECK-BE-NEXT:    addis 4, 2, .LC1@toc@ha
-; CHECK-BE-NEXT:    ld 3, .LC0@toc@l(3)
-; CHECK-BE-NEXT:    ld 4, .LC1@toc@l(4)
-; CHECK-BE-NEXT:    lwa 3, 0(3)
+; CHECK-BE-NEXT:    addis 3, 2, ai@toc@ha
+; CHECK-BE-NEXT:    addis 4, 2, bi@toc@ha
+; CHECK-BE-NEXT:    lwa 3, ai@toc@l(3)
+; CHECK-BE-NEXT:    addi 4, 4, bi@toc@l
 ; CHECK-BE-NEXT:    rldicl 3, 3, 32, 32
 ; CHECK-BE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-BE-NEXT:    blr
@@ -46,7 +45,7 @@ entry:
   ret void
 }
 
-define void @bswapStorei32Toi16() {
+define dso_local void @bswapStorei32Toi16() {
 ; CHECK-LABEL: bswapStorei32Toi16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, as@toc@ha
@@ -68,11 +67,10 @@ define void @bswapStorei32Toi16() {
 ;
 ; CHECK-BE-LABEL: bswapStorei32Toi16:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LC2@toc@ha
-; CHECK-BE-NEXT:    addis 4, 2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld 3, .LC2@toc@l(3)
-; CHECK-BE-NEXT:    ld 4, .LC3@toc@l(4)
-; CHECK-BE-NEXT:    lha 3, 0(3)
+; CHECK-BE-NEXT:    addis 3, 2, as@toc@ha
+; CHECK-BE-NEXT:    addis 4, 2, bs@toc@ha
+; CHECK-BE-NEXT:    lha 3, as@toc@l(3)
+; CHECK-BE-NEXT:    addi 4, 4, bs@toc@l
 ; CHECK-BE-NEXT:    srwi 3, 3, 16
 ; CHECK-BE-NEXT:    sthbrx 3, 0, 4
 ; CHECK-BE-NEXT:    blr
@@ -85,7 +83,7 @@ entry:
   ret void
 }
 
-define void @bswapStorei64Toi16() {
+define dso_local void @bswapStorei64Toi16() {
 ; CHECK-LABEL: bswapStorei64Toi16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, as@toc@ha
@@ -107,11 +105,10 @@ define void @bswapStorei64Toi16() {
 ;
 ; CHECK-BE-LABEL: bswapStorei64Toi16:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LC2@toc@ha
-; CHECK-BE-NEXT:    addis 4, 2, .LC3@toc@ha
-; CHECK-BE-NEXT:    ld 3, .LC2@toc@l(3)
-; CHECK-BE-NEXT:    ld 4, .LC3@toc@l(4)
-; CHECK-BE-NEXT:    lha 3, 0(3)
+; CHECK-BE-NEXT:    addis 3, 2, as@toc@ha
+; CHECK-BE-NEXT:    addis 4, 2, bs@toc@ha
+; CHECK-BE-NEXT:    lha 3, as@toc@l(3)
+; CHECK-BE-NEXT:    addi 4, 4, bs@toc@l
 ; CHECK-BE-NEXT:    rldicl 3, 3, 16, 48
 ; CHECK-BE-NEXT:    sthbrx 3, 0, 4
 ; CHECK-BE-NEXT:    blr

diff --git a/llvm/test/CodeGen/PowerPC/preemption.ll b/llvm/test/CodeGen/PowerPC/preemption.ll
deleted file mode 100644 (file)
index 849b505..0000000
--- a/llvm/test/CodeGen/PowerPC/preemption.ll
+++ /dev/null
@@ -1,302 +0,0 @@
-; RUN: llc -mtriple powerpc64le-unknown-gnu-linux  -relocation-model=pic \
-; RUN: < %s |  FileCheck %s
-; RUN: llc -mtriple powerpc64le-unknown-gnu-linux -relocation-model=static \
-; RUN: < %s |  FileCheck --check-prefix=STATIC %s
-; RUN: llc -mtriple powerpc64le-unknown-gnu-linux -relocation-model=pic \
-; RUN: < %s |  FileCheck %s
-
-; globals
-
-@strong_default = global i32 55
-define i32* @get_strong_default() #0 {
-  ret i32* @strong_default
-
-; STATIC-LABEL: @get_strong_default
-; STATIC: addis 3, 2, strong_default@toc@ha
-; STATIC: addi 3, 3, strong_default@toc@l
-; STATIC: blr
-
-; CHECK-LABEL: @get_strong_default
-; CHECK: addis 3, 2, .LC0@toc@ha
-; CHECK: ld 3, .LC0@toc@l(3)
-; CHECK: blr
-}
-
-@weak_default = weak global i32 55
-define i32* @get_weak_default() #0 {
-  ret i32* @weak_default
-
-; STATIC-LABEL: @get_weak_default
-; STATIC: addis 3, 2, weak_default@toc@ha
-; STATIC: addi 3, 3, weak_default@toc@l
-; STATIC: blr
-
-; CHECK-LABEL: @get_weak_default
-; CHECK: addis 3, 2, .LC1@toc@ha
-; CHECK: ld 3, .LC1@toc@l(3)
-; CHECK: blr
-}
-
-@external_default_global = external global i32
-define i32* @get_external_default_global() {
-  ret i32* @external_default_global
-
-; STATIC-LABEL: @get_external_default_global
-; STATIC: addis 3, 2, .LC0@toc@ha
-; STATIC: ld 3, .LC0@toc@l(3)
-; STATIC: blr
-
-; CHECK-LABEL: @get_external_default_global
-; CHECK: addis 3, 2, .LC2@toc@ha
-; CHECK: ld 3, .LC2@toc@l(3)
-; CHECK: blr
-}
-
-
-@strong_local_global = dso_local global i32 55
-define i32* @get_strong_local_global() {
-  ret i32* @strong_local_global
-
-; STATIC-LABEL: @get_strong_local_global
-; STATIC:       addis 3, 2, strong_local_global@toc@ha
-; STATIC:       addi 3, 3, strong_local_global@toc@l
-; STATIC:       blr
-
-; CHECK-LABEL: @get_strong_local_global
-; CHECK:       addis 3, 2, strong_local_global@toc@ha
-; CHECK:       addi 3, 3, strong_local_global@toc@l
-; CHECK:       blr
-}
-
-@weak_local_global = weak dso_local global i32 42
-define i32* @get_weak_local_global() {
-  ret i32* @weak_local_global
-
-; STATIC-LABEL: @get_weak_local_global
-; STATIC:       addis 3, 2, weak_local_global@toc@ha
-; STATIC:       addi 3, 3, weak_local_global@toc@l
-; STATIC:       blr
-
-; CHECK-LABEL: @get_weak_local_global
-; CHECK:       addis 3, 2, weak_local_global@toc@ha
-; CHECK:       addi 3, 3, weak_local_global@toc@l
-; CHECK:       blr
-}
-
-@external_local_global = external dso_local global i32
-define i32* @get_external_local_global() {
-  ret i32* @external_local_global
-; STATIC-LABEL: @get_external_local_global
-; STATIC:       addis 3, 2, external_local_global@toc@ha
-; STATIC:       addi 3, 3, external_local_global@toc@l
-; STATIC:       blr
-
-; CHECK-LABEL: @get_external_local_global
-; CHECK:       addis 3, 2, external_local_global@toc@ha
-; CHECK:       addi 3, 3, external_local_global@toc@l
-; CHECK:       blr
-}
-
-@strong_preemptable_global = dso_preemptable global i32 42
-define i32* @get_strong_preemptable_global() {
-  ret i32* @strong_preemptable_global
-
-; STATIC-LABEL: @get_strong_preemptable_global
-; STATIC: addis 3, 2, strong_preemptable_global@toc@ha
-; STATIC: addi 3, 3, strong_preemptable_global@toc@l
-; STATIC: blr
-
-; CHECK-LABEL: @get_strong_preemptable_global
-; CHECK: addis 3, 2, .LC3@toc@ha
-; CHECK: ld 3, .LC3@toc@l(3)
-; CHECK: blr
-}
-
-@weak_preemptable_global = weak dso_preemptable global i32 42
-define i32* @get_weak_preemptable_global() {
-  ret i32* @weak_preemptable_global
-
-; STATIC-LABEL: @get_weak_preemptable_global
-; STATIC: addis 3, 2, weak_preemptable_global@toc@ha
-; STATIC: addi 3, 3, weak_preemptable_global@toc@l
-; STATIC: blr
-
-; CHECK-LABEL: @get_weak_preemptable_global
-; CHECK: addis 3, 2, .LC4@toc@ha
-; CHECK: ld 3, .LC4@toc@l(3)
-; CHECK: blr
-}
-
-@external_preemptable_global = external dso_preemptable global i32
-define i32* @get_external_preemptable_global() {
-  ret i32* @external_preemptable_global
-
-; STATIC-LABEL: @get_external_preemptable_global
-; STATIC: addis 3, 2, .LC1@toc@ha
-; STATIC: ld 3, .LC1@toc@l(3)
-; STATIC: blr
-
-; CHECK-LABEL: @get_external_preemptable_global
-; CHECK: addis 3, 2, .LC5@toc@ha
-; CHECK: ld 3, .LC5@toc@l(3)
-; CHECK: blr
-}
-
-; functions
-define signext i32 @strong_default_function(i32 %i) {
-  ret i32 %i
-}
-define signext i32 @strong_default_function_caller(i32 %i) {
-  %call = notail call signext i32 @strong_default_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @strong_default_function_caller
-; STATIC:       bl strong_default_function
-; STATIC-NOT:   nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @strong_default_function_caller
-; CHECK:        bl strong_default_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-define weak signext i32 @weak_default_function(i32 %i) {
-  ret i32 %i
-}
-define signext i32 @weak_default_function_caller(i32 %i) {
-  %call = notail call signext i32 @weak_default_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @weak_default_function_caller
-; STATIC:       bl weak_default_function
-; STATIC-NEXT:  nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @weak_default_function_caller
-; CHECK:        bl weak_default_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-
-declare i32 @external_default_function(i32 %i)
-define i32 @external_default_function_caller(i32 %i) {
-  %call = notail call signext i32  @external_default_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @external_default_function_caller
-; STATIC:       bl external_default_function
-; STATIC-NEXT:  nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @external_default_function_caller
-; CHECK:        bl external_default_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-define dso_local signext i32 @strong_local_function(i32 %i) {
-  ret i32 %i
-}
-define signext i32 @strong_local_function_caller(i32 %i) {
-  %call = notail call signext i32 @strong_local_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @strong_local_function_caller
-; STATIC:       bl strong_local_function
-; STATIC-NOT:   nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @strong_local_function_caller
-; CHECK:        bl strong_local_function
-; CHECK-NOT:    nop
-; CHECK:        blr
-}
-
-define weak dso_local signext i32 @weak_local_function(i32 %i) {
-  ret i32 %i
-}
-define signext i32 @weak_local_function_caller(i32 %i) {
-  %call = notail call signext i32 @weak_local_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @weak_local_function_caller
-; STATIC:       bl weak_local_function
-; STATIC-NEXT:  nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @weak_local_function_caller
-; CHECK:        bl weak_local_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-declare dso_local i32 @external_local_function(i32 %i)
-define i32 @external_local_function_caller(i32 %i) {
-  %call = notail call signext i32  @external_local_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @external_local_function_caller
-; STATIC:       bl external_local_function
-; STATIC-NEXT:  nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @external_local_function_caller
-; CHECK:        bl external_local_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-define dso_preemptable signext i32 @strong_preemptable_function(i32 %i) {
-  ret i32 %i
-}
-define signext i32 @strong_preemptable_function_caller(i32 %i) {
-  %call = notail call signext i32 @strong_preemptable_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @strong_preemptable_function_caller
-; STATIC:       bl strong_preemptable_function
-; STATIC-NOT:   nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @strong_preemptable_function_caller
-; CHECK:        bl strong_preemptable_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-define weak dso_preemptable signext i32 @weak_preemptable_function(i32 %i) {
-  ret i32 %i
-}
-define signext i32 @weak_preemptable_function_caller(i32 %i) {
-  %call = notail call signext i32 @weak_preemptable_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @weak_preemptable_function_caller
-; STATIC:       bl weak_preemptable_function
-; STATIC-NEXT:  nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @weak_preemptable_function_caller
-; CHECK:        bl weak_preemptable_function
-; CHECK-NEXT:   nop
-; CHECK:        blr
-}
-
-declare dso_preemptable i32 @external_preemptable_function(i32 %i)
-define i32 @external_preemptable_function_caller(i32 %i) {
-  %call = notail call signext i32  @external_preemptable_function(i32 signext %i)
-  ret i32 %call
-
-; STATIC-LABEL: @external_preemptable_function_caller
-; STATIC:       bl external_preemptable_function
-; STATIC-NEXT:   nop
-; STATIC:       blr
-
-; CHECK-LABEL:  @external_preemptable_function_caller
-; CHECK:        bl external_preemptable_function
-; CHECK-NEXT:    nop
-; CHECK:        blr
-}
-

diff --git a/llvm/test/CodeGen/PowerPC/sched-addi.ll b/llvm/test/CodeGen/PowerPC/sched-addi.ll
index 19647b6..9cfe20e 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/sched-addi.ll
+++ b/llvm/test/CodeGen/PowerPC/sched-addi.ll
@@ -7,9 +7,9 @@
 %_elem_type_of_x = type <{ double }>
 %_elem_type_of_a = type <{ double }>
 
-@scalars = common local_unnamed_addr global %_type_of_scalars zeroinitializer, align 16
+@scalars = common dso_local local_unnamed_addr global %_type_of_scalars zeroinitializer, align 16
 
-define void @test([0 x %_elem_type_of_x]* noalias %.x, [0 x %_elem_type_of_a]* %.a, i64* noalias %.n) {
+define dso_local void @test([0 x %_elem_type_of_x]* noalias %.x, [0 x %_elem_type_of_a]* %.a, i64* noalias %.n) {
 ; CHECK-P9-LABEL: test:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    ld 5, 0(5)

diff --git a/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll b/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
index 244dac5..64709d0 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
+++ b/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
@@ -87,7 +87,7 @@ define dso_local double @speculatable_callee_intermediate_instructions (double*
 }
 
 
-define double @callee(double) #1 {
+define dso_local double @callee(double) #1 {
   ret double 4.5
 }
 

diff --git a/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll b/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll
index 86e7021..edf8c55 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll
+++ b/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll
@@ -18,13 +18,13 @@ target triple = "powerpc64le-linux-gnu"
 
 declare void @TestBaz(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg)
 
-define void @TestBar(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) {
+define dso_local void @TestBar(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) {
 bb:
   call void @TestBaz(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg)
   ret void
 }
 
-define void @TestFoo(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) {
+define dso_local void @TestFoo(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) {
 ; CHECK-LABEL: TestFoo:
 ; CHECK: #TC_RETURNd8 TestBar 0
 bb:

diff --git a/llvm/test/CodeGen/PowerPC/tailcall1-64.ll b/llvm/test/CodeGen/PowerPC/tailcall1-64.ll
index 58ab0bc..2843101 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/tailcall1-64.ll
+++ b/llvm/test/CodeGen/PowerPC/tailcall1-64.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=ppc64-- -tailcallopt | grep TC_RETURNd8
 ; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple=ppc64-- < %s | FileCheck %s
-define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+define dso_local fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
 entry:
        ret i32 %a3
 }
 
-define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+define dso_local fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
 entry:
        %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 )
        ret i32 %tmp11

diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
index fe4376c..4ecaf27 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -26,19 +26,18 @@
 declare signext i32 @fn2(...) local_unnamed_addr #1
 
 ; Function Attrs: nounwind
-define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind {
+define dso_local i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind {
 ; BE-LABEL: testCompare1:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    mflr r0
 ; BE-NEXT:    std r0, 16(r1)
 ; BE-NEXT:    stdu r1, -112(r1)
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; BE-NEXT:    lbz r3, 0(r3)
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; BE-NEXT:    clrlwi r3, r3, 31
-; BE-NEXT:    clrldi r3, r3, 32
-; BE-NEXT:    lbz r4, 0(r4)
 ; BE-NEXT:    clrlwi r4, r4, 31
+; BE-NEXT:    clrldi r3, r3, 32
 ; BE-NEXT:    clrldi r4, r4, 32
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    rldicl r3, r3, 1, 63
@@ -54,13 +53,12 @@ define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind
 ; LE-NEXT:    mflr r0
 ; LE-NEXT:    std r0, 16(r1)
 ; LE-NEXT:    stdu r1, -32(r1)
-; LE-NEXT:    addis r4, r2, .LC0@toc@ha
+; LE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; LE-NEXT:    lbz r3, 0(r3)
-; LE-NEXT:    ld r4, .LC0@toc@l(r4)
+; LE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; LE-NEXT:    clrlwi r3, r3, 31
-; LE-NEXT:    clrldi r3, r3, 32
-; LE-NEXT:    lbz r4, 0(r4)
 ; LE-NEXT:    clrlwi r4, r4, 31
+; LE-NEXT:    clrldi r3, r3, 32
 ; LE-NEXT:    clrldi r4, r4, 32
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    rldicl r3, r3, 1, 63
@@ -88,11 +86,10 @@ define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind
 ; CHECK-P10-BE-NEXT:    mflr r0
 ; CHECK-P10-BE-NEXT:    std r0, 16(r1)
 ; CHECK-P10-BE-NEXT:    stdu r1, -112(r1)
-; CHECK-P10-BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-P10-BE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; CHECK-P10-BE-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P10-BE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; CHECK-P10-BE-NEXT:    clrlwi r3, r3, 31
-; CHECK-P10-BE-NEXT:    lbz r4, 0(r4)
 ; CHECK-P10-BE-NEXT:    clrlwi r4, r4, 31
 ; CHECK-P10-BE-NEXT:    cmplw r4, r3
 ; CHECK-P10-BE-NEXT:    setbc r3, gt
@@ -108,13 +105,12 @@ define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind
 ; CHECK-P10-CMP-LE-NEXT:    mflr r0
 ; CHECK-P10-CMP-LE-NEXT:    std r0, 16(r1)
 ; CHECK-P10-CMP-LE-NEXT:    stdu r1, -112(r1)
-; CHECK-P10-CMP-LE-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-P10-CMP-LE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; CHECK-P10-CMP-LE-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-CMP-LE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P10-CMP-LE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; CHECK-P10-CMP-LE-NEXT:    clrlwi r3, r3, 31
-; CHECK-P10-CMP-LE-NEXT:    clrldi r3, r3, 32
-; CHECK-P10-CMP-LE-NEXT:    lbz r4, 0(r4)
 ; CHECK-P10-CMP-LE-NEXT:    clrlwi r4, r4, 31
+; CHECK-P10-CMP-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-CMP-LE-NEXT:    clrldi r4, r4, 32
 ; CHECK-P10-CMP-LE-NEXT:    sub r3, r3, r4
 ; CHECK-P10-CMP-LE-NEXT:    rldicl r3, r3, 1, 63
@@ -152,7 +148,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 31

diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
index 10dcc1d..0ecd1a1 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -28,19 +28,18 @@
 declare signext i32 @fn2(...) local_unnamed_addr #1
 
 ; Function Attrs: nounwind
-define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind {
+define dso_local i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind {
 ; BE-LABEL: testCompare1:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    mflr r0
 ; BE-NEXT:    std r0, 16(r1)
 ; BE-NEXT:    stdu r1, -112(r1)
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; BE-NEXT:    lbz r3, 0(r3)
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; BE-NEXT:    clrlwi r3, r3, 31
-; BE-NEXT:    clrldi r3, r3, 32
-; BE-NEXT:    lbz r4, 0(r4)
 ; BE-NEXT:    clrlwi r4, r4, 31
+; BE-NEXT:    clrldi r3, r3, 32
 ; BE-NEXT:    clrldi r4, r4, 32
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    rldicl r3, r3, 1, 63
@@ -56,13 +55,12 @@ define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind
 ; LE-NEXT:    mflr r0
 ; LE-NEXT:    std r0, 16(r1)
 ; LE-NEXT:    stdu r1, -32(r1)
-; LE-NEXT:    addis r4, r2, .LC0@toc@ha
+; LE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; LE-NEXT:    lbz r3, 0(r3)
-; LE-NEXT:    ld r4, .LC0@toc@l(r4)
+; LE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; LE-NEXT:    clrlwi r3, r3, 31
-; LE-NEXT:    clrldi r3, r3, 32
-; LE-NEXT:    lbz r4, 0(r4)
 ; LE-NEXT:    clrlwi r4, r4, 31
+; LE-NEXT:    clrldi r3, r3, 32
 ; LE-NEXT:    clrldi r4, r4, 32
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    rldicl r3, r3, 1, 63
@@ -90,11 +88,10 @@ define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind
 ; CHECK-P10-BE-NEXT:    mflr r0
 ; CHECK-P10-BE-NEXT:    std r0, 16(r1)
 ; CHECK-P10-BE-NEXT:    stdu r1, -112(r1)
-; CHECK-P10-BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-P10-BE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; CHECK-P10-BE-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P10-BE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; CHECK-P10-BE-NEXT:    clrlwi r3, r3, 31
-; CHECK-P10-BE-NEXT:    lbz r4, 0(r4)
 ; CHECK-P10-BE-NEXT:    clrlwi r4, r4, 31
 ; CHECK-P10-BE-NEXT:    cmplw r4, r3
 ; CHECK-P10-BE-NEXT:    setbc r3, lt
@@ -110,13 +107,12 @@ define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) nounwind
 ; CHECK-P10-CMP-LE-NEXT:    mflr r0
 ; CHECK-P10-CMP-LE-NEXT:    std r0, 16(r1)
 ; CHECK-P10-CMP-LE-NEXT:    stdu r1, -112(r1)
-; CHECK-P10-CMP-LE-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-P10-CMP-LE-NEXT:    addis r4, r2, testCompare1@toc@ha
 ; CHECK-P10-CMP-LE-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-CMP-LE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P10-CMP-LE-NEXT:    lbz r4, testCompare1@toc@l(r4)
 ; CHECK-P10-CMP-LE-NEXT:    clrlwi r3, r3, 31
-; CHECK-P10-CMP-LE-NEXT:    clrldi r3, r3, 32
-; CHECK-P10-CMP-LE-NEXT:    lbz r4, 0(r4)
 ; CHECK-P10-CMP-LE-NEXT:    clrlwi r4, r4, 31
+; CHECK-P10-CMP-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-CMP-LE-NEXT:    clrldi r4, r4, 32
 ; CHECK-P10-CMP-LE-NEXT:    sub r3, r4, r3
 ; CHECK-P10-CMP-LE-NEXT:    rldicl r3, r3, 1, 63
@@ -153,7 +149,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    clrlwi r3, r3, 31

diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
index 8b5cade..f3f76d5 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -67,7 +67,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsc_z(i8 signext %a) {
+define dso_local signext i32 @test_ieqsc_z(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -91,7 +91,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
+define dso_local signext i32 @test_ieqsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsc_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsc_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsc_z_store(i8 signext %a) {
+define dso_local void @test_ieqsc_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_ieqsc_z_store(i8 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsc_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsc_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsc_sext_z_store(i8 signext %a) {
+define dso_local void @test_ieqsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_ieqsc_sext_z_store(i8 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsc_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsc_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll
index d405741..ce1a588 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -67,7 +67,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsi_z(i32 signext %a) {
+define dso_local signext i32 @test_ieqsi_z(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -91,7 +91,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
+define dso_local signext i32 @test_ieqsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsi_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsi_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsi_z_store(i32 signext %a) {
+define dso_local void @test_ieqsi_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_ieqsi_z_store(i32 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsi_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsi_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsi_sext_z_store(i32 signext %a) {
+define dso_local void @test_ieqsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_ieqsi_sext_z_store(i32 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsi_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsi_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll
index 9d6e0b6..3924524 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsll(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ieqsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -64,7 +64,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsll_z(i64 %a) {
+define dso_local signext i32 @test_ieqsll_z(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -88,7 +88,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqsll_sext_z(i64 %a) {
+define dso_local signext i32 @test_ieqsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -112,7 +112,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsll_store(i64 %a, i64 %b) {
+define dso_local void @test_ieqsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -123,12 +123,11 @@ define void @test_ieqsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsll_store:
@@ -147,7 +146,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_ieqsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -158,12 +157,11 @@ define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsll_sext_store:
@@ -182,7 +180,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsll_z_store(i64 %a) {
+define dso_local void @test_ieqsll_z_store(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -192,11 +190,10 @@ define void @test_ieqsll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsll_z_store:
@@ -214,7 +211,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqsll_sext_z_store(i64 %a) {
+define dso_local void @test_ieqsll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -224,11 +221,10 @@ define void @test_ieqsll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqsll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
index 9acfcc4..265138b 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -67,7 +67,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqss_z(i16 signext %a) {
+define dso_local signext i32 @test_ieqss_z(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -91,7 +91,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ieqss_sext_z(i16 signext %a) {
+define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_ieqss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqss_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqss_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqss_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqss_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqss_z_store(i16 signext %a) {
+define dso_local void @test_ieqss_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_ieqss_z_store(i16 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqss_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqss_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ieqss_sext_z_store(i16 signext %a) {
+define dso_local void @test_ieqss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_ieqss_sext_z_store(i16 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ieqss_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqss_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll
index 7f938df..d06a990 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -67,7 +67,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequc_z(i8 zeroext %a) {
+define dso_local signext i32 @test_iequc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -91,7 +91,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
+define dso_local signext i32 @test_iequc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequc_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequc_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequc_z_store(i8 zeroext %a) {
+define dso_local void @test_iequc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_iequc_z_store(i8 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequc_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequc_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequc_sext_z_store(i8 zeroext %a) {
+define dso_local void @test_iequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_iequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequc_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequc_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll
index b40e3af..19e76ec 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -67,7 +67,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequi_z(i32 zeroext %a) {
+define dso_local signext i32 @test_iequi_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -91,7 +91,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
+define dso_local signext i32 @test_iequi_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequi_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequi_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequi_z_store(i32 zeroext %a) {
+define dso_local void @test_iequi_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_iequi_z_store(i32 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequi_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequi_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequi_sext_z_store(i32 zeroext %a) {
+define dso_local void @test_iequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_iequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequi_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequi_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll
index 6ef9db9..4caac97 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequll(i64 %a, i64 %b) {
+define dso_local signext i32 @test_iequll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_iequll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -64,7 +64,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequll_z(i64 %a) {
+define dso_local signext i32 @test_iequll_z(i64 %a) {
 ; CHECK-LABEL: test_iequll_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -88,7 +88,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequll_sext_z(i64 %a) {
+define dso_local signext i32 @test_iequll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_iequll_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -112,7 +112,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequll_store(i64 %a, i64 %b) {
+define dso_local void @test_iequll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -123,12 +123,11 @@ define void @test_iequll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequll_store:
@@ -147,7 +146,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_iequll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -158,12 +157,11 @@ define void @test_iequll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequll_sext_store:
@@ -182,7 +180,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequll_z_store(i64 %a) {
+define dso_local void @test_iequll_z_store(i64 %a) {
 ; CHECK-LABEL: test_iequll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -192,11 +190,10 @@ define void @test_iequll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequll_z_store:
@@ -214,7 +211,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequll_sext_z_store(i64 %a) {
+define dso_local void @test_iequll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_iequll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -224,11 +221,10 @@ define void @test_iequll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
index 90bcee8..e3e3a37 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
@@ -7,10 +7,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -67,7 +67,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequs_z(i16 zeroext %a) {
+define dso_local signext i32 @test_iequs_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -91,7 +91,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
+define dso_local signext i32 @test_iequs_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequs_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequs_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequs_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequs_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequs_z_store(i16 zeroext %a) {
+define dso_local void @test_iequs_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_iequs_z_store(i16 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequs_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequs_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iequs_sext_z_store(i16 zeroext %a) {
+define dso_local void @test_iequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_iequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iequs_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequs_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll
index d9a397c..8cf820d 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
-define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -33,7 +33,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -59,7 +59,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_igesc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_igesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -70,12 +70,11 @@ define void @test_igesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesc_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -104,12 +103,11 @@ define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesc_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll
index bff6cb2..b145450 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
-define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -33,7 +33,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -59,7 +59,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_igesi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_igesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -70,12 +70,11 @@ define void @test_igesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesi_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -104,12 +103,11 @@ define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesi_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
index a8c5b8e..59f0ef5 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
-define signext i32 @test_igesll(i64 %a, i64 %b) {
+define dso_local signext i32 @test_igesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
@@ -36,7 +36,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_igesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
@@ -68,7 +68,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_igesll_z(i64 %a) {
+define dso_local signext i32 @test_igesll_z(i64 %a) {
 ; CHECK-LABEL: test_igesll_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    not r3, r3
@@ -91,7 +91,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_igesll_sext_z(i64 %a) {
+define dso_local signext i32 @test_igesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_igesll_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r3, r3, 63
@@ -114,7 +114,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_igesll_store(i64 %a, i64 %b) {
+define dso_local void @test_igesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r3, 63
@@ -126,13 +126,12 @@ define void @test_igesll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
-; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
-; CHECK-BE-NEXT:    std r3, 0(r5)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesll_store:
@@ -151,7 +150,7 @@ entry:
   ret void
 }
 
-define void @test_igesll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_igesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r3, 63
@@ -165,13 +164,12 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: test_igesll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesll_sext_store:
@@ -191,7 +189,7 @@ entry:
   ret void
 }
 
-define void @test_igesll_z_store(i64 %a) {
+define dso_local void @test_igesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_igesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    not r3, r3
@@ -201,11 +199,10 @@ define void @test_igesll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    not r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesll_z_store:
@@ -222,7 +219,7 @@ entry:
   ret void
 }
 
-define void @test_igesll_sext_z_store(i64 %a) {
+define dso_local void @test_igesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_igesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    not r3, r3
@@ -232,11 +229,10 @@ define void @test_igesll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igesll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    not r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    sradi r3, r3, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigess.ll b/llvm/test/CodeGen/PowerPC/testComparesigess.ll
index c0e1ab8..17aeffc 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigess.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigess.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_igess(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -33,7 +33,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -59,7 +59,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_igess_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_igess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -70,12 +70,11 @@ define void @test_igess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igess_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igess_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -104,12 +103,11 @@ define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_igess_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igess_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
index 3b9314b..2f6cae6 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igeuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igeuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -40,7 +40,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeuc_z(i8 zeroext %a) {
+define dso_local signext i32 @test_igeuc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_igeuc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 1
@@ -52,7 +52,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
+define dso_local signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_igeuc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, -1
@@ -64,25 +64,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_igeuc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeuc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igeuc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -92,25 +82,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_igeuc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeuc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igeuc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -125,21 +105,13 @@ entry:
 }
 
 ; Function Attrs : norecurse nounwind
-define void @test_igeuc_z_store(i8 zeroext %a) {
-; BE-LABEL: test_igeuc_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stb r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeuc_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    stb r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igeuc_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    stb r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv3 = zext i1 %cmp to i8
@@ -148,21 +120,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeuc_sext_z_store(i8 zeroext %a) {
-; BE-LABEL: test_igeuc_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stb r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeuc_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    stb r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igeuc_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    stb r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv3 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
index 13d99c4..0b768d9 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igeui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igeui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeui_z(i32 zeroext %a) {
+define dso_local signext i32 @test_igeui_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_igeui_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 1
@@ -51,7 +51,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
+define dso_local signext i32 @test_igeui_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_igeui_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, -1
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_igeui_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeui_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igeui_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -91,25 +81,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_igeui_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeui_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igeui_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -118,21 +98,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeui_z_store(i32 zeroext %a) {
-; BE-LABEL: test_igeui_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stw r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeui_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    stw r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igeui_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    stw r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %conv1 = zext i1 %cmp to i32
@@ -141,21 +113,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeui_sext_z_store(i32 zeroext %a) {
-; BE-LABEL: test_igeui_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stw r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeui_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    stw r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igeui_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    stw r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %conv1 = sext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeull.ll b/llvm/test/CodeGen/PowerPC/testComparesigeull.ll
index a2af8d9..490435e 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeull.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeull(i64 %a, i64 %b) {
+define dso_local signext i32 @test_igeull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igeull:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subc r3, r3, r4
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_igeull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igeull_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subc r3, r3, r4
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeull_z(i64 %a) {
+define dso_local signext i32 @test_igeull_z(i64 %a) {
 ; CHECK-LABEL: test_igeull_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 1
@@ -51,7 +51,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeull_sext_z(i64 %a) {
+define dso_local signext i32 @test_igeull_sext_z(i64 %a) {
 ; CHECK-LABEL: test_igeull_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, -1
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeull_store(i64 %a, i64 %b) {
-; BE-LABEL: test_igeull_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    ld r3, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r4, r4, r4
-; BE-NEXT:    addi r4, r4, 1
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeull_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r4, r4
-; LE-NEXT:    addi r3, r3, 1
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igeull_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -90,25 +80,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeull_sext_store(i64 %a, i64 %b) {
-; BE-LABEL: test_igeull_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    ld r3, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r4, r4, r4
-; BE-NEXT:    not r4, r4
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeull_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r4, r4
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igeull_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -117,21 +97,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeull_z_store(i64 %a) {
-; BE-LABEL: test_igeull_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeull_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    std r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeull_z_store(i64 %a) {
+; CHECK-LABEL: test_igeull_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    std r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = zext i1 %cmp to i64
@@ -140,21 +112,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeull_sext_z_store(i64 %a) {
-; BE-LABEL: test_igeull_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeull_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    std r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_igeull_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    std r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
index 3e5063d..154912d 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igeus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igeus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeus_z(i16 zeroext %a) {
+define dso_local signext i32 @test_igeus_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_igeus_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 1
@@ -51,7 +51,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
+define dso_local signext i32 @test_igeus_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_igeus_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 1
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_igeus_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeus_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igeus_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -91,25 +81,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_igeus_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeus_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igeus_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -118,21 +98,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeus_z_store(i16 zeroext %a) {
-; BE-LABEL: test_igeus_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    sth r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeus_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    sth r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igeus_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    sth r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv3 = zext i1 %cmp to i16
@@ -141,21 +113,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_igeus_sext_z_store(i16 zeroext %a) {
-; BE-LABEL: test_igeus_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    sth r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_igeus_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    sth r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_igeus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igeus_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    sth r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv3 = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll
index bd5a16f..55b11c7 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
-define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -33,7 +33,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -59,7 +59,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_ilesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -70,12 +70,11 @@ define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesc_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -104,12 +103,11 @@ define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesc_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll
index 8717e23..9d23b97 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
-define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -33,7 +33,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -59,7 +59,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_ilesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -70,12 +70,11 @@ define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesi_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -104,12 +103,11 @@ define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesi_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
index 9f4e92c..b9ac9c0 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
-define signext i32 @test_ilesll(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ilesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
@@ -36,7 +36,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
@@ -68,7 +68,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_ilesll_z(i64 %a) {
+define dso_local signext i32 @test_ilesll_z(i64 %a) {
 ; CHECK-LABEL: test_ilesll_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
@@ -94,7 +94,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ilesll_sext_z(i64 %a) {
+define dso_local signext i32 @test_ilesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ilesll_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
@@ -120,7 +120,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ilesll_store(i64 %a, i64 %b) {
+define dso_local void @test_ilesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
@@ -132,13 +132,12 @@ define void @test_ilesll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
-; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
-; CHECK-BE-NEXT:    std r3, 0(r5)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesll_store:
@@ -157,7 +156,7 @@ entry:
   ret void
 }
 
-define void @test_ilesll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_ilesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
@@ -171,13 +170,12 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: test_ilesll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesll_sext_store:
@@ -197,7 +195,7 @@ entry:
   ret void
 }
 
-define void @test_ilesll_z_store(i64 %a) {
+define dso_local void @test_ilesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_ilesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r5, r3, -1
@@ -208,12 +206,11 @@ define void @test_ilesll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addi r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    or r3, r5, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesll_z_store:
@@ -231,7 +228,7 @@ entry:
   ret void
 }
 
-define void @test_ilesll_sext_z_store(i64 %a) {
+define dso_local void @test_ilesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_ilesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r5, r3, -1
@@ -242,12 +239,11 @@ define void @test_ilesll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ilesll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addi r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    or r3, r5, r3
 ; CHECK-BE-NEXT:    sradi r3, r3, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiless.ll b/llvm/test/CodeGen/PowerPC/testComparesiless.ll
index b9b0294..28c8e98 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiless.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiless.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_iless(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -33,7 +33,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -59,7 +59,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_iless_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_iless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -70,12 +70,11 @@ define void @test_iless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iless_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iless_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -104,12 +103,11 @@ define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iless_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iless_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
index 4461fb6..0817d78 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ileuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ileuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileuc_z(i8 zeroext %a) {
+define dso_local signext i32 @test_ileuc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_ileuc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -52,7 +52,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
+define dso_local signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_ileuc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -66,25 +66,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_ileuc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileuc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ileuc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -93,25 +83,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_ileuc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileuc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ileuc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -120,23 +100,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileuc_z_store(i8 zeroext %a) {
-; BE-LABEL: test_ileuc_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileuc_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    stb r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_ileuc_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = zext i1 %cmp to i8
@@ -145,25 +116,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileuc_sext_z_store(i8 zeroext %a) {
-; BE-LABEL: test_ileuc_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileuc_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    stb r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_ileuc_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesileui.ll b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
index ad6418c..7f0bfbd 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesileui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ileui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ileui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileui_z(i32 zeroext %a) {
+define dso_local signext i32 @test_ileui_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_ileui_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -52,7 +52,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
+define dso_local signext i32 @test_ileui_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_ileui_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -66,25 +66,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_ileui_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileui_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ileui_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = zext i1 %cmp to i32
@@ -93,25 +83,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_ileui_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileui_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ileui_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -120,23 +100,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileui_z_store(i32 zeroext %a) {
-; BE-LABEL: test_ileui_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileui_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    stw r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_ileui_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stw r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = zext i1 %cmp to i32
@@ -145,25 +116,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileui_sext_z_store(i32 zeroext %a) {
-; BE-LABEL: test_ileui_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileui_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    stw r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_ileui_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stw r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/PowerPC/testComparesileull.ll b/llvm/test/CodeGen/PowerPC/testComparesileull.ll
index 28d828f..84ef010 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesileull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileull.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileull(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ileull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ileull:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subc r4, r4, r3
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ileull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ileull_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subc r4, r4, r3
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileull_z(i64 %a) {
+define dso_local signext i32 @test_ileull_z(i64 %a) {
 ; CHECK-LABEL: test_ileull_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -52,7 +52,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileull_sext_z(i64 %a) {
+define dso_local signext i32 @test_ileull_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ileull_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -65,25 +65,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileull_store(i64 %a, i64 %b) {
-; BE-LABEL: test_ileull_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r4, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r3, r3, r3
-; BE-NEXT:    addi r3, r3, 1
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileull_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r4, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r3, r3
-; LE-NEXT:    addi r3, r3, 1
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ileull_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r4, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -92,25 +82,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileull_sext_store(i64 %a, i64 %b) {
-; BE-LABEL: test_ileull_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r4, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r3, r3, r3
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileull_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r4, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r3, r3
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ileull_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r4, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -119,23 +99,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileull_z_store(i64 %a) {
-; BE-LABEL: test_ileull_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzd r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    rldicl r3, r3, 58, 63
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileull_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzd r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 58, 63
-; LE-NEXT:    std r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileull_z_store(i64 %a) {
+; CHECK-LABEL: test_ileull_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = zext i1 %cmp to i64
@@ -144,23 +115,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileull_sext_z_store(i64 %a) {
-; BE-LABEL: test_ileull_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    addic r3, r3, -1
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    subfe r3, r3, r3
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileull_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addic r3, r3, -1
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ileull_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesileus.ll b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
index e4b68bb..d353ab3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesileus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ileus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -25,7 +25,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ileus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -39,7 +39,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileus_z(i16 zeroext %a) {
+define dso_local signext i32 @test_ileus_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_ileus_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -52,7 +52,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
+define dso_local signext i32 @test_ileus_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_ileus_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -66,25 +66,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_ileus_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileus_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ileus_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -93,25 +83,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_ileus_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileus_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ileus_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -120,23 +100,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileus_z_store(i16 zeroext %a) {
-; BE-LABEL: test_ileus_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileus_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    sth r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_ileus_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = zext i1 %cmp to i16
@@ -145,25 +116,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_ileus_sext_z_store(i16 zeroext %a) {
-; BE-LABEL: test_ileus_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_ileus_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    sth r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_ileus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_ileus_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
index b1a1b96..8e8fa13 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
@@ -8,10 +8,10 @@
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -24,7 +24,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsc_sext_z(i8 signext %a) {
+define dso_local signext i32 @test_iltsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_iltsc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    srawi r3, r3, 31
@@ -49,23 +49,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
-; BE-LABEL: test_iltsc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -74,23 +65,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
-; BE-LABEL: test_iltsc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    stb r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -99,21 +81,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsc_sext_z_store(i8 signext %a) {
-; BE-LABEL: test_iltsc_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    srwi r3, r3, 7
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsc_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 7
-; LE-NEXT:    stb r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_iltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 7
+; CHECK-NEXT:    stb r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, 0
   %conv2 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
index 252e9c3..d9a98c4 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -24,7 +24,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsi_sext_z(i32 signext %a) {
+define dso_local signext i32 @test_iltsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_iltsi_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    srawi r3, r3, 31
@@ -49,23 +49,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
-; BE-LABEL: test_iltsi_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stw r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsi_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -74,23 +65,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
-; BE-LABEL: test_iltsi_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    stw r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsi_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -99,21 +81,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsi_sext_z_store(i32 signext %a) {
-; BE-LABEL: test_iltsi_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    srawi r3, r3, 31
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsi_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srawi r3, r3, 31
-; LE-NEXT:    stw r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_iltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    stw r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, 0
   %sub = sext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
index 740eb33..3c06b7c 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsll(i64 %a, i64 %b) {
+define dso_local signext i32 @test_iltsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
@@ -27,7 +27,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
@@ -44,7 +44,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltsll_sext_z(i64 %a) {
+define dso_local signext i32 @test_iltsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_iltsll_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r3, r3, 63
@@ -56,29 +56,17 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsll_store(i64 %a, i64 %b) {
-; BE-LABEL: test_iltsll_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    sradi r6, r3, 63
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    adde r3, r3, r6
-; BE-NEXT:    xori r3, r3, 1
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsll_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sradi r6, r3, 63
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
-; LE-NEXT:    adde r3, r3, r6
-; LE-NEXT:    xori r3, r3, 1
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltsll_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -88,31 +76,18 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsll_sext_store(i64 %a, i64 %b) {
-; BE-LABEL: test_iltsll_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    sradi r6, r3, 63
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    adde r3, r3, r6
-; BE-NEXT:    xori r3, r3, 1
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsll_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sradi r6, r3, 63
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
-; LE-NEXT:    adde r3, r3, r6
-; LE-NEXT:    xori r3, r3, 1
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltsll_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -122,21 +97,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltsll_sext_z_store(i64 %a) {
-; BE-LABEL: test_iltsll_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltsll_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    std r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_iltsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_iltsll_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 0
   %conv2 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltss.ll b/llvm/test/CodeGen/PowerPC/testComparesiltss.ll
index f6a9125..e7230c6 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltss.ll
@@ -8,10 +8,10 @@
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -24,7 +24,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -37,7 +37,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltss_sext_z(i16 signext %a) {
+define dso_local signext i32 @test_iltss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_iltss_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    srawi r3, r3, 31
@@ -49,23 +49,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltss_store(i16 signext %a, i16 signext %b) {
-; BE-LABEL: test_iltss_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltss_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -74,23 +65,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
-; BE-LABEL: test_iltss_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    sth r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltss_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -99,21 +81,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltss_sext_z_store(i16 signext %a) {
-; BE-LABEL: test_iltss_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    srwi r3, r3, 15
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltss_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 15
-; LE-NEXT:    sth r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_iltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 15
+; CHECK-NEXT:    sth r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, 0
   %sub = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll b/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
index de2dc1c..d191afb 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iltuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -24,7 +24,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iltuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -37,23 +37,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_iltuc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltuc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -62,23 +53,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_iltuc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    stb r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltuc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltui.ll b/llvm/test/CodeGen/PowerPC/testComparesiltui.ll
index a0d40b6..165d114 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltui.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iltui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -24,7 +24,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iltui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -37,23 +37,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_iltui_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stw r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltui_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -62,23 +53,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_iltui_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    stw r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltui_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
   %sub = sext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltus.ll b/llvm/test/CodeGen/PowerPC/testComparesiltus.ll
index 98b8f35..3d82cb3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltus.ll
@@ -8,10 +8,10 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iltus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -24,7 +24,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iltus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -37,23 +37,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_iltus_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltus_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -62,23 +53,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_iltus_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    sth r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_iltus_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesc.ll b/llvm/test/CodeGen/PowerPC/testComparesinesc.ll
index 8c81ead..7006838 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesinesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesinesc.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
-define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_inesc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
+define dso_local signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_inesc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -69,7 +69,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_inesc_z(i8 signext %a) {
+define dso_local signext i32 @test_inesc_z(i8 signext %a) {
 ; CHECK-LABEL: test_inesc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -95,7 +95,7 @@ entry:
   ret i32 %conv1
 }
 
-define signext i32 @test_inesc_sext_z(i8 signext %a) {
+define dso_local signext i32 @test_inesc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_inesc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -124,7 +124,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_inesc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_inesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_inesc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -136,13 +136,12 @@ define void @test_inesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesc_store:
@@ -161,7 +160,7 @@ entry:
   ret void
 }
 
-define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_inesc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -175,13 +174,12 @@ define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-BE-LABEL: test_inesc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesc_sext_store:
@@ -201,7 +199,7 @@ entry:
   ret void
 }
 
-define void @test_inesc_z_store(i8 signext %a) {
+define dso_local void @test_inesc_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_inesc_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -212,12 +210,11 @@ define void @test_inesc_z_store(i8 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesc_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesc_z_store:
@@ -235,7 +232,7 @@ entry:
   ret void
 }
 
-define void @test_inesc_sext_z_store(i8 signext %a) {
+define dso_local void @test_inesc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_inesc_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -247,13 +244,12 @@ define void @test_inesc_sext_z_store(i8 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesc_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesc_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesi.ll b/llvm/test/CodeGen/PowerPC/testComparesinesi.ll
index ae8d981..67d1bed 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesinesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesinesi.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
-define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_inesi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
+define dso_local signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_inesi_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -69,7 +69,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_inesi_z(i32 signext %a) {
+define dso_local signext i32 @test_inesi_z(i32 signext %a) {
 ; CHECK-LABEL: test_inesi_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -95,7 +95,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_inesi_sext_z(i32 signext %a) {
+define dso_local signext i32 @test_inesi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_inesi_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -124,7 +124,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_inesi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_inesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_inesi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -136,13 +136,12 @@ define void @test_inesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesi_store:
@@ -161,7 +160,7 @@ entry:
   ret void
 }
 
-define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_inesi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -175,13 +174,12 @@ define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-BE-LABEL: test_inesi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesi_sext_store:
@@ -201,7 +199,7 @@ entry:
   ret void
 }
 
-define void @test_inesi_z_store(i32 signext %a) {
+define dso_local void @test_inesi_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_inesi_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -212,12 +210,11 @@ define void @test_inesi_z_store(i32 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesi_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesi_z_store:
@@ -235,7 +232,7 @@ entry:
   ret void
 }
 
-define void @test_inesi_sext_z_store(i32 signext %a) {
+define dso_local void @test_inesi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_inesi_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -247,13 +244,12 @@ define void @test_inesi_sext_z_store(i32 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesi_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesi_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesll.ll b/llvm/test/CodeGen/PowerPC/testComparesinesll.ll
index c360fb9..e50a182 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesinesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesinesll.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
-define signext i32 @test_inesll(i64 %a, i64 %b) {
+define dso_local signext i32 @test_inesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -34,7 +34,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_inesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -60,7 +60,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_inesll_z(i64 %a) {
+define dso_local signext i32 @test_inesll_z(i64 %a) {
 ; CHECK-LABEL: test_inesll_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r4, r3, -1
@@ -83,7 +83,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_inesll_sext_z(i64 %a) {
+define dso_local signext i32 @test_inesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_inesll_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
@@ -106,7 +106,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_inesll_store(i64 %a, i64 %b) {
+define dso_local void @test_inesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -117,12 +117,11 @@ define void @test_inesll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-BE-NEXT:    addic r4, r3, -1
+; CHECK-BE-NEXT:    subfe r3, r4, r3
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesll_store:
@@ -140,7 +139,7 @@ entry:
   ret void
 }
 
-define void @test_inesll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_inesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -151,12 +150,11 @@ define void @test_inesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesll_sext_store:
@@ -174,7 +172,7 @@ entry:
   ret void
 }
 
-define void @test_inesll_z_store(i64 %a) {
+define dso_local void @test_inesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_inesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r5, r3, -1
@@ -184,11 +182,10 @@ define void @test_inesll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesll_z_store:
@@ -205,7 +202,7 @@ entry:
   ret void
 }
 
-define void @test_inesll_sext_z_store(i64 %a) {
+define dso_local void @test_inesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_inesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
@@ -215,11 +212,10 @@ define void @test_inesll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_inesll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_inesll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiness.ll b/llvm/test/CodeGen/PowerPC/testComparesiness.ll
index cdfeaa9..662599f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiness.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiness.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_iness(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iness:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
+define dso_local signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iness_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -69,7 +69,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_iness_z(i16 signext %a) {
+define dso_local signext i32 @test_iness_z(i16 signext %a) {
 ; CHECK-LABEL: test_iness_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -95,7 +95,7 @@ entry:
   ret i32 %conv1
 }
 
-define signext i32 @test_iness_sext_z(i16 signext %a) {
+define dso_local signext i32 @test_iness_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_iness_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -124,7 +124,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_iness_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_iness_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iness_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -136,13 +136,12 @@ define void @test_iness_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iness_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iness_store:
@@ -161,7 +160,7 @@ entry:
   ret void
 }
 
-define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iness_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -175,13 +174,12 @@ define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-BE-LABEL: test_iness_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iness_sext_store:
@@ -201,7 +199,7 @@ entry:
   ret void
 }
 
-define void @test_iness_z_store(i16 signext %a) {
+define dso_local void @test_iness_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_iness_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -212,12 +210,11 @@ define void @test_iness_z_store(i16 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iness_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iness_z_store:
@@ -235,7 +232,7 @@ entry:
   ret void
 }
 
-define void @test_iness_sext_z_store(i16 signext %a) {
+define dso_local void @test_iness_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_iness_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -247,13 +244,12 @@ define void @test_iness_sext_z_store(i16 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_iness_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iness_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesineuc.ll b/llvm/test/CodeGen/PowerPC/testComparesineuc.ll
index e63ea46..a78d26a 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesineuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesineuc.ll
@@ -5,9 +5,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
-define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -36,7 +36,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
+define dso_local signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -68,7 +68,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_ineuc_z(i8 zeroext %a) {
+define dso_local signext i32 @test_ineuc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -94,7 +94,7 @@ entry:
   ret i32 %conv1
 }
 
-define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
+define dso_local signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -123,7 +123,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -135,13 +135,12 @@ define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineuc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineuc_store:
@@ -160,7 +159,7 @@ entry:
   ret void
 }
 
-define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -174,13 +173,12 @@ define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-BE-LABEL: test_ineuc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineuc_sext_store:
@@ -200,7 +198,7 @@ entry:
   ret void
 }
 
-define void @test_ineuc_z_store(i8 zeroext %a) {
+define dso_local void @test_ineuc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -211,12 +209,11 @@ define void @test_ineuc_z_store(i8 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineuc_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineuc_z_store:
@@ -234,7 +231,7 @@ entry:
   ret void
 }
 
-define void @test_ineuc_sext_z_store(i8 zeroext %a) {
+define dso_local void @test_ineuc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -246,13 +243,12 @@ define void @test_ineuc_sext_z_store(i8 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineuc_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineuc_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesineui.ll b/llvm/test/CodeGen/PowerPC/testComparesineui.ll
index 86e6fb9..910eab0 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesineui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesineui.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
-define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ineui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
+define dso_local signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ineui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -69,7 +69,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_ineui_z(i32 zeroext %a) {
+define dso_local signext i32 @test_ineui_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_ineui_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -95,7 +95,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
+define dso_local signext i32 @test_ineui_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_ineui_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -124,7 +124,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ineui_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -136,13 +136,12 @@ define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineui_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineui_store:
@@ -161,7 +160,7 @@ entry:
   ret void
 }
 
-define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ineui_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -175,13 +174,12 @@ define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-BE-LABEL: test_ineui_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineui_sext_store:
@@ -201,7 +199,7 @@ entry:
   ret void
 }
 
-define void @test_ineui_z_store(i32 zeroext %a) {
+define dso_local void @test_ineui_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_ineui_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -212,12 +210,11 @@ define void @test_ineui_z_store(i32 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineui_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineui_z_store:
@@ -235,7 +232,7 @@ entry:
   ret void
 }
 
-define void @test_ineui_sext_z_store(i32 zeroext %a) {
+define dso_local void @test_ineui_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_ineui_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -247,13 +244,12 @@ define void @test_ineui_sext_z_store(i32 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineui_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineui_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesineull.ll b/llvm/test/CodeGen/PowerPC/testComparesineull.ll
index c0b04c2..9a9999d 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesineull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesineull.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
-define signext i32 @test_ineull(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ineull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -34,7 +34,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
+define dso_local signext i32 @test_ineull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -60,7 +60,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_ineull_z(i64 %a) {
+define dso_local signext i32 @test_ineull_z(i64 %a) {
 ; CHECK-LABEL: test_ineull_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r4, r3, -1
@@ -83,7 +83,7 @@ entry:
   ret i32 %conv
 }
 
-define signext i32 @test_ineull_sext_z(i64 %a) {
+define dso_local signext i32 @test_ineull_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ineull_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
@@ -106,7 +106,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ineull_store(i64 %a, i64 %b) {
+define dso_local void @test_ineull_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -117,12 +117,11 @@ define void @test_ineull_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineull_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-BE-NEXT:    addic r4, r3, -1
+; CHECK-BE-NEXT:    subfe r3, r4, r3
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineull_store:
@@ -140,7 +139,7 @@ entry:
   ret void
 }
 
-define void @test_ineull_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_ineull_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -151,12 +150,11 @@ define void @test_ineull_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineull_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineull_sext_store:
@@ -174,7 +172,7 @@ entry:
   ret void
 }
 
-define void @test_ineull_z_store(i64 %a) {
+define dso_local void @test_ineull_z_store(i64 %a) {
 ; CHECK-LABEL: test_ineull_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r5, r3, -1
@@ -184,11 +182,10 @@ define void @test_ineull_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineull_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineull_z_store:
@@ -205,7 +202,7 @@ entry:
   ret void
 }
 
-define void @test_ineull_sext_z_store(i64 %a) {
+define dso_local void @test_ineull_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_ineull_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
@@ -215,11 +212,10 @@ define void @test_ineull_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineull_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineull_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesineus.ll b/llvm/test/CodeGen/PowerPC/testComparesineus.ll
index df208ee..3cb8887 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesineus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesineus.ll
@@ -6,9 +6,9 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
-define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -37,7 +37,7 @@ entry:
   ret i32 %conv2
 }
 
-define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
+define dso_local signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -69,7 +69,7 @@ entry:
   ret i32 %sub
 }
 
-define signext i32 @test_ineus_z(i16 zeroext %a) {
+define dso_local signext i32 @test_ineus_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -95,7 +95,7 @@ entry:
   ret i32 %conv1
 }
 
-define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
+define dso_local signext i32 @test_ineus_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_sext_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -124,7 +124,7 @@ entry:
   ret i32 %sub
 }
 
-define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -136,13 +136,12 @@ define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineus_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineus_store:
@@ -161,7 +160,7 @@ entry:
   ret void
 }
 
-define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -175,13 +174,12 @@ define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-BE-LABEL: test_ineus_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineus_sext_store:
@@ -201,7 +199,7 @@ entry:
   ret void
 }
 
-define void @test_ineus_z_store(i16 zeroext %a) {
+define dso_local void @test_ineus_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -212,12 +210,11 @@ define void @test_ineus_z_store(i16 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineus_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineus_z_store:
@@ -235,7 +232,7 @@ entry:
   ret void
 }
 
-define void @test_ineus_sext_z_store(i16 zeroext %a) {
+define dso_local void @test_ineus_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -247,13 +244,12 @@ define void @test_ineus_sext_z_store(i16 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_ineus_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ineus_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
index 7759f0a..57f9985 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -7,7 +7,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
@@ -118,7 +118,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -129,12 +129,11 @@ define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsc_store:
@@ -153,7 +152,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -165,13 +164,12 @@ define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsc_sext_store:
@@ -191,7 +189,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsc_z_store(i8 signext %a) {
+define dso_local void @test_lleqsc_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -201,11 +199,10 @@ define void @test_lleqsc_z_store(i8 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsc_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsc_z_store:
@@ -223,7 +220,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsc_sext_z_store(i8 signext %a) {
+define dso_local void @test_lleqsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -234,12 +231,11 @@ define void @test_lleqsc_sext_z_store(i8 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsc_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsc_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll
index 4785373..dc0c8d4 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
@@ -117,7 +117,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -128,12 +128,11 @@ define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsi_store:
@@ -152,7 +151,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -164,13 +163,12 @@ define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsi_sext_store:
@@ -190,7 +188,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsi_z_store(i32 signext %a) {
+define dso_local void @test_lleqsi_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -200,11 +198,10 @@ define void @test_lleqsi_z_store(i32 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsi_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsi_z_store:
@@ -222,7 +219,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsi_sext_z_store(i32 signext %a) {
+define dso_local void @test_lleqsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -233,12 +230,11 @@ define void @test_lleqsi_sext_z_store(i32 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsi_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsi_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll
index 18b8d0b..4e01dc7 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsll(i64 %a, i64 %b) {
@@ -111,7 +111,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsll_store(i64 %a, i64 %b) {
+define dso_local void @test_lleqsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lleqsll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -122,12 +122,11 @@ define void @test_lleqsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsll_store:
@@ -146,7 +145,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_lleqsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lleqsll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -157,12 +156,11 @@ define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsll_sext_store:
@@ -181,7 +179,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsll_z_store(i64 %a) {
+define dso_local void @test_lleqsll_z_store(i64 %a) {
 ; CHECK-LABEL: test_lleqsll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -191,11 +189,10 @@ define void @test_lleqsll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsll_z_store:
@@ -213,7 +210,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqsll_sext_z_store(i64 %a) {
+define dso_local void @test_lleqsll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_lleqsll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -223,11 +220,10 @@ define void @test_lleqsll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqsll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
index 13e0759..992b79f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
@@ -117,7 +117,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_lleqss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -128,12 +128,11 @@ define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqss_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqss_store:
@@ -152,7 +151,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -164,13 +163,12 @@ define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqss_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqss_sext_store:
@@ -190,7 +188,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqss_z_store(i16 signext %a) {
+define dso_local void @test_lleqss_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -200,11 +198,10 @@ define void @test_lleqss_z_store(i16 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqss_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqss_z_store:
@@ -222,7 +219,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lleqss_sext_z_store(i16 signext %a) {
+define dso_local void @test_lleqss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -233,12 +230,11 @@ define void @test_lleqss_sext_z_store(i16 signext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lleqss_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqss_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll
index 4c3c1d6..acd865c 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
@@ -117,7 +117,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -128,12 +128,11 @@ define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequc_store:
@@ -152,7 +151,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+define dso_local void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -164,13 +163,12 @@ define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequc_sext_store:
@@ -190,7 +188,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequc_z_store(i8 zeroext %a) {
+define dso_local void @test_llequc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -200,11 +198,10 @@ define void @test_llequc_z_store(i8 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequc_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequc_z_store:
@@ -222,7 +219,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequc_sext_z_store(i8 zeroext %a) {
+define dso_local void @test_llequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -233,12 +230,11 @@ define void @test_llequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequc_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequc_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll
index 16741ea..37715dd 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
@@ -117,7 +117,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -128,12 +128,11 @@ define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequi_store:
@@ -152,7 +151,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
+define dso_local void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -164,13 +163,12 @@ define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequi_sext_store:
@@ -190,7 +188,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequi_z_store(i32 zeroext %a) {
+define dso_local void @test_llequi_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -200,11 +198,10 @@ define void @test_llequi_z_store(i32 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequi_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequi_z_store:
@@ -222,7 +219,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequi_sext_z_store(i32 zeroext %a) {
+define dso_local void @test_llequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -233,12 +230,11 @@ define void @test_llequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequi_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequi_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll
index 16bd2d1..a396d9c 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequll(i64 %a, i64 %b) {
@@ -111,7 +111,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequll_store(i64 %a, i64 %b) {
+define dso_local void @test_llequll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llequll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -122,12 +122,11 @@ define void @test_llequll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequll_store:
@@ -146,7 +145,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_llequll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llequll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -157,12 +156,11 @@ define void @test_llequll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequll_sext_store:
@@ -181,7 +179,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequll_z_store(i64 %a) {
+define dso_local void @test_llequll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llequll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
@@ -191,11 +189,10 @@ define void @test_llequll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequll_z_store:
@@ -213,7 +210,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequll_sext_z_store(i64 %a) {
+define dso_local void @test_llequll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llequll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
@@ -223,11 +220,10 @@ define void @test_llequll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r3, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll
index 4470b4f..224238b 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
@@ -117,7 +117,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -128,12 +128,11 @@ define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequs_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequs_store:
@@ -152,7 +151,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
+define dso_local void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -164,13 +163,12 @@ define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequs_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequs_sext_store:
@@ -190,7 +188,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequs_z_store(i16 zeroext %a) {
+define dso_local void @test_llequs_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -200,11 +198,10 @@ define void @test_llequs_z_store(i16 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequs_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequs_z_store:
@@ -222,7 +219,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llequs_sext_z_store(i16 zeroext %a) {
+define dso_local void @test_llequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -233,12 +230,11 @@ define void @test_llequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llequs_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzw r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequs_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll
index f7c7985..5a0152d 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc:
@@ -59,7 +59,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_llgesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -70,12 +70,11 @@ define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesc_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -104,12 +103,11 @@ define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesc_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
index 046c037..8e5f1bf 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi:
@@ -59,7 +59,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_llgesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -70,12 +70,11 @@ define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesi_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -104,12 +103,11 @@ define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesi_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
index 4b34429..ceba16f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 define i64 @test_llgesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll:
@@ -114,7 +114,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @test_llgesll_store(i64 %a, i64 %b) {
+define dso_local void @test_llgesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r3, 63
@@ -126,13 +126,12 @@ define void @test_llgesll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
-; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
-; CHECK-BE-NEXT:    std r3, 0(r5)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesll_store:
@@ -151,7 +150,7 @@ entry:
   ret void
 }
 
-define void @test_llgesll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_llgesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r3, 63
@@ -165,13 +164,12 @@ define void @test_llgesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: test_llgesll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesll_sext_store:
@@ -191,7 +189,7 @@ entry:
   ret void
 }
 
-define void @test_llgesll_z_store(i64 %a) {
+define dso_local void @test_llgesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    not r3, r3
@@ -201,11 +199,10 @@ define void @test_llgesll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    not r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesll_z_store:
@@ -222,7 +219,7 @@ entry:
   ret void
 }
 
-define void @test_llgesll_sext_z_store(i64 %a) {
+define dso_local void @test_llgesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    not r3, r3
@@ -232,11 +229,10 @@ define void @test_llgesll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgesll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    not r3, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    sradi r3, r3, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll
index 50583cd..bdf0fc4 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 define i64 @test_llgess(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess:
@@ -59,7 +59,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @test_llgess_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_llgess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -70,12 +70,11 @@ define void @test_llgess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgess_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgess_store:
@@ -93,7 +92,7 @@ entry:
   ret void
 }
 
-define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
@@ -104,12 +103,11 @@ define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llgess_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgess_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
index 85a9df5..c640d30 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_llgeuc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeuc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgeuc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -91,25 +81,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_llgeuc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeuc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgeuc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -118,21 +98,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeuc_z_store(i8 zeroext %a) {
-; BE-LABEL: test_llgeuc_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stb r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeuc_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    stb r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgeuc_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    stb r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv1 = zext i1 %cmp to i8
@@ -141,21 +113,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeuc_sext_z_store(i8 zeroext %a) {
-; BE-LABEL: test_llgeuc_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stb r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeuc_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    stb r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgeuc_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    stb r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv1 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
index 19da9da..a06d514 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_llgeui_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeui_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgeui_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -91,25 +81,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_llgeui_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeui_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgeui_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -118,21 +98,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeui_z_store(i32 zeroext %a) {
-; BE-LABEL: test_llgeui_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stw r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeui_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    stw r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgeui_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    stw r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %sub = zext i1 %cmp to i32
@@ -141,21 +113,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeui_sext_z_store(i32 zeroext %a) {
-; BE-LABEL: test_llgeui_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    stw r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeui_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    stw r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgeui_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    stw r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %sub = sext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
index 580bf83..aa6dbdc 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeull(i64 %a, i64 %b) {
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeull_store(i64 %a, i64 %b) {
-; BE-LABEL: test_llgeull_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    ld r3, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r4, r4, r4
-; BE-NEXT:    addi r4, r4, 1
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeull_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r4, r4
-; LE-NEXT:    addi r3, r3, 1
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgeull_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -90,25 +80,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeull_sext_store(i64 %a, i64 %b) {
-; BE-LABEL: test_llgeull_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    ld r3, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r4, r4, r4
-; BE-NEXT:    not r4, r4
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeull_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r4, r4
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgeull_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -117,21 +97,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeull_z_store(i64 %a) {
-; BE-LABEL: test_llgeull_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeull_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    std r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeull_z_store(i64 %a) {
+; CHECK-LABEL: test_llgeull_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    std r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = zext i1 %cmp to i64
@@ -140,21 +112,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeull_sext_z_store(i64 %a) {
-; BE-LABEL: test_llgeull_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    std r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeull_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    std r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llgeull_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    std r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   store i64 -1, i64* @glob
   ret void

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
index 56099c6..e39f809 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
@@ -63,25 +63,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_llgeus_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeus_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgeus_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -91,25 +81,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_llgeus_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeus_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgeus_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -118,21 +98,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeus_z_store(i16 zeroext %a) {
-; BE-LABEL: test_llgeus_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, 1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    sth r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeus_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, 1
-; LE-NEXT:    sth r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgeus_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    sth r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv1 = zext i1 %cmp to i16
@@ -141,21 +113,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llgeus_sext_z_store(i16 zeroext %a) {
-; BE-LABEL: test_llgeus_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; BE-NEXT:    li r4, -1
-; BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; BE-NEXT:    sth r4, 0(r3)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llgeus_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r3, r2, glob@toc@ha
-; LE-NEXT:    li r4, -1
-; LE-NEXT:    sth r4, glob@toc@l(r3)
-; LE-NEXT:    blr
+define dso_local void @test_llgeus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgeus_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, glob@toc@ha
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    sth r4, glob@toc@l(r3)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv1 = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll
index 1ec226a..25910f3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc:
@@ -60,7 +60,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_lllesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -71,12 +71,11 @@ define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesc_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesc_store:
@@ -94,7 +93,7 @@ entry:
   ret void
 }
 
-define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
+define dso_local void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -105,12 +104,11 @@ define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesc_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stb r3, 0(r4)
+; CHECK-BE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesc_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll
index 3ff4907..c8470ce 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 define i64 @test_lllesi(i32 signext %a, i32 signext %b)  {
 ; CHECK-LABEL: test_lllesi:
@@ -60,7 +60,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_lllesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lllesi_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -71,12 +71,11 @@ define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesi_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesi_store:
@@ -94,7 +93,7 @@ entry:
   ret void
 }
 
-define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
+define dso_local void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lllesi_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -105,12 +104,11 @@ define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesi_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    stw r3, 0(r4)
+; CHECK-BE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesi_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
index a323f07..5704651 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lllesll(i64 %a, i64 %b)  {
@@ -125,7 +125,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lllesll_store(i64 %a, i64 %b) {
+define dso_local void @test_lllesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lllesll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
@@ -137,13 +137,12 @@ define void @test_lllesll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
-; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
-; CHECK-BE-NEXT:    std r3, 0(r5)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesll_store:
@@ -163,7 +162,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lllesll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_lllesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lllesll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
@@ -177,13 +176,12 @@ define void @test_lllesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-BE-LABEL: test_lllesll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesll_sext_store:
@@ -204,7 +202,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lllesll_z_store(i64 %a) {
+define dso_local void @test_lllesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_lllesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r5, r3, -1
@@ -215,12 +213,11 @@ define void @test_lllesll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addi r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    or r3, r5, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesll_z_store:
@@ -239,7 +236,7 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_lllesll_sext_z_store(i64 %a) {
+define dso_local void @test_lllesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_lllesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r5, r3, -1
@@ -250,12 +247,11 @@ define void @test_lllesll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_lllesll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addi r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    or r3, r5, r3
 ; CHECK-BE-NEXT:    sradi r3, r3, 63
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllless.ll b/llvm/test/CodeGen/PowerPC/testComparesllless.ll
index c67ef49..ba96393 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllless.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllless.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 define i64 @test_llless(i16 signext %a, i16 signext %b)  {
 ; CHECK-LABEL: test_llless:
@@ -60,7 +60,7 @@ entry:
   ret i64 %conv3
 }
 
-define void @test_llless_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_llless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llless_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -71,12 +71,11 @@ define void @test_llless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llless_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llless_store:
@@ -94,7 +93,7 @@ entry:
   ret void
 }
 
-define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
+define dso_local void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llless_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
@@ -105,12 +104,11 @@ define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llless_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
-; CHECK-BE-NEXT:    sth r3, 0(r4)
+; CHECK-BE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llless_sext_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
index 9f0bf57..d6356bf 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
@@ -66,25 +66,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_llleuc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleuc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llleuc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -93,25 +83,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_llleuc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleuc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llleuc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -120,23 +100,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleuc_z_store(i8 zeroext %a) {
-; BE-LABEL: test_llleuc_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleuc_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    stb r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llleuc_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %conv2 = zext i1 %cmp to i8
@@ -145,25 +116,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleuc_sext_z_store(i8 zeroext %a) {
-; BE-LABEL: test_llleuc_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    stb r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleuc_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    stb r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llleuc_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %conv2 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
index b6c43e4..0df54dd 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i32 0, align 4
+@glob = dso_local local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
@@ -66,25 +66,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_llleui_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleui_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llleui_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -93,25 +83,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; BE-LABEL: test_llleui_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleui_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    stw r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llleui_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -120,23 +100,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleui_z_store(i32 zeroext %a) {
-; BE-LABEL: test_llleui_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleui_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    stw r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llleui_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stw r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, 0
   %conv = zext i1 %cmp to i32
@@ -145,25 +116,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleui_sext_z_store(i32 zeroext %a) {
-; BE-LABEL: test_llleui_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    stw r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleui_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    stw r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llleui_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stw r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, 0
   %sub = sext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleull.ll b/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
index 05df4b3..2e4e6f0 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleull(i64 %a, i64 %b) {
@@ -65,25 +65,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleull_store(i64 %a, i64 %b) {
-; BE-LABEL: test_llleull_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r4, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r3, r3, r3
-; BE-NEXT:    addi r3, r3, 1
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleull_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r4, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r3, r3
-; LE-NEXT:    addi r3, r3, 1
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llleull_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r4, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -92,25 +82,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleull_sext_store(i64 %a, i64 %b) {
-; BE-LABEL: test_llleull_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r4, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    subfe r3, r3, r3
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleull_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    subc r4, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r3, r3
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llleull_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subc r4, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -119,23 +99,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleull_z_store(i64 %a) {
-; BE-LABEL: test_llleull_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzd r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    rldicl r3, r3, 58, 63
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleull_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzd r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 58, 63
-; LE-NEXT:    std r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleull_z_store(i64 %a) {
+; CHECK-LABEL: test_llleull_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = zext i1 %cmp to i64
@@ -144,23 +115,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleull_sext_z_store(i64 %a) {
-; BE-LABEL: test_llleull_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    addic r3, r3, -1
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    subfe r3, r3, r3
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleull_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addic r3, r3, -1
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    subfe r3, r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llleull_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
index 8c852f1..18120bf 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
@@ -66,25 +66,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_llleus_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleus_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llleus_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -93,25 +83,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_llleus_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    addi r3, r3, -1
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleus_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    addi r3, r3, -1
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llleus_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -120,23 +100,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleus_z_store(i16 zeroext %a) {
-; BE-LABEL: test_llleus_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleus_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    sth r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llleus_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = zext i1 %cmp to i16
@@ -145,25 +116,15 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llleus_sext_z_store(i16 zeroext %a) {
-; BE-LABEL: test_llleus_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    cntlzw r3, r3
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    srwi r3, r3, 5
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    sth r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llleus_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    cntlzw r3, r3
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    srwi r3, r3, 5
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    sth r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llleus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llleus_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
index fbaa5cb..5da4b25 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltsll(i64 %a, i64 %b) {
@@ -56,29 +56,17 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltsll_store(i64 %a, i64 %b) {
-; BE-LABEL: test_llltsll_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    sradi r6, r3, 63
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    adde r3, r3, r6
-; BE-NEXT:    xori r3, r3, 1
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltsll_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sradi r6, r3, 63
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
-; LE-NEXT:    adde r3, r3, r6
-; LE-NEXT:    xori r3, r3, 1
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llltsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltsll_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -88,31 +76,18 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltsll_sext_store(i64 %a, i64 %b) {
-; BE-LABEL: test_llltsll_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    sradi r6, r3, 63
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
-; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    adde r3, r3, r6
-; BE-NEXT:    xori r3, r3, 1
-; BE-NEXT:    neg r3, r3
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltsll_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sradi r6, r3, 63
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
-; LE-NEXT:    adde r3, r3, r6
-; LE-NEXT:    xori r3, r3, 1
-; LE-NEXT:    neg r3, r3
-; LE-NEXT:    std r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llltsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltsll_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    subc r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -122,21 +97,13 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltsll_sext_z_store(i64 %a) {
-; BE-LABEL: test_llltsll_sext_z_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r4, r2, .LC0@toc@ha
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    std r3, 0(r4)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltsll_sext_z_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    std r3, glob@toc@l(r4)
-; LE-NEXT:    blr
+define dso_local void @test_llltsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llltsll_sext_z_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, glob@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 0
   %sub = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
index dafbbc1..cc3ebac 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i8 0, align 1
+@glob = dso_local local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
@@ -37,23 +37,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_llltuc_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    stb r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltuc_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -62,23 +53,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; BE-LABEL: test_llltuc_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    stb r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltuc_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    stb r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = sext i1 %cmp to i8

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltus.ll b/llvm/test/CodeGen/PowerPC/testComparesllltus.ll
index 217821b..fbe6553 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllltus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltus.ll
@@ -8,7 +8,7 @@
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
 
-@glob = local_unnamed_addr global i16 0, align 2
+@glob = dso_local local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
@@ -37,23 +37,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_llltus_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
-; BE-NEXT:    sth r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltus_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -62,23 +53,14 @@ entry:
 }
 
 ; Function Attrs: norecurse nounwind
-define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; BE-LABEL: test_llltus_sext_store:
-; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    sradi r3, r3, 63
-; BE-NEXT:    sth r3, 0(r5)
-; BE-NEXT:    blr
-;
-; LE-LABEL: test_llltus_sext_store:
-; LE:       # %bb.0: # %entry
-; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    sradi r3, r3, 63
-; LE-NEXT:    sth r3, glob@toc@l(r5)
-; LE-NEXT:    blr
+define dso_local void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext_store:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, glob@toc@l(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = sext i1 %cmp to i16

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll
index 76ea626..7528c33 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 define i64 @test_llnesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll:
@@ -106,7 +106,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @test_llnesll_store(i64 %a, i64 %b) {
+define dso_local void @test_llnesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -117,12 +117,11 @@ define void @test_llnesll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llnesll_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-BE-NEXT:    addic r4, r3, -1
+; CHECK-BE-NEXT:    subfe r3, r4, r3
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llnesll_store:
@@ -140,7 +139,7 @@ entry:
   ret void
 }
 
-define void @test_llnesll_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_llnesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -151,12 +150,11 @@ define void @test_llnesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llnesll_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llnesll_sext_store:
@@ -174,7 +172,7 @@ entry:
   ret void
 }
 
-define void @test_llnesll_z_store(i64 %a) {
+define dso_local void @test_llnesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llnesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r5, r3, -1
@@ -184,11 +182,10 @@ define void @test_llnesll_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llnesll_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llnesll_z_store:
@@ -205,7 +202,7 @@ entry:
   ret void
 }
 
-define void @test_llnesll_sext_z_store(i64 %a) {
+define dso_local void @test_llnesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llnesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
@@ -215,11 +212,10 @@ define void @test_llnesll_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llnesll_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llnesll_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllneull.ll b/llvm/test/CodeGen/PowerPC/testComparesllneull.ll
index e809a0b..d6b2604 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllneull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllneull.ll
@@ -6,7 +6,7 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 
-@glob = local_unnamed_addr global i64 0, align 8
+@glob = dso_local local_unnamed_addr global i64 0, align 8
 
 define i64 @test_llneull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull:
@@ -106,7 +106,7 @@ entry:
   ret i64 %conv1
 }
 
-define void @test_llneull_store(i64 %a, i64 %b) {
+define dso_local void @test_llneull_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -117,12 +117,11 @@ define void @test_llneull_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llneull_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
+; CHECK-BE-NEXT:    addic r4, r3, -1
+; CHECK-BE-NEXT:    subfe r3, r4, r3
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llneull_store:
@@ -140,7 +139,7 @@ entry:
   ret void
 }
 
-define void @test_llneull_sext_store(i64 %a, i64 %b) {
+define dso_local void @test_llneull_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull_sext_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
@@ -151,12 +150,11 @@ define void @test_llneull_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llneull_sext_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xor r3, r3, r4
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llneull_sext_store:
@@ -174,7 +172,7 @@ entry:
   ret void
 }
 
-define void @test_llneull_z_store(i64 %a) {
+define dso_local void @test_llneull_z_store(i64 %a) {
 ; CHECK-LABEL: test_llneull_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r5, r3, -1
@@ -184,11 +182,10 @@ define void @test_llneull_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llneull_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    addic r5, r3, -1
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r5, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llneull_z_store:
@@ -205,7 +202,7 @@ entry:
   ret void
 }
 
-define void @test_llneull_sext_z_store(i64 %a) {
+define dso_local void @test_llneull_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llneull_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
@@ -215,11 +212,10 @@ define void @test_llneull_sext_z_store(i64 %a) {
 ; CHECK-NEXT:    blr
 ; CHECK-BE-LABEL: test_llneull_sext_z_store:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subfic r3, r3, 0
-; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-BE-NEXT:    subfe r3, r3, r3
-; CHECK-BE-NEXT:    std r3, 0(r4)
+; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llneull_sext_z_store:

diff --git a/llvm/test/CodeGen/PowerPC/tls.ll b/llvm/test/CodeGen/PowerPC/tls.ll
index c5570e1..e2c9006 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/tls.ll
+++ b/llvm/test/CodeGen/PowerPC/tls.ll
@@ -5,11 +5,11 @@
 ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32-PIC %s
 
-@a = thread_local global i32 0, align 4
+@a = dso_local thread_local global i32 0, align 4
 
 ;OPT0-LABEL:          localexec:
 ;OPT1-LABEL:          localexec:
-define i32 @localexec() nounwind {
+define dso_local i32 @localexec() nounwind {
 entry:
 ;OPT0:          addis [[REG1:[1-9][0-9]*]], 13, a@tprel@ha
 ;OPT0-NEXT:     addi [[REG2:[1-9][0-9]*]], [[REG1]], a@tprel@l
@@ -27,7 +27,7 @@ entry:
 
 @a2 = external thread_local(initialexec) global i32
 
-define signext i32 @main2() nounwind {
+define dso_local signext i32 @main2() nounwind {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval