ARM: dts: meson: add the SDIO MMC controller
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Sat, 7 Oct 2017 16:29:39 +0000 (18:29 +0200)
committerKevin Hilman <khilman@baylibre.com>
Thu, 12 Oct 2017 00:18:25 +0000 (17:18 -0700)
Meson6, Meson8 and Meson8b are using the same MMC controller IP. This
adds the MMC controller node to meson.dtsi so it can be used by all
SoCs.

The controller itself is a bit special, because it has multiple slots.
Each slot is accessed through a sub-node of the controller. However,
currently the driver for this hardware only supports one slot.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm/boot/dts/meson.dtsi
arch/arm/boot/dts/meson8.dtsi
arch/arm/boot/dts/meson8b.dtsi

index 7ae30e7..290a183 100644 (file)
                                status = "disabled";
                        };
 
+                       sdio: mmc@8c20 {
+                               compatible = "amlogic,meson-mx-sdio";
+                               reg = <0x8c20 0x20>;
+                               interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        spifc: spi@8c80 {
                                compatible = "amlogic,meson6-spifc";
                                reg = <0x8c80 0x80>;
index ada26f8..e6abcc7 100644 (file)
        clock-names = "clkin", "core", "sana";
 };
 
+&sdio {
+       compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
+       clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
+       clock-names = "core", "clkin";
+};
+
 &spifc {
        clocks = <&clkc CLKID_CLK81>;
 };
index bc4d4a2..283c68c 100644 (file)
        clock-names = "clkin", "core", "sana";
 };
 
+&sdio {
+       compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
+       clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
+       clock-names = "core", "clkin";
+};
+
 &uart_AO {
        clocks = <&clkc CLKID_CLK81>;
 };