[Aarch64] Adding support for Armv9-A Realm Management Extension

This adds support for Armv9-A's Realm Management Extension, including
three new system registers - MFAR_EL3, GPCCR_EL3 and GPTBR_EL3 - and
four new TLBI instructions.

The reference for the Realm Management Extension can be found at: https://developer.arm.com/documentation/ddi0615/aa.

Based on patches by Victor Campos.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D104773

diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index bb88699..e0961e6 100644 (file)
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -74,6 +74,11 @@ Changes to building LLVM
 Changes to TableGen
 -------------------
 
+Changes to the AArch64 Backend
+--------------------------
+
+* Introduced support for Armv9-A's Realm Management Extension.
+
 Changes to the ARM Backend
 --------------------------
 

diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index dab6dbe..4e1dc81 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -426,6 +426,9 @@ def FeatureEnhancedCounterVirtualization :
       SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
       "true", "Enable enhanced counter virtualization extension">;
 
+def FeatureRME : SubtargetFeature<"rme", "HasRME",
+    "true", "Enable Realm Management Extension">;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index ea1fbc1..491e7bd 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -183,6 +183,9 @@ protected:
   bool HasSVE2SHA3 = false;
   bool HasSVE2BitPerm = false;
 
+  // Armv9-A Extensions
+  bool HasRME = false;
+
   // Future architecture extensions.
   bool HasETE = false;
   bool HasTRBE = false;

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1909e79..8594ec9 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -531,6 +531,14 @@ defm : TLBI<"RVAE3OS",      0b110, 0b1000, 0b0101, 0b001>;
 defm : TLBI<"RVALE3OS",     0b110, 0b1000, 0b0101, 0b101>;
 } //FeatureTLB_RMI
 
+// Armv9-A Realm Management Extention TLBI Instructions
+let Requires = ["AArch64::FeatureRME"] in {
+defm : TLBI<"RPAOS",        0b110, 0b1000, 0b0100, 0b011>;
+defm : TLBI<"RPALOS",       0b110, 0b1000, 0b0100, 0b111>;
+defm : TLBI<"PAALLOS",      0b110, 0b1000, 0b0001, 0b100, 0>;
+defm : TLBI<"PAALL",        0b110, 0b1000, 0b0111, 0b100, 0>;
+}
+
 // Armv8.5-A Prediction Restriction by Context instruction options:
 class PRCTX<string name, bits<4> crm> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
@@ -743,6 +751,13 @@ def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;
 }
 
+// v9a Realm Management Extension registers
+let Requires = [{ {AArch64::FeatureRME} }] in {
+def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
+def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
+}
+
 //===----------------------
 // Write-only regs
 //===----------------------

diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index d2a0b1d..cd7001f 100644 (file)
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2917,6 +2917,7 @@ static const struct Extension {
     {"xs", {AArch64::FeatureXS}},
     {"pauth", {AArch64::FeaturePAuth}},
     {"flagm", {AArch64::FeatureFlagM}},
+    {"rme", {AArch64::FeatureRME}},
     // FIXME: Unsupported extensions
     {"lor", {}},
     {"rdma", {}},

diff --git a/llvm/test/MC/AArch64/armv9a-rme.s b/llvm/test/MC/AArch64/armv9a-rme.s
new file mode 100644 (file)
index 0000000..0a575fa
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9a-rme.s
@@ -0,0 +1,70 @@
+// RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -show-encoding %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-arm-none-eabi -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK-NO-RME %s
+// RUN: FileCheck --check-prefix=CHECK-NO-RME-ERROR %s < %t
+
+msr MFAR_EL3, x0
+msr GPCCR_EL3, x0
+msr GPTBR_EL3, x0
+mrs x0, MFAR_EL3
+mrs x0, GPCCR_EL3
+mrs x0, GPTBR_EL3
+// CHECK: msr MFAR_EL3,  x0   // encoding: [0xa0,0x60,0x1e,0xd5]
+// CHECK: msr GPCCR_EL3, x0   // encoding: [0xc0,0x21,0x1e,0xd5]
+// CHECK: msr GPTBR_EL3, x0   // encoding: [0x80,0x21,0x1e,0xd5]
+// CHECK: mrs x0, MFAR_EL3    // encoding: [0xa0,0x60,0x3e,0xd5]
+// CHECK: mrs x0, GPCCR_EL3   // encoding: [0xc0,0x21,0x3e,0xd5]
+// CHECK: mrs x0, GPTBR_EL3   // encoding: [0x80,0x21,0x3e,0xd5]
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+
+tlbi rpaos, x0
+tlbi rpalos, x0
+tlbi paallos
+tlbi paall
+// CHECK: tlbi rpaos, x0      // encoding: [0x60,0x84,0x0e,0xd5]
+// CHECK: tlbi rpalos, x0     // encoding: [0xe0,0x84,0x0e,0xd5]
+// CHECK: tlbi paallos        // encoding: [0x9f,0x81,0x0e,0xd5]
+// CHECK: tlbi paall          // encoding: [0x9f,0x87,0x0e,0xd5]
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI RPAOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI RPALOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI PAALLOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI PAALL requires: rme
+
+tlbi RPAOS
+tlbi RPALOS
+tlbi PAALLOS, x25
+tlbi PAALL, x25
+// CHECK-ERROR: error: specified {{TLBI|tlbi}} op requires a register
+// CHECK-ERROR-NEXT:         tlbi RPAOS
+// CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
+// CHECK-ERROR-NEXT:         tlbi RPALOS
+// CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
+// CHECK-ERROR-NEXT:         tlbi PAALLOS, x25
+// CHECK-ERROR-NEXT:                       ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
+// CHECK-ERROR-NEXT:         tlbi PAALL, x25
+// CHECK-ERROR-NEXT:                    ^
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI RPAOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI RPALOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI PAALLOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI PAALL requires: rme
+
+sys #6, c8, c4, #3
+sys #6, c8, c4, #7
+sys #6, c8, c1, #4
+sys #6, c8, c7, #4
+// CHECK: tlbi rpaos
+// CHECK: tlbi rpalos
+// CHECK: tlbi paallos
+// CHECK: tlbi paall
+// CHECK-NO-RME: sys #6, c8, c4, #3
+// CHECK-NO-RME: sys #6, c8, c4, #7
+// CHECK-NO-RME: sys #6, c8, c1, #4
+// CHECK-NO-RME: sys #6, c8, c7, #4

diff --git a/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
new file mode 100644 (file)
index 0000000..f10a07c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -disassemble %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple aarch64-arm-none-eabi -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-RME %s
+
+[0xa0,0x60,0x3e,0xd5]
+[0xc0,0x21,0x3e,0xd5]
+[0x80,0x21,0x3e,0xd5]
+# CHECK: mrs x0, MFAR_EL3
+# CHECK: mrs x0, GPCCR_EL3
+# CHECK: mrs x0, GPTBR_EL3
+# CHECK-NO-RME: mrs x0, S3_6_C6_C0_5
+# CHECK-NO-RME: mrs x0, S3_6_C2_C1_6
+# CHECK-NO-RME: mrs x0, S3_6_C2_C1_4
+
+[0x60,0x84,0x0e,0xd5]
+[0xe0,0x84,0x0e,0xd5]
+[0x9f,0x81,0x0e,0xd5]
+[0x9f,0x87,0x0e,0xd5]
+# CHECK: tlbi rpaos, x0
+# CHECK: tlbi rpalos, x0
+# CHECK: tlbi paallos
+# CHECK: tlbi paall
+# CHECK-NO-RME: sys #6, c8, c4, #3
+# CHECK-NO-RME: sys #6, c8, c4, #7
+# CHECK-NO-RME: sys #6, c8, c1, #4
+# CHECK-NO-RME: sys #6, c8, c7, #4
\ No newline at end of file