+2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * testsuite/i386/avx512_4fmaps_vl-warn.l: Likewise.
+ * testsuite/i386/avx512_4fmaps_vl-warn.s: Likewise.
+ * testsuite/i386/avx512_4fmaps_vl.d: Likewise.
+ * testsuite/i386/avx512_4fmaps_vl.s: Likewise.
+ * testsuite/i386/avx512_4vnniw_vl-intel.d: Likewise.
+ * testsuite/i386/avx512_4vnniw_vl.d: Likewise.
+ * testsuite/i386/avx512_4vnniw_vl.s: Likewise.
+ * testsuite/i386/i386.exp: Removed _vl tests for 4fmaps an 4vnniw
+ tests.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl-intel.d: Removed.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
+ * testsuite/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
+ * testsuite/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
+ * testsuite/i386/x86-64-avx512_4vnniw_vl.s: Likewise.
+
2018-01-11 Alan Modra <amodra@gmail.com>
* config/tc-arm.c (aeabi_set_public_attributes): Avoid false
.*: Assembler messages:
-.*:5: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:6: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:7: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:10: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:11: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:12: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
+.*:5: Warning: the second source register `%zmm1' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
+.*:6: Warning: the second source register `%zmm2' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
+.*:7: Warning: the second source register `%zmm3' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
+.*:10: Warning: the second source register `%zmm1' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
+.*:11: Warning: the second source register `%zmm2' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
+.*:12: Warning: the second source register `%zmm3' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
.*:15: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddss'
.*:16: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddss'
.*:17: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddss'
# Check warnings for invalid usage of register group
.text
- v4fmaddps (%eax), %xmm0, %xmm6
- v4fmaddps (%eax), %xmm1, %xmm6
- v4fmaddps (%eax), %xmm2, %xmm6
- v4fmaddps (%eax), %xmm3, %xmm6
- v4fmaddps (%eax), %xmm4, %xmm6
- v4fnmaddps (%eax), %xmm0, %xmm6
- v4fnmaddps (%eax), %xmm1, %xmm6
- v4fnmaddps (%eax), %xmm2, %xmm6
- v4fnmaddps (%eax), %xmm3, %xmm6
- v4fnmaddps (%eax), %xmm4, %xmm6
+ v4fmaddps (%eax), %zmm0, %zmm6
+ v4fmaddps (%eax), %zmm1, %zmm6
+ v4fmaddps (%eax), %zmm2, %zmm6
+ v4fmaddps (%eax), %zmm3, %zmm6
+ v4fmaddps (%eax), %zmm4, %zmm6
+ v4fnmaddps (%eax), %zmm0, %zmm6
+ v4fnmaddps (%eax), %zmm1, %zmm6
+ v4fnmaddps (%eax), %zmm2, %zmm6
+ v4fnmaddps (%eax), %zmm3, %zmm6
+ v4fnmaddps (%eax), %zmm4, %zmm6
v4fmaddss (%eax), %xmm0, %xmm6
v4fmaddss (%eax), %xmm1, %xmm6
v4fmaddss (%eax), %xmm2, %xmm6
+++ /dev/null
-#objdump: -dw -Mintel
-#name: i386 AVX512/4FMAPS_VL insns (Intel disassembly)
-#source: avx512_4fmaps_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 09[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 9a 09[ ]*v4fmaddps xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 9a 09[ ]*v4fmaddps xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 7f[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a 00 08 00 00[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 80[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 09[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 9a 09[ ]*v4fmaddps ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 9a 09[ ]*v4fmaddps ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 7f[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a 00 08 00 00[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 80[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 09[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f aa 09[ ]*v4fnmaddps xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f aa 09[ ]*v4fnmaddps xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 7f[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 80[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 09[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f aa 09[ ]*v4fnmaddps ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af aa 09[ ]*v4fnmaddps ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 7f[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 80[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx\-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 09[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 09[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 9a 09[ ]*v4fmaddps xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 9a 09[ ]*v4fmaddps xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 7f[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a 00 08 00 00[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 80[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 09[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 09[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 9a 09[ ]*v4fmaddps ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 9a 09[ ]*v4fmaddps ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 7f[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a 00 08 00 00[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 80[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 09[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 09[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f aa 09[ ]*v4fnmaddps xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f aa 09[ ]*v4fnmaddps xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 7f[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 80[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps xmm1,xmm4,XMMWORD PTR \[edx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 09[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 09[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f aa 09[ ]*v4fnmaddps ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af aa 09[ ]*v4fnmaddps ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 7f[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 80[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps ymm1,ymm4,XMMWORD PTR \[edx-0x810\]
-#pass
+++ /dev/null
-.*: Assembler messages:
-.*:5: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:6: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:7: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:10: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:11: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:12: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:15: Warning: the second source register `%ymm1' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fmaddps'
-.*:16: Warning: the second source register `%ymm2' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fmaddps'
-.*:17: Warning: the second source register `%ymm3' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fmaddps'
-.*:20: Warning: the second source register `%ymm1' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fnmaddps'
-.*:21: Warning: the second source register `%ymm2' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fnmaddps'
-.*:22: Warning: the second source register `%ymm3' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fnmaddps'
+++ /dev/null
-# Check warnings for invalid usage of register group
-
-.text
- v4fmaddps (%eax), %xmm0, %xmm6
- v4fmaddps (%eax), %xmm1, %xmm6
- v4fmaddps (%eax), %xmm2, %xmm6
- v4fmaddps (%eax), %xmm3, %xmm6
- v4fmaddps (%eax), %xmm4, %xmm6
- v4fnmaddps (%eax), %xmm0, %xmm6
- v4fnmaddps (%eax), %xmm1, %xmm6
- v4fnmaddps (%eax), %xmm2, %xmm6
- v4fnmaddps (%eax), %xmm3, %xmm6
- v4fnmaddps (%eax), %xmm4, %xmm6
- v4fmaddps (%eax), %ymm0, %ymm6
- v4fmaddps (%eax), %ymm1, %ymm6
- v4fmaddps (%eax), %ymm2, %ymm6
- v4fmaddps (%eax), %ymm3, %ymm6
- v4fmaddps (%eax), %ymm4, %ymm6
- v4fnmaddps (%eax), %ymm0, %ymm6
- v4fnmaddps (%eax), %ymm1, %ymm6
- v4fnmaddps (%eax), %ymm2, %ymm6
- v4fnmaddps (%eax), %ymm3, %ymm6
- v4fnmaddps (%eax), %ymm4, %ymm6
+++ /dev/null
-#objdump: -dw
-#name: i386 AVX512/4FMAPS_VL insns
-#source: avx512_4fmaps_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 80[ ]*v4fmaddps -0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 80[ ]*v4fmaddps -0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 80[ ]*v4fnmaddps -0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 80[ ]*v4fnmaddps -0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 9a 09[ ]*v4fmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 4a 80[ ]*v4fmaddps -0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 9a 09[ ]*v4fmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8c f4 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 4a 80[ ]*v4fmaddps -0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f aa 09[ ]*v4fnmaddps \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 4a 80[ ]*v4fnmaddps -0x800\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af aa 09[ ]*v4fnmaddps \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8c f4 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 4a 80[ ]*v4fnmaddps -0x800\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%edx\),%ymm4,%ymm1
-#pass
+++ /dev/null
-# Check 32bit AVX512{_4FMAPS,VL} instructions
-
- .allow_index_reg
- .text
-_start:
- v4fmaddps (%ecx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4FMAPS,VL}
- v4fmaddps (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fmaddps -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps 0x7f0(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps 0x800(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps -0x800(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps -0x810(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps (%ecx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fmaddps (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4FMAPS,VL}
- v4fmaddps (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fmaddps -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fmaddps 0x7f0(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps 0x800(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fmaddps -0x800(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps -0x810(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%ecx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4FMAPS,VL}
- v4fnmaddps (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fnmaddps -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps 0x7f0(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps 0x800(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps -0x800(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps -0x810(%edx), %xmm4, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%ecx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4FMAPS,VL}
- v4fnmaddps (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fnmaddps -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps 0x7f0(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps 0x800(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps -0x800(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps -0x810(%edx), %ymm4, %ymm1 # AVX512{_4FMAPS,VL}
-
- .intel_syntax noprefix
- v4fmaddps xmm1, xmm4, [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm4, XMMWORD PTR [edx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps xmm1, xmm4, XMMWORD PTR [edx+0x800] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm4, XMMWORD PTR [edx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps xmm1, xmm4, XMMWORD PTR [edx-0x810] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm4, [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm4, XMMWORD PTR [edx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps ymm1, ymm4, XMMWORD PTR [edx+0x800] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm4, XMMWORD PTR [edx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps ymm1, ymm4, XMMWORD PTR [edx-0x810] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm4, [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm4, XMMWORD PTR [edx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps xmm1, xmm4, XMMWORD PTR [edx+0x800] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm4, XMMWORD PTR [edx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps xmm1, xmm4, XMMWORD PTR [edx-0x810] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm4, [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm4, XMMWORD PTR [edx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps ymm1, ymm4, XMMWORD PTR [edx+0x800] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm4, XMMWORD PTR [edx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps ymm1, ymm4, XMMWORD PTR [edx-0x810] # AVX512{_4FMAPS,VL}
+++ /dev/null
-#objdump: -dw -Mintel
-#name: i386 AVX512/4VNNIW_VL insns (Intel disassembly)
-#source: avx512_4vnniw_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
-#pass
+++ /dev/null
-#objdump: -dw
-#name: i386 AVX512/4VNNIW_VL insns
-#source: avx512_4vnniw_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%xmm4,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%ymm4,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%ymm4,%ymm1
-#pass
+++ /dev/null
-# Check 32bit AVX512{_4VNNIW,VL} instructions
-
- .allow_index_reg
- .text
-_start:
- vp4dpwssd (%ecx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssd (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssd -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd 4064(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd 4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd -4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd -4128(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd (%ecx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssd (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssd -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd 4064(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd 4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd -4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd -4128(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%ecx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssds (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssds -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds 4064(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds 4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds -4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds -4128(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%ecx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssds (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssds -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds 4064(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds 4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds -4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds -4128(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
-
- .intel_syntax noprefix
- vp4dpwssd xmm1, xmm4, [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm4, [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm4, [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm4, [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
run_dump_test "avx512vbmi_vl-intel"
run_dump_test "avx512_4fmaps"
run_dump_test "avx512_4fmaps-intel"
- run_dump_test "avx512_4fmaps_vl"
- run_dump_test "avx512_4fmaps_vl-intel"
run_list_test "avx512_4fmaps-warn"
- run_list_test "avx512_4fmaps_vl-warn"
run_dump_test "avx512_4vnniw"
run_dump_test "avx512_4vnniw-intel"
- run_dump_test "avx512_4vnniw_vl"
- run_dump_test "avx512_4vnniw_vl-intel"
run_dump_test "avx512_vpopcntdq"
run_dump_test "avx512_vpopcntdq-intel"
run_dump_test "avx512vbmi2"
run_dump_test "x86-64-avx512vbmi_vl-intel"
run_dump_test "x86-64-avx512_4fmaps"
run_dump_test "x86-64-avx512_4fmaps-intel"
- run_dump_test "x86-64-avx512_4fmaps_vl"
- run_dump_test "x86-64-avx512_4fmaps_vl-intel"
run_list_test "x86-64-avx512_4fmaps-warn"
- run_list_test "x86-64-avx512_4fmaps_vl-warn"
run_dump_test "x86-64-avx512_4vnniw"
run_dump_test "x86-64-avx512_4vnniw-intel"
- run_dump_test "x86-64-avx512_4vnniw_vl"
- run_dump_test "x86-64-avx512_4vnniw_vl-intel"
run_dump_test "x86-64-avx512_vpopcntdq"
run_dump_test "x86-64-avx512_vpopcntdq-intel"
run_dump_test "x86-64-avx512vbmi2"
+++ /dev/null
-#objdump: -dw -Mintel
-#name: x86_64 AVX512/4FMAPS_VL insns (Intel disassembly)
-#source: x86-64-avx512_4fmaps_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 09[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 9a 09[ ]*v4fmaddps xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 9a 09[ ]*v4fmaddps xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 7f[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a 00 08 00 00[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 80[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 09[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 9a 09[ ]*v4fmaddps ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 9a 09[ ]*v4fmaddps ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 7f[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a 00 08 00 00[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 80[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 09[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f aa 09[ ]*v4fnmaddps xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f aa 09[ ]*v4fnmaddps xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 7f[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 80[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 09[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f aa 09[ ]*v4fnmaddps ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af aa 09[ ]*v4fnmaddps ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 7f[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 80[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 09[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 09[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 9a 09[ ]*v4fmaddps xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 9a 09[ ]*v4fmaddps xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 7f[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a 00 08 00 00[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 80[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 09[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 09[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 9a 09[ ]*v4fmaddps ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 9a 09[ ]*v4fmaddps ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 7f[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a 00 08 00 00[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 80[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 09[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 09[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f aa 09[ ]*v4fnmaddps xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f aa 09[ ]*v4fnmaddps xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 7f[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 80[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps xmm1,xmm8,XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 09[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 09[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f aa 09[ ]*v4fnmaddps ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af aa 09[ ]*v4fnmaddps ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 7f[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x7f0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx\+0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 80[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x800\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps ymm1,ymm8,XMMWORD PTR \[rdx-0x810\]
-#pass
+++ /dev/null
-.*: Assembler messages:
-.*:5: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:6: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:7: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddps'
-.*:10: Warning: the second source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:11: Warning: the second source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:12: Warning: the second source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddps'
-.*:15: Warning: the second source register `%ymm1' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fmaddps'
-.*:16: Warning: the second source register `%ymm2' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fmaddps'
-.*:17: Warning: the second source register `%ymm3' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fmaddps'
-.*:20: Warning: the second source register `%ymm1' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fnmaddps'
-.*:21: Warning: the second source register `%ymm2' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fnmaddps'
-.*:22: Warning: the second source register `%ymm3' implicitly denotes `%ymm0' to `%ymm3' source group in `v4fnmaddps'
+++ /dev/null
-# Check warnings for invalid usage of register group
-
-.text
- v4fmaddps (%rax), %xmm0, %xmm10
- v4fmaddps (%rax), %xmm1, %xmm10
- v4fmaddps (%rax), %xmm2, %xmm10
- v4fmaddps (%rax), %xmm3, %xmm10
- v4fmaddps (%rax), %xmm4, %xmm10
- v4fnmaddps (%rax), %xmm0, %xmm10
- v4fnmaddps (%rax), %xmm1, %xmm10
- v4fnmaddps (%rax), %xmm2, %xmm10
- v4fnmaddps (%rax), %xmm3, %xmm10
- v4fnmaddps (%rax), %xmm4, %xmm10
- v4fmaddps (%rax), %ymm0, %ymm10
- v4fmaddps (%rax), %ymm1, %ymm10
- v4fmaddps (%rax), %ymm2, %ymm10
- v4fmaddps (%rax), %ymm3, %ymm10
- v4fmaddps (%rax), %ymm4, %ymm10
- v4fnmaddps (%rax), %ymm0, %ymm10
- v4fnmaddps (%rax), %ymm1, %ymm10
- v4fnmaddps (%rax), %ymm2, %ymm10
- v4fnmaddps (%rax), %ymm3, %ymm10
- v4fnmaddps (%rax), %ymm4, %ymm10
+++ /dev/null
-#objdump: -dw
-#name: x86_64 AVX512/4FMAPS_VL insns
-#source: x86-64-avx512_4fmaps_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 80[ ]*v4fmaddps -0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 80[ ]*v4fmaddps -0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 80[ ]*v4fnmaddps -0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 80[ ]*v4fnmaddps -0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 9a 09[ ]*v4fmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 4a 80[ ]*v4fmaddps -0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 9a 09[ ]*v4fmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 9a 8c f0 c0 1d fe ff[ ]*v4fmaddps -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 7f[ ]*v4fmaddps 0x7f0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a 00 08 00 00[ ]*v4fmaddps 0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 4a 80[ ]*v4fmaddps -0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 9a 8a f0 f7 ff ff[ ]*v4fmaddps -0x810\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f aa 09[ ]*v4fnmaddps \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 4a 80[ ]*v4fnmaddps -0x800\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af aa 09[ ]*v4fnmaddps \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 aa 8c f0 c0 1d fe ff[ ]*v4fnmaddps -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 7f[ ]*v4fnmaddps 0x7f0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a 00 08 00 00[ ]*v4fnmaddps 0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 4a 80[ ]*v4fnmaddps -0x800\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 aa 8a f0 f7 ff ff[ ]*v4fnmaddps -0x810\(%rdx\),%ymm8,%ymm1
-#pass
+++ /dev/null
-# Check 64bit AVX512{_4FMAPS,VL} instructions
-
- .allow_index_reg
- .text
-_start:
- v4fmaddps (%rcx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps (%rcx), %xmm8, %xmm1{%k7} # AVX512{_4FMAPS,VL}
- v4fmaddps (%rcx), %xmm8, %xmm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fmaddps -123456(%rax,%r14,8), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps 0x7f0(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps 0x800(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps -0x800(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps -0x810(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fmaddps (%rcx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fmaddps (%rcx), %ymm8, %ymm1{%k7} # AVX512{_4FMAPS,VL}
- v4fmaddps (%rcx), %ymm8, %ymm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fmaddps -123456(%rax,%r14,8), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fmaddps 0x7f0(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps 0x800(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fmaddps -0x800(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps -0x810(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%rcx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%rcx), %xmm8, %xmm1{%k7} # AVX512{_4FMAPS,VL}
- v4fnmaddps (%rcx), %xmm8, %xmm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fnmaddps -123456(%rax,%r14,8), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps 0x7f0(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps 0x800(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps -0x800(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps -0x810(%rdx), %xmm8, %xmm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%rcx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps (%rcx), %ymm8, %ymm1{%k7} # AVX512{_4FMAPS,VL}
- v4fnmaddps (%rcx), %ymm8, %ymm1{%k7}{z} # AVX512{_4FMAPS,VL}
- v4fnmaddps -123456(%rax,%r14,8), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps 0x7f0(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps 0x800(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
- v4fnmaddps -0x800(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps -0x810(%rdx), %ymm8, %ymm1 # AVX512{_4FMAPS,VL}
-
- .intel_syntax noprefix
- v4fmaddps xmm1, xmm8, [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1{k7}, xmm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm8, XMMWORD PTR [rdx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps xmm1, xmm8, XMMWORD PTR [rdx+0x800] # AVX512{_4FMAPS,VL}
- v4fmaddps xmm1, xmm8, XMMWORD PTR [rdx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps xmm1, xmm8, XMMWORD PTR [rdx-0x810] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm8, [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1{k7}, ymm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm8, XMMWORD PTR [rdx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps ymm1, ymm8, XMMWORD PTR [rdx+0x800] # AVX512{_4FMAPS,VL}
- v4fmaddps ymm1, ymm8, XMMWORD PTR [rdx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fmaddps ymm1, ymm8, XMMWORD PTR [rdx-0x810] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm8, [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1{k7}, xmm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm8, XMMWORD PTR [rdx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps xmm1, xmm8, XMMWORD PTR [rdx+0x800] # AVX512{_4FMAPS,VL}
- v4fnmaddps xmm1, xmm8, XMMWORD PTR [rdx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps xmm1, xmm8, XMMWORD PTR [rdx-0x810] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm8, [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1{k7}, ymm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm8, XMMWORD PTR [rdx+0x7f0] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps ymm1, ymm8, XMMWORD PTR [rdx+0x800] # AVX512{_4FMAPS,VL}
- v4fnmaddps ymm1, ymm8, XMMWORD PTR [rdx-0x800] # AVX512{_4FMAPS,VL} Disp8
- v4fnmaddps ymm1, ymm8, XMMWORD PTR [rdx-0x810] # AVX512{_4FMAPS,VL}
+++ /dev/null
-#objdump: -dw -Mintel
-#name: x86_64 AVX512/4VNNIW_VL insns (Intel disassembly)
-#source: x86-64-avx512_4vnniw_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
-#pass
+++ /dev/null
-#objdump: -dw
-#name: x86_64 AVX512/4VNNIW_VL insns
-#source: x86-64-avx512_4vnniw_vl.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%xmm8,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}
-[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
-[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%ymm8,%ymm1
-[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%ymm8,%ymm1
-#pass
+++ /dev/null
-# Check 64bit AVX512{_4VNNIW,VL} instructions
-
- .allow_index_reg
- .text
-_start:
- vp4dpwssd (%rcx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd (%rcx), %xmm8, %xmm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssd (%rcx), %xmm8, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssd -123456(%rax,%r14,8), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd 4064(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd 4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd -4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd -4128(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd (%rcx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd (%rcx), %ymm8, %ymm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssd (%rcx), %ymm8, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssd -123456(%rax,%r14,8), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd 4064(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd 4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssd -4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd -4128(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%rcx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%rcx), %xmm8, %xmm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssds (%rcx), %xmm8, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssds -123456(%rax,%r14,8), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds 4064(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds 4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds -4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds -4128(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%rcx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds (%rcx), %ymm8, %ymm1{%k7} # AVX512{_4VNNIW,VL}
- vp4dpwssds (%rcx), %ymm8, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
- vp4dpwssds -123456(%rax,%r14,8), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds 4064(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds 4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
- vp4dpwssds -4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds -4128(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
-
- .intel_syntax noprefix
- vp4dpwssd xmm1, xmm8, [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1{k7}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm8, [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1{k7}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm8, [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1{k7}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm8, [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1{k7}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
- vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
- vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
+2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
+ * i386-tbl.h: Regenerate.
+
2018-01-10 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
// AVX512_4FMAPS instructions
v4fmaddps, 3, 0xf29a, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-v4fmaddps, 3, 0xf29a, None, 1, CpuAVX512_4FMAPS|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
-v4fmaddps, 3, 0xf29a, None, 1, CpuAVX512_4FMAPS|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
-
v4fnmaddps, 3, 0xf2aa, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-v4fnmaddps, 3, 0xf2aa, None, 1, CpuAVX512_4FMAPS|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
-v4fnmaddps, 3, 0xf2aa, None, 1, CpuAVX512_4FMAPS|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
-
v4fmaddss, 3, 0xf29b, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
-
v4fnmaddss, 3, 0xf2ab, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
// AVX512_4FMAPS instructions end
// AVX512_4VNNIW instructions
vp4dpwssd, 3, 0xf252, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vp4dpwssd, 3, 0xf252, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vp4dpwssd, 3, 0xf252, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
-
vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
// AVX512_4VNNIW instructions end
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0 } } } },
- { "v4fmaddps", 3, 0xf29a, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 2, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } } } },
- { "v4fmaddps", 3, 0xf29a, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } } } },
{ "v4fnmaddps", 3, 0xf2aa, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0 } } } },
- { "v4fnmaddps", 3, 0xf2aa, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 2, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } } } },
- { "v4fnmaddps", 3, 0xf2aa, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } } } },
{ "v4fmaddss", 3, 0xf29b, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0 } } } },
- { "vp4dpwssd", 3, 0xf252, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 2, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } } } },
- { "vp4dpwssd", 3, 0xf252, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } } } },
{ "vp4dpwssds", 3, 0xf253, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0 } } } },
- { "vp4dpwssds", 3, 0xf253, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 2, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0 } } } },
- { "vp4dpwssds", 3, 0xf253, None, 1,
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 4, 0, 1, 0,
- 0, 0, 0, 0, 0 },
- { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } },
- { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
- 0, 0, 0 } } } },
{ "vpopcntd", 2, 0x6655, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
projects / external / binutils.git / commitdiff