arm64: dts: qcom: sm8250: fix display nodes

Apply these fixes to the newly added sm8250 display ndoes
 - Remove "notused" interconnect (which apparently was blindly copied from
   my old patches)
 - Use dispcc node example from dt-bindings, removing clocks which aren't
   documented or used by the driver and fixing the region size.

Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[DB: compatibility changes split into separate patch]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210329120051.3401567-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 9fe1d39..394973e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2287,10 +2287,9 @@
                        reg = <0 0x0ae00000 0 0x1000>;
                        reg-names = "mdss";
 
-                       interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
-                                       <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
+                       interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
                                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
-                       interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+                       interconnect-names = "mdp0-mem", "mdp1-mem";
 
                        power-domains = <&dispcc MDSS_GDSC>;
 
@@ -2540,7 +2539,7 @@
 
                dispcc: clock-controller@af00000 {
                        compatible = "qcom,sm8250-dispcc";
-                       reg = <0 0x0af00000 0 0x20000>;
+                       reg = <0 0x0af00000 0 0x10000>;
                        mmcx-supply = <&mmcx_reg>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&dsi0_phy 0>,
@@ -2548,28 +2547,14 @@
                                 <&dsi1_phy 0>,
                                 <&dsi1_phy 1>,
                                 <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <&sleep_clk>;
+                                <0>;
                        clock-names = "bi_tcxo",
                                      "dsi0_phy_pll_out_byteclk",
                                      "dsi0_phy_pll_out_dsiclk",
                                      "dsi1_phy_pll_out_byteclk",
                                      "dsi1_phy_pll_out_dsiclk",
-                                     "dp_link_clk_divsel_ten",
-                                     "dp_vco_divided_clk_src_mux",
-                                     "dptx1_phy_pll_link_clk",
-                                     "dptx1_phy_pll_vco_div_clk",
-                                     "dptx2_phy_pll_link_clk",
-                                     "dptx2_phy_pll_vco_div_clk",
-                                     "edp_phy_pll_link_clk",
-                                     "edp_phy_pll_vco_div_clk",
-                                     "sleep_clk";
+                                     "dp_phy_pll_link_clk",
+                                     "dp_phy_pll_vco_div_clk";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                        #power-domain-cells = <1>;