New ARC implementation.

bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index b2a8855..e84205f 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,15 @@
+2015-10-07  Cupertino Miranda  <cmiranda@synopsys.com>
+
+       * archures.c: Remove support for older ARC. Added support for new
+       ARC cpus (ARC600, ARC601, ARC700, ARCV2).
+       * bfd-in2.h: Likewise.
+       * config.bfd: Likewise.
+       * cpu-arc.c: Likewise.
+       * elf32-arc.c: Totally changed file with a refactored
+       inplementation of the ARC port.
+       * libbfd.h: Added ARC specific relocation types.
+       * reloc.c: Likewise.
+
 2015-10-06  H.J. Lu  <hongjiu.lu@intel.com>
 
        * bfd.c (bfd_update_compression_header): Clear the ch_reserved

diff --git a/bfd/archures.c b/bfd/archures.c
index 95433f8..51068b9 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -353,10 +353,12 @@ DESCRIPTION
 .#define bfd_mach_v850e2v3      0x45325633
 .#define bfd_mach_v850e3v5      0x45335635 {* ('E'|'3'|'V'|'5') *}
 .  bfd_arch_arc,       {* ARC Cores *}
-.#define bfd_mach_arc_5         5
-.#define bfd_mach_arc_6         6
-.#define bfd_mach_arc_7         7
-.#define bfd_mach_arc_8         8
+.#define bfd_mach_arc_a4        0
+.#define bfd_mach_arc_a5        1
+.#define bfd_mach_arc_arc600    2
+.#define bfd_mach_arc_arc601    4
+.#define bfd_mach_arc_arc700    3
+.#define bfd_mach_arc_arcv2     5
 . bfd_arch_m32c,     {* Renesas M16C/M32C.  *}
 .#define bfd_mach_m16c        0x75
 .#define bfd_mach_m32c        0x78

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index f4f98af..60d7e45 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2148,10 +2148,12 @@ enum bfd_architecture
 #define bfd_mach_v850e2v3      0x45325633
 #define bfd_mach_v850e3v5      0x45335635 /* ('E'|'3'|'V'|'5') */
   bfd_arch_arc,       /* ARC Cores */
-#define bfd_mach_arc_5         5
-#define bfd_mach_arc_6         6
-#define bfd_mach_arc_7         7
-#define bfd_mach_arc_8         8
+#define bfd_mach_arc_a4        0
+#define bfd_mach_arc_a5        1
+#define bfd_mach_arc_arc600    2
+#define bfd_mach_arc_arc601    4
+#define bfd_mach_arc_arc700    3
+#define bfd_mach_arc_arcv2     5
  bfd_arch_m32c,     /* Renesas M16C/M32C.  */
 #define bfd_mach_m16c        0x75
 #define bfd_mach_m32c        0x78
@@ -3620,16 +3622,72 @@ pc-relative or some form of GOT-indirect relocation.  */
   BFD_RELOC_SH_GOTOFFFUNCDESC20,
   BFD_RELOC_SH_FUNCDESC,
 
-/* ARC Cores relocs.
-ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
-not stored in the instruction.  The high 20 bits are installed in bits 26
-through 7 of the instruction.  */
-  BFD_RELOC_ARC_B22_PCREL,
-
-/* ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
-stored in the instruction.  The high 24 bits are installed in bits 23
-through 0.  */
-  BFD_RELOC_ARC_B26,
+/* ARC relocs.  */
+  BFD_RELOC_ARC_NONE,
+  BFD_RELOC_ARC_8,
+  BFD_RELOC_ARC_16,
+  BFD_RELOC_ARC_24,
+  BFD_RELOC_ARC_32,
+  BFD_RELOC_ARC_N8,
+  BFD_RELOC_ARC_N16,
+  BFD_RELOC_ARC_N24,
+  BFD_RELOC_ARC_N32,
+  BFD_RELOC_ARC_SDA,
+  BFD_RELOC_ARC_SECTOFF,
+  BFD_RELOC_ARC_S21H_PCREL,
+  BFD_RELOC_ARC_S21W_PCREL,
+  BFD_RELOC_ARC_S25H_PCREL,
+  BFD_RELOC_ARC_S25W_PCREL,
+  BFD_RELOC_ARC_SDA32,
+  BFD_RELOC_ARC_SDA_LDST,
+  BFD_RELOC_ARC_SDA_LDST1,
+  BFD_RELOC_ARC_SDA_LDST2,
+  BFD_RELOC_ARC_SDA16_LD,
+  BFD_RELOC_ARC_SDA16_LD1,
+  BFD_RELOC_ARC_SDA16_LD2,
+  BFD_RELOC_ARC_S13_PCREL,
+  BFD_RELOC_ARC_W,
+  BFD_RELOC_ARC_32_ME,
+  BFD_RELOC_ARC_32_ME_S,
+  BFD_RELOC_ARC_N32_ME,
+  BFD_RELOC_ARC_SECTOFF_ME,
+  BFD_RELOC_ARC_SDA32_ME,
+  BFD_RELOC_ARC_W_ME,
+  BFD_RELOC_AC_SECTOFF_U8,
+  BFD_RELOC_AC_SECTOFF_U8_1,
+  BFD_RELOC_AC_SECTOFF_U8_2,
+  BFD_RELOC_AC_SECTFOFF_S9,
+  BFD_RELOC_AC_SECTFOFF_S9_1,
+  BFD_RELOC_AC_SECTFOFF_S9_2,
+  BFD_RELOC_ARC_SECTOFF_ME_1,
+  BFD_RELOC_ARC_SECTOFF_ME_2,
+  BFD_RELOC_ARC_SECTOFF_1,
+  BFD_RELOC_ARC_SECTOFF_2,
+  BFD_RELOC_ARC_SDA16_ST2,
+  BFD_RELOC_ARC_PC32,
+  BFD_RELOC_ARC_GOT32,
+  BFD_RELOC_ARC_GOTPC32,
+  BFD_RELOC_ARC_PLT32,
+  BFD_RELOC_ARC_COPY,
+  BFD_RELOC_ARC_GLOB_DAT,
+  BFD_RELOC_ARC_JMP_SLOT,
+  BFD_RELOC_ARC_RELATIVE,
+  BFD_RELOC_ARC_GOTOFF,
+  BFD_RELOC_ARC_GOTPC,
+  BFD_RELOC_ARC_S21W_PCREL_PLT,
+  BFD_RELOC_ARC_S25H_PCREL_PLT,
+  BFD_RELOC_ARC_TLS_DTPMOD,
+  BFD_RELOC_ARC_TLS_TPOFF,
+  BFD_RELOC_ARC_TLS_GD_GOT,
+  BFD_RELOC_ARC_TLS_GD_LD,
+  BFD_RELOC_ARC_TLS_GD_CALL,
+  BFD_RELOC_ARC_TLS_IE_GOT,
+  BFD_RELOC_ARC_TLS_DTPOFF,
+  BFD_RELOC_ARC_TLS_DTPOFF_S9,
+  BFD_RELOC_ARC_TLS_LE_S9,
+  BFD_RELOC_ARC_TLS_LE_32,
+  BFD_RELOC_ARC_S25W_PCREL_PLT,
+  BFD_RELOC_ARC_S21H_PCREL_PLT,
 
 /* ADI Blackfin 16 bit immediate absolute reloc.  */
   BFD_RELOC_BFIN_16_IMM,

diff --git a/bfd/config.bfd b/bfd/config.bfd
index 30b45b5..fe43153 100644 (file)
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -93,6 +93,7 @@ case "${targ_cpu}" in
 aarch64*)       targ_archs="bfd_aarch64_arch bfd_arm_arch";;
 alpha*)                 targ_archs=bfd_alpha_arch ;;
 am34*|am33_2.0*) targ_archs=bfd_mn10300_arch ;;
+arc*)           targ_archs=bfd_arc_arch ;;
 arm*)           targ_archs=bfd_arm_arch ;;
 bfin*)          targ_archs=bfd_bfin_arch ;;
 c30*)           targ_archs=bfd_tic30_arch ;;
@@ -262,7 +263,7 @@ case "${targ}" in
     targ_defvec=am33_elf32_linux_vec
     ;;
 
-  arc-*-elf*)
+  arc*-*-elf* | arc*-*-linux-uclibc*)
     targ_defvec=arc_elf32_le_vec
     targ_selvecs=arc_elf32_be_vec
     ;;

diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index a99e539..8bf4393 100644 (file)
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -42,22 +42,24 @@
 
 static const bfd_arch_info_type arch_info_struct[] =
 {
-  ARC ( bfd_mach_arc_5, "arc5", FALSE, &arch_info_struct[1] ),
-  ARC ( bfd_mach_arc_5, "base", FALSE, &arch_info_struct[2] ),
-  ARC ( bfd_mach_arc_6, "arc6", FALSE, &arch_info_struct[3] ),
-  ARC ( bfd_mach_arc_7, "arc7", FALSE, &arch_info_struct[4] ),
-  ARC ( bfd_mach_arc_8, "arc8", FALSE, NULL ),
+  ARC (bfd_mach_arc_arc600, "ARC600", FALSE, &arch_info_struct[1]),
+  ARC (bfd_mach_arc_arc600, "A6"    , FALSE, &arch_info_struct[2]),
+  ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
+  ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
+  ARC (bfd_mach_arc_arc700, "A7",     FALSE, &arch_info_struct[5]),
+  ARC (bfd_mach_arc_arcv2,  "ARCv2",  FALSE, &arch_info_struct[6]),
+  ARC (bfd_mach_arc_arcv2,  "EM",     FALSE, &arch_info_struct[7]),
+  ARC (bfd_mach_arc_arcv2,  "HS",     FALSE, NULL),
 };
 
 const bfd_arch_info_type bfd_arc_arch =
-  ARC ( bfd_mach_arc_6, "arc", TRUE, &arch_info_struct[0] );
+  ARC (bfd_mach_arc_arcv2,  "HS", TRUE, &arch_info_struct[0]);
 
 /* Utility routines.  */
 
 /* Given cpu type NAME, return its bfd_mach_arc_xxx value.
    Returns -1 if not found.  */
-
-int arc_get_mach (char *);
+int arc_get_mach (char *name);
 
 int
 arc_get_mach (char *name)

diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 07af56b..68a47ca 100644 (file)
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -1,6 +1,6 @@
 /* ARC-specific support for 32-bit ELF
    Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+   Contributed by Cupertino Miranda (cmiranda@synopsys.com).
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -25,189 +25,348 @@
 #include "elf-bfd.h"
 #include "elf/arc.h"
 #include "libiberty.h"
+#include "opcode/arc-func.h"
+
+#define ARC_DEBUG(...)
+#define DEBUG(...) printf (__ARGV__)
+#define DEBUG_ARC_RELOC(A)
+
+struct arc_local_data
+{
+  bfd_vma        sdata_begin_symbol_vma;
+  asection *      sdata_output_section;
+  bfd_vma        got_symbol_vma;
+};
+
+struct arc_local_data global_arc_data =
+{
+  .sdata_begin_symbol_vma = 0,
+  .sdata_output_section = NULL,
+  .got_symbol_vma = 0,
+};
+
+struct dynamic_sections
+{
+  bfd_boolean    initialized;
+  asection *      sgot;
+  asection *      srelgot;
+  asection *      sgotplt;
+  asection *      sdyn;
+  asection *      splt;
+  asection *      srelplt;
+};
+
+static struct dynamic_sections
+arc_create_dynamic_sections (bfd * abfd, struct bfd_link_info *info);
+
+enum dyn_section_types
+{
+  got = 0,
+  relgot,
+  gotplt,
+  dyn,
+  plt,
+  relplt,
+  DYN_SECTION_TYPES_END
+};
+
+const char * dyn_section_names[DYN_SECTION_TYPES_END] =
+{
+  ".got",
+  ".rela.got",
+  ".got.plt",
+  ".dynamic",
+  ".plt",
+  ".rela.plt"
+};
+
+/* The default symbols representing the init and fini dyn values.
+   TODO: Check what is the relation of those strings with arclinux.em
+   and DT_INIT.  */
+#define INIT_SYM_STRING "_init"
+#define FINI_SYM_STRING "_fini"
+
+char * init_str = INIT_SYM_STRING;
+char * fini_str = FINI_SYM_STRING;
+
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+      case VALUE: \
+       return #TYPE; \
+       break;
+
+static ATTRIBUTE_UNUSED const char *
+reloc_type_to_name (unsigned int type)
+{
+  switch (type)
+    {
+      #include "elf/arc-reloc.def"
+
+      default:
+       return "UNKNOWN";
+       break;
+    }
+}
+#undef ARC_RELOC_HOWTO
 
 /* Try to minimize the amount of space occupied by relocation tables
    on the ROM (not that the ROM won't be swamped by other ELF overhead).  */
 
-#define USE_REL        1
+#define USE_REL 1
+
+static ATTRIBUTE_UNUSED bfd_boolean
+is_reloc_PC_relative (reloc_howto_type *howto)
+{
+  return (strstr (howto->name, "PC") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_SDA_relative (reloc_howto_type *howto)
+{
+  return (strstr (howto->name, "SDA") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_for_GOT (reloc_howto_type * howto)
+{
+  return (strstr (howto->name, "GOT") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_for_PLT (reloc_howto_type * howto)
+{
+  return (strstr (howto->name, "PLT") != NULL) ? TRUE : FALSE;
+}
+
+#define arc_bfd_get_8(A,B,C) bfd_get_8(A,B)
+#define arc_bfd_get_16(A,B,C) bfd_get_16(A,B)
+#define arc_bfd_put_8(A,B,C,D) bfd_put_8(A,B,C)
+#define arc_bfd_put_16(A,B,C,D) bfd_put_16(A,B,C)
+
+static long
+arc_bfd_get_32 (bfd * abfd, void *loc, asection * input_section)
+{
+  long insn = bfd_get_32 (abfd, loc);
+
+  if (!bfd_big_endian (abfd)
+      && input_section
+      && (input_section->flags & SEC_CODE))
+    insn = ((0x0000fffff & insn) << 16) | ((0xffff0000 & insn) >> 16);
+
+  return insn;
+}
+
+static void
+arc_bfd_put_32 (bfd * abfd, long insn, void *loc, asection * input_section)
+{
+  if (!bfd_big_endian (abfd)
+      && input_section
+      && (input_section->flags & SEC_CODE))
+    insn = ((0x0000fffff & insn) << 16) | ((0xffff0000 & insn) >> 16);
+
+  bfd_put_32 (abfd, insn, loc);
+}
 
 static bfd_reloc_status_type
-arc_elf_b22_pcrel (bfd * abfd,
-                  arelent * reloc_entry,
-                  asymbol * symbol,
-                  void * data,
-                  asection * input_section,
-                  bfd * output_bfd,
-                  char ** error_message)
-{
-  /* If linking, back up the final symbol address by the address of the
-     reloc.  This cannot be accomplished by setting the pcrel_offset
-     field to TRUE, as bfd_install_relocation will detect this and refuse
-     to install the offset in the first place, but bfd_perform_relocation
-     will still insist on removing it.  */
-  if (output_bfd == NULL)
-    reloc_entry->addend -= reloc_entry->address;
-
-  /* Fall through to the default elf reloc handler.  */
-  return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
-                               input_section, output_bfd, error_message);
+arc_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED,
+              arelent *reloc_entry,
+              asymbol *symbol_in,
+              void *data ATTRIBUTE_UNUSED,
+              asection *input_section,
+              bfd *output_bfd,
+              char ** error_message ATTRIBUTE_UNUSED)
+{
+  if (output_bfd != NULL)
+    {
+      reloc_entry->address += input_section->output_offset;
+
+      /* In case of relocateable link and if the reloc is against a
+        section symbol, the addend needs to be adjusted according to
+        where the section symbol winds up in the output section.  */
+      if ((symbol_in->flags & BSF_SECTION_SYM) && symbol_in->section)
+       reloc_entry->addend += symbol_in->section->output_offset;
+
+      return bfd_reloc_ok;
+    }
+
+  return bfd_reloc_continue;
+}
+
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  TYPE = VALUE,
+enum howto_list
+{
+#include "elf/arc-reloc.def"
+  HOWTO_LIST_LAST
+};
+#undef ARC_RELOC_HOWTO
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, RSIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  [TYPE] = HOWTO (R_##TYPE, 0, RSIZE, BITSIZE, FALSE, 0, complain_overflow_##OVERFLOW, arc_elf_reloc, #TYPE, FALSE, 0, 0, FALSE),
+
+static struct reloc_howto_struct elf_arc_howto_table[] =
+{
+#include "elf/arc-reloc.def"
+/* Example of what is generated by the preprocessor.  Currently kept as an example.
+ HOWTO (R_ARC_NONE, // Type.
+    0, // Rightshift.
+    2, // Size (0 = byte, 1 = short, 2 = long).
+    32, // Bitsize.
+    FALSE, // PC_relative.
+    0, // Bitpos.
+    complain_overflow_bitfield, // Complain_on_overflow.
+    bfd_elf_generic_reloc, // Special_function.
+    "R_ARC_NONE", // Name.
+    TRUE, // Partial_inplace.
+    0, // Src_mask.
+    0, // Dst_mask.
+    FALSE), // PCrel_offset.
+*/
+};
+#undef ARC_RELOC_HOWTO
+
+static void arc_elf_howto_init (void)
+{
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  elf_arc_howto_table[TYPE].pc_relative = (strstr (#FORMULA, " P ") != NULL);
+
+  #include "elf/arc-reloc.def"
 }
+#undef ARC_RELOC_HOWTO
 
-static reloc_howto_type elf_arc_howto_table[] =
-{
-  /* This reloc does nothing.  */
-  HOWTO (R_ARC_NONE,           /* Type.  */
-        0,                     /* Rightshift.  */
-        3,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-        0,                     /* Bitsize.  */
-        FALSE,                 /* PC_relative.  */
-        0,                     /* Bitpos.  */
-        complain_overflow_bitfield, /* Complain_on_overflow.  */
-        bfd_elf_generic_reloc, /* Special_function.  */
-        "R_ARC_NONE",          /* Name.  */
-        TRUE,                  /* Partial_inplace.  */
-        0,                     /* Src_mask.  */
-        0,                     /* Dst_mask.  */
-        FALSE),                /* PCrel_offset.  */
-
-  /* A standard 32 bit relocation.  */
-  HOWTO (R_ARC_32,             /* Type.  */
-        0,                     /* Rightshift.  */
-        2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-        32,                    /* Bitsize.  */
-        FALSE,                 /* PC_relative.  */
-        0,                     /* Bitpos.  */
-        complain_overflow_bitfield, /* Complain_on_overflow.  */
-        bfd_elf_generic_reloc, /* Special_function.  */
-        "R_ARC_32",            /* Name.  */
-        TRUE,                  /* Partial_inplace.  */
-        0xffffffff,            /* Src_mask.  */
-        0xffffffff,            /* Dst_mask.  */
-        FALSE),                /* PCrel_offset.  */
-
-  /* A 26 bit absolute branch, right shifted by 2.  */
-  HOWTO (R_ARC_B26,            /* Type.  */
-        2,                     /* Rightshift.  */
-        2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-        26,                    /* Bitsize.  */
-        FALSE,                 /* PC_relative.  */
-        0,                     /* Bitpos.  */
-        complain_overflow_bitfield, /* Complain_on_overflow.  */
-        bfd_elf_generic_reloc, /* Special_function.  */
-        "R_ARC_B26",           /* Name.  */
-        TRUE,                  /* Partial_inplace.  */
-        0x00ffffff,            /* Src_mask.  */
-        0x00ffffff,            /* Dst_mask.  */
-        FALSE),                /* PCrel_offset.  */
-
-  /* A relative 22 bit branch; bits 21-2 are stored in bits 26-7.  */
-  HOWTO (R_ARC_B22_PCREL,      /* Type.  */
-        2,                     /* Rightshift.  */
-        2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-        22,                    /* Bitsize.  */
-        TRUE,                  /* PC_relative.  */
-        7,                     /* Bitpos.  */
-        complain_overflow_signed, /* Complain_on_overflow.  */
-        arc_elf_b22_pcrel,     /* Special_function.  */
-        "R_ARC_B22_PCREL",     /* Name.  */
-        TRUE,                  /* Partial_inplace.  */
-        0x07ffff80,            /* Src_mask.  */
-        0x07ffff80,            /* Dst_mask.  */
-        FALSE),                /* PCrel_offset.  */
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  [TYPE] = VALUE,
+const int howto_table_lookup[] =
+{
+  #include "elf/arc-reloc.def"
 };
+#undef ARC_RELOC_HOWTO
+
+#define ARC_ELF_HOWTO(r_type) \
+  (&elf_arc_howto_table[r_type])
 
 /* Map BFD reloc types to ARC ELF reloc types.  */
 
 struct arc_reloc_map
 {
   bfd_reloc_code_real_type bfd_reloc_val;
-  unsigned char elf_reloc_val;
+  unsigned char   elf_reloc_val;
 };
 
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  { BFD_RELOC_##TYPE, R_##TYPE },
 static const struct arc_reloc_map arc_reloc_map[] =
 {
-  { BFD_RELOC_NONE, R_ARC_NONE, },
-  { BFD_RELOC_32, R_ARC_32 },
-  { BFD_RELOC_CTOR, R_ARC_32 },
-  { BFD_RELOC_ARC_B26, R_ARC_B26 },
-  { BFD_RELOC_ARC_B22_PCREL, R_ARC_B22_PCREL },
+  #include "elf/arc-reloc.def"
+  {BFD_RELOC_NONE,  R_ARC_NONE},
+  {BFD_RELOC_8,  R_ARC_8},
+  {BFD_RELOC_16, R_ARC_16},
+  {BFD_RELOC_24, R_ARC_24},
+  {BFD_RELOC_32, R_ARC_32},
 };
+#undef ARC_RELOC_HOWTO
 
 static reloc_howto_type *
-bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
                                 bfd_reloc_code_real_type code)
 {
   unsigned int i;
+  static int fully_initialized = FALSE;
+
+  if (fully_initialized == FALSE)
+    {
+      arc_elf_howto_init ();
+      fully_initialized = TRUE; /* TODO: CHECK THIS IF IT STOPS WORKING.  */
+    }
 
   for (i = ARRAY_SIZE (arc_reloc_map); i--;)
-    if (arc_reloc_map[i].bfd_reloc_val == code)
-      return elf_arc_howto_table + arc_reloc_map[i].elf_reloc_val;
+    {
+      if (arc_reloc_map[i].bfd_reloc_val == code)
+       return elf_arc_howto_table + arc_reloc_map[i].elf_reloc_val;
+    }
 
   return NULL;
 }
 
 static reloc_howto_type *
-bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-                                const char *r_name)
+bfd_elf32_bfd_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char *r_name)
 {
   unsigned int i;
 
-  for (i = 0;
-       i < sizeof (elf_arc_howto_table) / sizeof (elf_arc_howto_table[0]);
-       i++)
+  for (i = 0; i < ARRAY_SIZE (elf_arc_howto_table); i++)
     if (elf_arc_howto_table[i].name != NULL
        && strcasecmp (elf_arc_howto_table[i].name, r_name) == 0)
-      return &elf_arc_howto_table[i];
+      return elf_arc_howto_table + i;
 
   return NULL;
 }
 
-/* Set the howto pointer for an ARC ELF reloc.  */
 
+/* Set the howto pointer for an ARC ELF reloc.  */
 static void
-arc_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
-                      arelent *cache_ptr,
-                      Elf_Internal_Rela *dst)
+arc_info_to_howto_rel (bfd * abfd ATTRIBUTE_UNUSED,
+                      arelent * cache_ptr,
+                      Elf_Internal_Rela * dst)
 {
   unsigned int r_type;
 
   r_type = ELF32_R_TYPE (dst->r_info);
-  if (r_type >= (unsigned int) R_ARC_max)
-    {
-      _bfd_error_handler (_("%B: invalid ARC reloc number: %d"), abfd, r_type);
-      r_type = 0;
-    }
+  BFD_ASSERT (r_type < (unsigned int) R_ARC_max);
   cache_ptr->howto = &elf_arc_howto_table[r_type];
 }
 
 /* Set the right machine number for an ARC ELF file.  */
-
 static bfd_boolean
-arc_elf_object_p (bfd *abfd)
+arc_elf_object_p (bfd * abfd)
 {
-  unsigned int mach = bfd_mach_arc_6;
+  /* Make sure this is initialised, or you'll have the potential of passing
+     garbage---or misleading values---into the call to
+     bfd_default_set_arch_mach ().  */
+  int            mach = bfd_mach_arc_arc700;
+  unsigned long   arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK;
+  unsigned       e_machine = elf_elfheader (abfd)->e_machine;
 
-  if (elf_elfheader(abfd)->e_machine == EM_ARC)
+  if (e_machine == EM_ARC_COMPACT || e_machine == EM_ARC_COMPACT2)
     {
-      unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
-
       switch (arch)
        {
-       case E_ARC_MACH_ARC5:
-         mach = bfd_mach_arc_5;
-         break;
-       default:
-       case E_ARC_MACH_ARC6:
-         mach = bfd_mach_arc_6;
-         break;
-       case E_ARC_MACH_ARC7:
-         mach = bfd_mach_arc_7;
-         break;
-       case E_ARC_MACH_ARC8:
-         mach = bfd_mach_arc_8;
-         break;
+         case E_ARC_MACH_ARC600:
+           mach = bfd_mach_arc_arc600;
+           break;
+         case E_ARC_MACH_ARC601:
+           mach = bfd_mach_arc_arc601;
+           break;
+         case E_ARC_MACH_ARC700:
+           mach = bfd_mach_arc_arc700;
+           break;
+         case EF_ARC_CPU_ARCV2HS:
+         case EF_ARC_CPU_ARCV2EM:
+           mach = bfd_mach_arc_arcv2;
+           break;
+         default:
+           mach = (e_machine == EM_ARC_COMPACT) ?
+             bfd_mach_arc_arc700 : bfd_mach_arc_arcv2;
+           break;
+       }
+    }
+  else
+    {
+      if (e_machine == EM_ARC)
+       {
+         (*_bfd_error_handler)
+           (_("Error: The ARC4 architecture is no longer supported.\n"));
+         return FALSE;
+       }
+      else
+       {
+         (*_bfd_error_handler)
+           (_("Warning: unset or old architecture flags. \n"
+              "               Use default machine.\n"));
        }
     }
+
   return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
 }
 
@@ -215,42 +374,1323 @@ arc_elf_object_p (bfd *abfd)
    This gets the ARC architecture right based on the machine number.  */
 
 static void
-arc_elf_final_write_processing (bfd *abfd,
-                               bfd_boolean linker ATTRIBUTE_UNUSED)
+arc_elf_final_write_processing (bfd * abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
 {
   unsigned long val;
+  unsigned long emf;
 
   switch (bfd_get_mach (abfd))
     {
-    case bfd_mach_arc_5:
-      val = E_ARC_MACH_ARC5;
+    case bfd_mach_arc_arc600:
+      val = E_ARC_MACH_ARC600;
+      emf = EM_ARC_COMPACT;
       break;
-    default:
-    case bfd_mach_arc_6:
-      val = E_ARC_MACH_ARC6;
+    case bfd_mach_arc_arc601:
+      val = E_ARC_MACH_ARC601;
+      emf = EM_ARC_COMPACT;
       break;
-    case bfd_mach_arc_7:
-      val = E_ARC_MACH_ARC7;
+    case bfd_mach_arc_arc700:
+      val = E_ARC_MACH_ARC700;
+      emf = EM_ARC_COMPACT;
       break;
-    case bfd_mach_arc_8:
-      val = E_ARC_MACH_ARC8;
+    case bfd_mach_arc_arcv2:
+      val = EF_ARC_CPU_GENERIC;
+      emf = EM_ARC_COMPACT2;
+      /* TODO: Check validity of this.  It can also be ARCV2EM here.
+        Previous version sets the e_machine here.  */
       break;
+    default:
+      abort ();
     }
-  elf_elfheader (abfd)->e_flags &=~ EF_ARC_MACH;
+  elf_elfheader (abfd)->e_flags &= ~EF_ARC_MACH;
   elf_elfheader (abfd)->e_flags |= val;
+  elf_elfheader (abfd)->e_machine = emf;
+
+  /* Record whatever is the current syscall ABI version.  */
+  elf_elfheader (abfd)->e_flags |= E_ARC_OSABI_CURRENT;
 }
 
+#define BFD_DEBUG_PIC(...)
+
+struct arc_relocation_data
+{
+  bfd_vma        reloc_offset;
+  bfd_vma        reloc_addend;
+  bfd_vma        got_offset_value;
+
+  bfd_vma        sym_value;
+  asection *     sym_section;
+
+  reloc_howto_type *howto;
+
+  asection *     input_section;
+
+  bfd_vma        sdata_begin_symbol_vma;
+  bfd_boolean    sdata_begin_symbol_vma_set;
+  bfd_vma        got_symbol_vma;
+
+  bfd_boolean    should_relocate;
+};
+
+static void
+debug_arc_reloc (struct arc_relocation_data reloc_data)
+{
+  fprintf (stderr, "Reloc type=%s, should_relocate = %s\n",
+          reloc_data.howto->name,
+          reloc_data.should_relocate ? "true" : "false");
+  fprintf (stderr, "  offset = 0x%x, addend = 0x%x\n",
+          (unsigned int) reloc_data.reloc_offset,
+          (unsigned int) reloc_data.reloc_addend);
+  fprintf (stderr, " Symbol:\n");
+  fprintf (stderr, "  value = 0x%08x\n",
+          (unsigned int) reloc_data.sym_value);
+  if (reloc_data.sym_section != NULL)
+    {
+      fprintf (stderr, "IN IF\n");
+      fprintf (stderr,
+              "  section name = %s, output_offset 0x%08x, output_section->vma = 0x%08x\n",
+              reloc_data.sym_section->name,
+              (unsigned int) reloc_data.sym_section->output_offset,
+              (unsigned int) reloc_data.sym_section->output_section->vma);
+    }
+  else
+    fprintf (stderr, " symbol section is NULL\n");
+
+  fprintf (stderr, " Input_section:\n");
+  if (reloc_data.input_section != NULL)
+    {
+      fprintf (stderr,
+              "  section name = %s, output_offset 0x%08x, output_section->vma = 0x%08x\n",
+              reloc_data.input_section->name,
+              (unsigned int) reloc_data.input_section->output_offset,
+              (unsigned int) reloc_data.input_section->output_section->vma);
+      fprintf (stderr, "  changed_address = 0x%08x\n",
+              (unsigned int) (reloc_data.input_section->output_section->vma +
+              reloc_data.input_section->output_offset +
+              reloc_data.reloc_offset));
+    }
+  else
+    fprintf (stderr, " input section is NULL\n");
+}
+
+#define S (reloc_data.sym_value \
+          + reloc_data.sym_section->output_offset \
+          + reloc_data.sym_section->output_section->vma)
+#define A (reloc_data.reloc_addend)
+#define B (0)
+#define G (reloc_data.got_offset_value)
+#define GOT (reloc_data.got_symbol_vma + 12)
+#define L (reloc_data.sym_value \
+          + reloc_data.sym_section->output_section->vma \
+          + reloc_data.sym_section->output_offset)
+#define MES (0)
+       /* P: relative offset to PCL The offset should be to the current location
+          aligned to 32 bits.  */
+#define P ( \
+           (reloc_data.input_section->output_section->vma \
+            + reloc_data.input_section->output_offset \
+            + (reloc_data.reloc_offset - (bitsize >= 32 ? 4 : 0)) \
+           ) & ~0x3)
+#define SECTSTAR (reloc_data.input_section->output_offset)
+#define SECTSTART (reloc_data.input_section->output_offset)
+#define _SDA_BASE_ (reloc_data.sdata_begin_symbol_vma)
+
+#define none (0)
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  case R_##TYPE: \
+    { \
+      bfd_vma bitsize ATTRIBUTE_UNUSED = BITSIZE; \
+      relocation = FORMULA  ; \
+      insn = RELOC_FUNCTION (insn, relocation); \
+    } \
+    break;
+
+static bfd_reloc_status_type
+arc_do_relocation (bfd_byte * contents, struct arc_relocation_data reloc_data)
+{
+  bfd_vma relocation = 0;
+  bfd_vma insn;
+  bfd_vma orig_insn ATTRIBUTE_UNUSED;
+
+  if (reloc_data.should_relocate == FALSE)
+    return bfd_reloc_notsupported;
+
+  switch (reloc_data.howto->size)
+    {
+      case 2:
+       insn = arc_bfd_get_32 (reloc_data.input_section->owner,
+                              contents + reloc_data.reloc_offset,
+                              reloc_data.input_section);
+       break;
+      case 1:
+      case 0:
+       insn = arc_bfd_get_16 (reloc_data.input_section->owner,
+                              contents + reloc_data.reloc_offset,
+                              reloc_data.input_section);
+       break;
+      default:
+       insn = 0;
+       BFD_ASSERT (0);
+       break;
+    }
+
+  orig_insn = insn;
+
+  switch (reloc_data.howto->type)
+    {
+      #include "elf/arc-reloc.def"
+
+      default:
+       BFD_ASSERT (0);
+       break;
+    }
+
+  /* Check for relocation overflow.  */
+  if (reloc_data.howto->complain_on_overflow != complain_overflow_dont)
+    {
+      bfd_reloc_status_type flag;
+      flag = bfd_check_overflow (reloc_data.howto->complain_on_overflow,
+                                reloc_data.howto->bitsize,
+                                reloc_data.howto->rightshift,
+                                bfd_arch_bits_per_address (reloc_data.input_section->owner),
+                                relocation);
+
+#undef DEBUG_ARC_RELOC
+#define DEBUG_ARC_RELOC(A) debug_arc_reloc (A)
+      if (flag != bfd_reloc_ok)
+       {
+         fprintf (stderr, "Relocation overflows !!!!\n");
+
+         DEBUG_ARC_RELOC (reloc_data);
+
+         fprintf (stderr,
+                 "Relocation value = signed -> %d, unsigned -> %u, hex -> (0x%08x)\n",
+                 (int) relocation,
+                 (unsigned int) relocation,
+                 (unsigned int) relocation);
+         return flag;
+       }
+    }
+#undef DEBUG_ARC_RELOC
+#define DEBUG_ARC_RELOC(A)
+
+  switch (reloc_data.howto->size)
+    {
+      case 2:
+       arc_bfd_put_32 (reloc_data.input_section->owner, insn,
+                      contents + reloc_data.reloc_offset,
+                      reloc_data.input_section);
+       break;
+      case 1:
+      case 0:
+       arc_bfd_put_16 (reloc_data.input_section->owner, insn,
+                      contents + reloc_data.reloc_offset,
+                      reloc_data.input_section);
+       break;
+      default:
+       ARC_DEBUG ("size = %d\n", reloc_data.howto->size);
+       BFD_ASSERT (0);
+       break;
+    }
+
+  return bfd_reloc_ok;
+}
+#undef S
+#undef A
+#undef B
+#undef G
+#undef GOT
+#undef L
+#undef MES
+#undef P
+#undef SECTSTAR
+#undef SECTSTART
+#undef _SDA_BASE_
+#undef none
+
+#undef ARC_RELOC_HOWTO
+
+static bfd_vma *
+arc_get_local_got_offsets (bfd * abfd)
+{
+  static bfd_vma *local_got_offsets = NULL;
+
+  if (local_got_offsets == NULL)
+    {
+      size_t      size;
+      unsigned int i;
+      Elf_Internal_Shdr *symtab_hdr = &((elf_tdata (abfd))->symtab_hdr);
+
+      size = symtab_hdr->sh_info * sizeof (bfd_vma);
+      local_got_offsets = (bfd_vma *) bfd_alloc (abfd, size);
+      if (local_got_offsets == NULL)
+       return FALSE;
+      elf_local_got_offsets (abfd) = local_got_offsets;
+      for (i = 0; i < symtab_hdr->sh_info; i++)
+       local_got_offsets[i] = (bfd_vma) - 1;
+    }
+
+  return local_got_offsets;
+}
+
+
+/* Relocate an arc ELF section.
+   Function : elf_arc_relocate_section
+   Brief    : Relocate an arc section, by handling all the relocations
+            appearing in that section.
+   Args     : output_bfd    : The bfd being written to.
+             info          : Link information.
+             input_bfd     : The input bfd.
+             input_section : The section being relocated.
+             contents      : contents of the section being relocated.
+             relocs        : List of relocations in the section.
+             local_syms    : is a pointer to the swapped in local symbols.
+             local_section : is an array giving the section in the input file
+                             corresponding to the st_shndx field of each
+                             local symbol.  */
+static bfd_boolean
+elf_arc_relocate_section (bfd *                   output_bfd,
+                         struct bfd_link_info *  info,
+                         bfd *                   input_bfd,
+                         asection *              input_section,
+                         bfd_byte *              contents,
+                         Elf_Internal_Rela *     relocs,
+                         Elf_Internal_Sym *      local_syms,
+                         asection **             local_sections)
+{
+  Elf_Internal_Shdr *           symtab_hdr;
+  struct elf_link_hash_entry ** sym_hashes;
+  bfd_vma *                     local_got_offsets;
+  Elf_Internal_Rela *           rel;
+  Elf_Internal_Rela *           relend;
+
+  symtab_hdr = &((elf_tdata (input_bfd))->symtab_hdr);
+  sym_hashes = elf_sym_hashes (input_bfd);
+
+  rel = relocs;
+  relend = relocs + input_section->reloc_count;
+  for (; rel < relend; rel++)
+    {
+      enum elf_arc_reloc_type       r_type;
+      reloc_howto_type *            howto;
+      unsigned long                 r_symndx;
+      struct elf_link_hash_entry *  h;
+      Elf_Internal_Sym *            sym;
+      asection *                    sec;
+
+      struct arc_relocation_data reloc_data =
+      {
+       .reloc_offset = 0,      /* bfd_vma reloc_offset; */
+       .reloc_addend = 0,      /* bfd_vma reloc_addend; */
+       .got_offset_value = 0,  /* bfd_vma got_offset_value; */
+       .sym_value = 0,         /* bfd_vma sym_value; */
+       .sym_section = NULL,    /* asection *sym_section; */
+       .howto = NULL,          /* reloc_howto_type *howto; */
+       .input_section = NULL,  /* asection *input_section; */
+       .sdata_begin_symbol_vma = 0,    /* bfd_vma sdata_begin_symbol_vma; */
+       .sdata_begin_symbol_vma_set = FALSE,    /* bfd_vma sdata_begin_symbol_vma_set; */
+       .got_symbol_vma = 0,    /* bfd_vma got_symbol_vma; */
+       .should_relocate = FALSE        /* bfd_boolean should_relocate; */
+      };
+
+      struct elf_link_hash_entry *h2;
+
+      h2 = elf_link_hash_lookup (elf_hash_table (info), "__SDATA_BEGIN__",
+                                FALSE, FALSE, TRUE);
+
+      if (reloc_data.sdata_begin_symbol_vma_set == FALSE
+           && h2 != NULL && h2->root.type != bfd_link_hash_undefined)
+       {
+         reloc_data.sdata_begin_symbol_vma =
+           (h2->root.u.def.value +
+            h2->root.u.def.section->output_section->vma);
+         reloc_data.sdata_begin_symbol_vma_set = TRUE;
+       }
+
+      h2 = elf_link_hash_lookup (elf_hash_table (info),
+                                "_GLOBAL_OFFSET_TABLE_", FALSE, FALSE,
+                                TRUE);
+      if (h2 != NULL && h2->root.type != bfd_link_hash_undefined)
+       {
+         reloc_data.got_symbol_vma =
+             (h2->root.u.def.value +
+              h2->root.u.def.section->output_section->vma);
+       }
+
+      r_type = ELF32_R_TYPE (rel->r_info);
+
+      if (r_type >= (int) R_ARC_max)
+       {
+         bfd_set_error (bfd_error_bad_value);
+         return FALSE;
+       }
+      howto = &elf_arc_howto_table[r_type];
+
+      reloc_data.input_section = input_section;
+      reloc_data.howto = howto;
+      reloc_data.reloc_offset = rel->r_offset;
+      reloc_data.reloc_addend = rel->r_addend;
+
+      r_symndx = ELF32_R_SYM (rel->r_info);
+
+      /* This is a final link.  */
+      h = NULL;
+      sym = NULL;
+      sec = NULL;
+
+      if (r_symndx < symtab_hdr->sh_info) /* A local symbol.  */
+       {
+         sym = local_syms + r_symndx;
+         sec = local_sections[r_symndx];
+
+         reloc_data.sym_value = sym->st_value;
+         reloc_data.sym_section = sec;
+
+           if (is_reloc_for_GOT (reloc_data.howto))
+             {
+               local_got_offsets = arc_get_local_got_offsets (output_bfd);
+               reloc_data.got_offset_value = local_got_offsets[r_symndx];
+             }
+
+         reloc_data.should_relocate = TRUE;
+       }
+      else /* Global symbol.  */
+       {
+         /* Get the symbol's entry in the symtab.  */
+         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+
+         while (h->root.type == bfd_link_hash_indirect
+                || h->root.type == bfd_link_hash_warning)
+           h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+         BFD_ASSERT ((h->dynindx == -1) >= (h->forced_local != 0));
+         /* If we have encountered a definition for this symbol.  */
+         if (h->root.type == bfd_link_hash_defined
+             || h->root.type == bfd_link_hash_defweak)
+           {
+             reloc_data.sym_value = h->root.u.def.value;
+             reloc_data.sym_section = h->root.u.def.section;
+
+             reloc_data.should_relocate = TRUE;
+
+             if (is_reloc_for_GOT (howto))
+               {
+                 struct dynamic_sections ds =
+                 arc_create_dynamic_sections (output_bfd, info);
+
+                 /* TODO: Change it to use arc_do_relocation with ARC_32
+                    reloc.  */
+                 bfd_vma relocation =
+                   reloc_data.sym_value + reloc_data.reloc_addend
+                   + reloc_data.sym_section->output_offset
+                   + reloc_data.sym_section->output_section->vma;
+
+                 bfd_put_32 (output_bfd, relocation, ds.sgot->contents + h->got.offset);
+
+               }
+           }
+         else if (h->root.type == bfd_link_hash_undefweak)
+           {
+             /* Is weak symbol and has no definition.  */
+             continue;
+           }
+         else
+           {
+             if (is_reloc_for_GOT (howto))
+               {
+                 struct dynamic_sections ds =
+                     arc_create_dynamic_sections (output_bfd, info);
+
+                 reloc_data.sym_value = h->root.u.def.value;
+                 reloc_data.sym_section = ds.sgot;
+
+                 reloc_data.should_relocate = TRUE;
+               }
+             else if (is_reloc_for_PLT (howto))
+               {
+                 struct dynamic_sections ds =
+                   arc_create_dynamic_sections (output_bfd, info);
+
+                 reloc_data.sym_value = h->plt.offset;
+                 reloc_data.sym_section = ds.splt;
+
+                 reloc_data.should_relocate = TRUE;
+               }
+             else if (!(*info->callbacks->undefined_symbol)
+                      (info, h->root.root.string, input_bfd, input_section,
+                       rel->r_offset,!bfd_link_pic (info)))
+               {
+                 return FALSE;
+               }
+           }
+
+         reloc_data.got_offset_value = h->got.offset;
+       }
+
+      if (is_reloc_SDA_relative (howto) && reloc_data.sdata_begin_symbol_vma_set == FALSE)
+       {
+         (*_bfd_error_handler)
+             ("Error: Linker symbol __SDATA_BEGIN__ not found");
+         bfd_set_error (bfd_error_bad_value);
+         return FALSE;
+       }
+
+      DEBUG_ARC_RELOC (reloc_data);
+      if (arc_do_relocation (contents, reloc_data) != bfd_reloc_ok)
+       return FALSE;
+    }
+
+  return TRUE;
+}
+
+static struct dynamic_sections
+arc_create_dynamic_sections (bfd * abfd, struct bfd_link_info *info)
+{
+  static bfd * dynobj = NULL;
+  struct dynamic_sections ds =
+  {
+       .initialized = FALSE,
+       .sgot = NULL,
+       .srelgot = NULL,
+       .sgotplt = NULL,
+       .sdyn = NULL,
+       .splt = NULL,
+       .srelplt = NULL
+  };
+
+  if (dynobj == NULL)
+    {
+      elf_hash_table (info)->dynobj = dynobj = abfd;
+      if (!_bfd_elf_create_got_section (dynobj, info))
+       return ds;
+    }
+  else
+    dynobj = (elf_hash_table (info))->dynobj;
+
+  ds.sgot = bfd_get_section_by_name (dynobj, ".got");
+
+  ds.srelgot = bfd_get_section_by_name (dynobj, ".rela.got");
+  if (ds.srelgot == NULL)
+    {
+      ds.srelgot = bfd_make_section_with_flags (dynobj, ".rela.got",
+                                        SEC_ALLOC
+                                        | SEC_LOAD
+                                        | SEC_HAS_CONTENTS
+                                        | SEC_IN_MEMORY
+                                        | SEC_LINKER_CREATED
+                                        | SEC_READONLY);
+      if (ds.srelgot == NULL
+         || !bfd_set_section_alignment (dynobj, ds.srelgot, 2))
+       return ds;
+    }
+
+  ds.sgotplt = bfd_get_section_by_name (dynobj, ".got.plt");
+
+  ds.sdyn = bfd_get_section_by_name (dynobj, ".dynamic");
+  ds.splt = bfd_get_section_by_name (dynobj, ".plt");
+  ds.srelplt = bfd_get_section_by_name (dynobj, ".rela.plt");
+
+  ds.initialized = TRUE;
+
+  return ds;
+}
+
+#define ADD_SYMBOL_REF_SEC_AND_RELOC(SECNAME, COND_FOR_RELOC, H) \
+  ds.s##SECNAME->size; \
+  { \
+    if (COND_FOR_RELOC) ds.srel##SECNAME->size += sizeof (Elf32_External_Rela); \
+    if (H)  \
+      if (h->dynindx == -1 && !h->forced_local) \
+       if (! bfd_elf_link_record_dynamic_symbol (info, H)) \
+         return FALSE; \
+    ds.s##SECNAME->size += 4; \
+  }
+
+static bfd_boolean
+elf_arc_check_relocs (bfd *                      abfd,
+                     struct bfd_link_info *     info,
+                     asection *                 sec,
+                     const Elf_Internal_Rela *  relocs)
+{
+  Elf_Internal_Shdr *            symtab_hdr;
+  struct elf_link_hash_entry **  sym_hashes;
+  bfd_vma *                      local_got_offsets;
+  const Elf_Internal_Rela *      rel;
+  const Elf_Internal_Rela *      rel_end;
+  bfd *                          dynobj ATTRIBUTE_UNUSED;
+
+  dynobj = (elf_hash_table (info))->dynobj;
+  symtab_hdr = &((elf_tdata (abfd))->symtab_hdr);
+  sym_hashes = elf_sym_hashes (abfd);
+  local_got_offsets = arc_get_local_got_offsets (abfd);
+
+  struct dynamic_sections ds = arc_create_dynamic_sections (abfd, info);
+
+  rel_end = relocs + sec->reloc_count;
+  for (rel = relocs; rel < rel_end; rel++)
+    {
+      enum elf_arc_reloc_type r_type;
+      reloc_howto_type *howto;
+      unsigned long   r_symndx;
+      struct elf_link_hash_entry *h;
+
+      r_type = ELF32_R_TYPE (rel->r_info);
+
+      if (r_type >= (int) R_ARC_max)
+       {
+         bfd_set_error (bfd_error_bad_value);
+         return FALSE;
+       }
+      howto = &elf_arc_howto_table[r_type];
+
+      /* Load symbol information.  */
+      r_symndx = ELF32_R_SYM (rel->r_info);
+      if (r_symndx < symtab_hdr->sh_info) /* Is a local symbol.  */
+       h = NULL;
+      else /* Global one.  */
+       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+
+      if (is_reloc_for_PLT (howto) == TRUE)
+       {
+         if (h == NULL)
+           continue;
+         else
+           h->needs_plt = 1;
+       }
+
+      if (is_reloc_for_GOT (howto) == TRUE)
+       {
+         if (h == NULL)
+           {
+             /* Local symbol.  */
+             local_got_offsets[r_symndx] =
+               ADD_SYMBOL_REF_SEC_AND_RELOC (got, bfd_link_pic (info), NULL);
+           }
+         else
+           {
+             /* Global symbol.  */
+             h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+             h->got.offset =
+               ADD_SYMBOL_REF_SEC_AND_RELOC (got, TRUE, h);
+           }
+       }
+    }
+
+  return TRUE;
+}
+
+#define ELF_DYNAMIC_INTERPRETER  "/sbin/ld-uClibc.so"
+
+/* Size of one plt entry in bytes.  */
+#define PLT_ENTRY_SIZE 12
+#define PLT_ENTRY_SIZE_V2 16
+
+/* Instructions appear in memory as a sequence of half-words (16 bit);
+   individual half-words are represented on the target in target byte order.
+   We use 'unsigned short' on the host to represent the PLT templates,
+   and translate to target byte order as we copy to the target.  */
+typedef unsigned short insn_hword;
+
+
+/* TODO: Make this PLT entry code be in a separate object file.  */
+/* TODO: This is a linker BTW, we should be able to link. :)  */
+
+/* The zeroth entry in the absolute plt entry.  */
+static const insn_hword elf_arc_abs_plt0_entry[2 * PLT_ENTRY_SIZE / 2] =
+{
+  0x1600,      /* ld %r11, [0] */
+  0x700b,
+  0x0000,
+  0x0000,
+  0x1600,      /* ld %r10, [0] */
+  0x700a,      /* */
+  0,
+  0,
+  0x2020,      /* j [%r10] */
+  0x0280,      /* ---"---- */
+  0x0000,      /* pad */
+  0x0000       /* pad */
+};
+
+/* Contents of the subsequent entries in the absolute plt.  */
+static const insn_hword elf_arc_abs_pltn_entry[PLT_ENTRY_SIZE / 2] =
+{
+  0x2730,      /* ld %r12, [%pc,func@gotpc] */
+  0x7f8c,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x7c20,      /* j_s.d [%r12] */
+  0x74ef       /* mov_s %r12, %pcl */
+};
+
+/* The zeroth entry in the absolute plt entry for ARCv2.  */
+static const insn_hword elf_arcV2_abs_plt0_entry[2 * PLT_ENTRY_SIZE_V2 / 2] =
+{
+  0x1600, 0x700b, 0, 0,   /* ld %r11, [0] */
+  0x1600, 0x700a, 0, 0,   /* ld %r10, [0] */
+  0x2020, 0x0280,        /* j [%r10] */
+  0x0000, 0x0000,        /* -> RELOCATED TO ABS ADDRESS OF GOT <- */
+  0x0000,                /* pad */
+  0x0000,                /* pad */
+  0x0000,                /* pad */
+  0x0000                 /* pad */
+};
+
+/* Contents of the subsequent entries in the absolute plt for ARCv2.  */
+static const insn_hword elf_arcV2_abs_pltn_entry[PLT_ENTRY_SIZE_V2 / 2] =
+{
+  0x2730,      /* ld %r12, [%pcl,func@gotpc] */
+  0x7f8c,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x2021,      /* j.d [%r12] */
+  0x0300,      /* ------ " " -------------- */
+  0x240a,      /* mov %r12, %pcl */
+  0x1fc0       /* ------ " " -------------- */
+};
+
+/* The zeroth entry in the pic plt entry.  */
+static const insn_hword elf_arc_pic_plt0_entry[2 * PLT_ENTRY_SIZE / 2] =
+{
+  0x2730,      /* ld %r11, [pcl,0] : 0 to be replaced by
+                  _DYNAMIC@GOTPC+4 */
+  0x7f8b,
+  0x0000,
+  0x0000,
+  0x2730,      /* ld %r10, [pcl,0] : 0 to be replaced by
+                  -DYNAMIC@GOTPC+8 */
+  0x7f8a,      /* */
+  0,
+  0,
+  0x2020,      /* j [%r10] */
+  0x0280,      /* ---"---- */
+  0x0000,      /* pad */
+  0x0000       /* pad */
+};
+
+/* Contents of the subsequent entries in the pic plt.  */
+static const insn_hword elf_arc_pic_pltn_entry[PLT_ENTRY_SIZE / 2] =
+{
+  0x2730,      /* ld %r12, [%pc,func@got] */
+  0x7f8c,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x7c20,      /* j_s.d [%r12] */
+  0x74ef,      /* mov_s %r12, %pcl */
+};
+
+/* The zeroth entry in the pic plt entry for ARCv2.  */
+static const insn_hword elf_arcV2_pic_plt0_entry[2 * PLT_ENTRY_SIZE_V2 / 2] =
+{
+  0x2730,      /* ld %r11, [pcl,0] : 0 to be replaced by
+                  _DYNAMIC@GOTPC+4 */
+  0x7f8b,
+  0x0000,
+  0x0000,
+  0x2730,      /* ld %r10, [pcl,0] : 0 to be replaced by
+                  -DYNAMIC@GOTPC+8 */
+  0x7f8a,      /* */
+  0,
+  0,
+  0x2020,      /* j [%r10] */
+  0x0280,      /* ---"---- */
+  0x0000,      /* pad */
+  0x0000,      /* pad */
+  0x0000,      /* pad */
+  0x0000,      /* pad */
+  0x0000,      /* pad */
+  0x0000       /* pad */
+};
+
+#define elf_arcV2_pic_PLT0_ENTRY_SIZE (2 * PLT_ENTRY_SIZE_V2/2)
+
+/* Contents of the subsequent entries in the pic plt for ARCv2.  */
+static const insn_hword elf_arcV2_pic_pltn_entry[PLT_ENTRY_SIZE_V2 / 2] =
+{
+  0x2730,      /* ld %r12, [%pc,func@got] */
+  0x7f8c,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x0000,      /* ------ " " -------------- */
+  0x2021,      /* j.d [%r12] */
+  0x0300,      /* ------ " " -------------- */
+  0x240a,      /* mov %r12, %pcl */
+  0x1fc0       /* ------ " " -------------- */
+};
+
+#define elf_arcV2_pic_PLTN_ENTRY_SIZE (PLT_ENTRY_SIZE_V2/2)
+
+enum plt_reloc_symbol
+{
+  LAST_RELOC = 0,
+
+  SGOT = 1,
+
+  RELATIVE = (1 << 8),
+  MIDDLE_ENDIAN = (1 << 9)
+};
+
+#define IS_RELATIVE(S) ((S & RELATIVE) != 0)
+#define IS_MIDDLE_ENDIAN(S) ((S & MIDDLE_ENDIAN) != 0)
+#define SYM_ONLY(S) (S & 0xFF)
+
+struct plt_reloc
+{
+  bfd_vma        offset;
+  bfd_vma        size;
+  bfd_vma        mask;
+  enum plt_reloc_symbol symbol;
+  bfd_vma        addend;
+};
+
+struct plt_version_t
+{
+  const insn_hword *    entry;
+  const bfd_vma                entry_size;
+  const insn_hword *    elem;
+  const bfd_vma                elem_size;
+
+  struct plt_reloc entry_relocs[5];
+  struct plt_reloc elem_relocs[5];
+};
+
+
+#define PLT_DATA(NAME, ...) \
+  .entry = NAME##_plt0_entry, \
+  .entry_size = NAME##_PLT0_ENTRY_SIZE, \
+  .elem = NAME##_pltn_entry, \
+  .elem_size = NAME##_PLTN_ENTRY_SIZE
+
+struct plt_version_t plt_versions[] =
+{
+  {
+    PLT_DATA (elf_arcV2_pic),
+    .entry_relocs =
+    {
+      {4, 32, 0xFFFFFFFF, SGOT | RELATIVE | MIDDLE_ENDIAN, 4},
+      {12, 32, 0xFFFFFFFF, SGOT | RELATIVE | MIDDLE_ENDIAN, 8},
+      {20, 32, 0xFFFFFFFF, SGOT, 0},
+      {0, 0, 0, LAST_RELOC, 0}
+    },
+    .elem_relocs =
+    {
+      {4, 32, 0xFFFFFFFF, SGOT, 0},
+      {0, 0, 0, LAST_RELOC, 0}
+    }
+  }
+};
+#undef PLT_DATA
+
+static struct plt_version_t *
+arc_get_plt_version (void)
+{
+  return &(plt_versions[0]);
+}
+
+static bfd_vma
+add_symbol_to_plt (struct bfd_link_info *info)
+{
+  bfd *dynobj = (elf_hash_table (info))->dynobj;
+  struct dynamic_sections ds = arc_create_dynamic_sections (dynobj, info);
+  bfd_vma ret;
+
+  /* If this is the first .plt entry, make room for the special first entry.  */
+  if (ds.splt->size == 0)
+    ds.splt->size += 2 *
+                    (bfd_get_mach (dynobj) == bfd_mach_arc_arcv2
+                     ? PLT_ENTRY_SIZE_V2 : PLT_ENTRY_SIZE);
+
+  ret = ds.splt->size;
+
+  ds.splt->size += (bfd_get_mach (dynobj) == bfd_mach_arc_arcv2
+                   ? PLT_ENTRY_SIZE_V2
+                   : PLT_ENTRY_SIZE
+                  );
+  ds.sgotplt->size += 4;
+  ds.srelplt->size += sizeof (Elf32_External_Rela);
+
+  return ret;
+}
+
+#define PLT_DO_RELOCS_FOR_ENTRY(DS, RELOCS) \
+  plt_do_relocs_for_symbol (DS, RELOCS, 0, 0)
+
+static void
+plt_do_relocs_for_symbol (struct dynamic_sections *ds,
+                         struct plt_reloc *reloc,
+                         bfd_vma plt_offset,
+                         bfd_vma symbol_got_offset)
+{
+  while (SYM_ONLY (reloc->symbol) != LAST_RELOC)
+    {
+      bfd_vma relocation = 0;
+
+      switch (SYM_ONLY (reloc->symbol))
+       {
+         case SGOT:
+               relocation =
+                   ds->sgotplt->output_section->vma +
+                   ds->sgotplt->output_offset + symbol_got_offset;
+               break;
+       }
+      relocation += reloc->addend;
+
+      relocation -= (IS_RELATIVE (reloc->symbol))
+         ? ds->splt->output_section->vma + ds->splt->output_offset +
+         plt_offset + reloc->offset : 0;
+
+      if (IS_MIDDLE_ENDIAN (reloc->symbol))
+       {
+         relocation =
+             ((relocation & 0xffff0000) >> 16) |
+             ((relocation & 0xffff) << 16);
+       }
+
+      switch (reloc->size)
+       {
+         case 32:
+           bfd_put_32 (ds->splt->output_section->owner,
+                       relocation,
+                       ds->splt->contents + plt_offset + reloc->offset);
+           break;
+       }
+
+      reloc = &(reloc[1]);     /* Jump to next relocation.  */
+    }
+}
+
+static void
+relocate_plt_for_symbol (struct bfd_link_info *info,
+                        struct elf_link_hash_entry *h)
+{
+  bfd * dynobj = elf_hash_table (info)->dynobj;
+  struct plt_version_t *plt_data = arc_get_plt_version ();
+  struct dynamic_sections ds = arc_create_dynamic_sections (dynobj, info);
+
+  bfd_vma plt_index = h->plt.offset / plt_data->elem_size;
+  bfd_vma got_offset = (plt_index + 3) * 4;
+
+  memcpy (ds.splt->contents + h->plt.offset, plt_data->elem,
+         plt_data->elem_size * sizeof (insn_hword));
+  plt_do_relocs_for_symbol (&ds, plt_data->elem_relocs, h->plt.offset,
+                           got_offset);
+}
+
+static void
+relocate_plt_for_entry (struct bfd_link_info *info)
+{
+  bfd * dynobj = (elf_hash_table (info))->dynobj;
+  struct plt_version_t *plt_data = arc_get_plt_version ();
+  struct dynamic_sections ds = arc_create_dynamic_sections (dynobj, info);
+
+  memcpy (ds.splt->contents, plt_data->entry,
+         plt_data->entry_size * sizeof (insn_hword));
+  PLT_DO_RELOCS_FOR_ENTRY (&ds, plt_data->entry_relocs);
+}
+
+
+/* Desc : Adjust a symbol defined by a dynamic object and referenced by a
+   regular object.  The current definition is in some section of the
+   dynamic object, but we're not including those sections.  We have to
+   change the definition to something the rest of the link can
+   understand.  */
+
+static bfd_boolean
+elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info,
+                             struct elf_link_hash_entry *h)
+{
+  bfd *dynobj = (elf_hash_table (info))->dynobj;
+  struct dynamic_sections ds = arc_create_dynamic_sections (dynobj, info);
+
+  if (h->needs_plt == 1)
+    {
+      if (!bfd_link_pic (info) && !h->def_dynamic && !h->ref_dynamic)
+       {
+         /* This case can occur if we saw a PLT32 reloc in an input
+            file, but the symbol was never referred to by a dynamic
+            object.  In such a case, we don't actually need to build
+            a procedure linkage table, and we can just do a PC32
+            reloc instead.  */
+         BFD_ASSERT (h->needs_plt);
+         return TRUE;
+       }
+
+      /* Make sure this symbol is output as a dynamic symbol.  */
+      if (h->dynindx == -1 && !h->forced_local
+         && !bfd_elf_link_record_dynamic_symbol (info, h))
+       return FALSE;
+
+      if (bfd_link_pic (info) || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
+       {
+         bfd_vma loc = add_symbol_to_plt (info);
+
+         if (!bfd_link_pic (info) && !h->def_regular)
+           {
+             h->root.u.def.section = ds.splt;
+             h->root.u.def.value = loc;
+           }
+         h->plt.offset = loc;
+       }
+    }
+  else
+    {
+      h->plt.offset = (bfd_vma) - 1;
+      h->needs_plt = 0;
+    }
+
+  return TRUE;
+}
+
+#define ADD_RELA(BFD, SECTION, OFFSET, SYM_IDX, TYPE, ADDEND) \
+{\
+  struct dynamic_sections ds = arc_create_dynamic_sections (output_bfd, info); \
+  bfd_byte * rloc = ds.srel##SECTION->contents + \
+    ((ds.srel##SECTION->reloc_count++) * sizeof (Elf32_External_Rela)); \
+  Elf_Internal_Rela rel; \
+  bfd_put_32 (output_bfd, (bfd_vma) 0, ds.s##SECTION->contents + OFFSET); \
+  rel.r_addend = ADDEND; \
+  rel.r_offset = (ds.s##SECTION)->output_section->vma + (ds.s##SECTION)->output_offset + OFFSET; \
+  rel.r_info = ELF32_R_INFO (SYM_IDX, TYPE); \
+  bfd_elf32_swap_reloca_out (BFD, &rel, rloc); \
+}
+
+/* Function :  elf_arc_finish_dynamic_symbol
+   Brief    :  Finish up dynamic symbol handling.  We set the
+            contents of various dynamic sections here.
+   Args     :  output_bfd :
+              info       :
+              h          :
+              sym        :
+   Returns  : True/False as the return status.  */
+static bfd_boolean
+elf_arc_finish_dynamic_symbol (bfd * output_bfd,
+                              struct bfd_link_info *info,
+                              struct elf_link_hash_entry *h,
+                              Elf_Internal_Sym * sym)
+{
+  if (h->plt.offset != (bfd_vma) - 1)
+    relocate_plt_for_symbol (info, h);
+
+  if (h->got.offset != (bfd_vma) - 1)
+    {
+      if (bfd_link_pic (info) && (info->symbolic || h->dynindx == -1)
+         && h->def_regular)
+       {
+         ADD_RELA (output_bfd, got, h->got.offset, 0, R_ARC_RELATIVE, 0);
+       }
+      else
+       {
+         ADD_RELA (output_bfd, got, h->got.offset, h->dynindx,
+                   R_ARC_GLOB_DAT, 0);
+       }
+    }
+
+  /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
+  if (strcmp (h->root.root.string, "_DYNAMIC") == 0
+      || strcmp (h->root.root.string, "__DYNAMIC") == 0
+      || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
+    sym->st_shndx = SHN_ABS;
+
+  return TRUE;
+}
+
+#define GET_SYMBOL_OR_SECTION(TAG, SYMBOL, SECTION) \
+  case TAG: \
+    if (SYMBOL != NULL) \
+      { \
+       h = elf_link_hash_lookup (elf_hash_table (info), SYMBOL, FALSE, FALSE, TRUE); \
+      } \
+    else if (SECTION != NULL) \
+      { \
+       s = bfd_get_section_by_name (output_bfd, SECTION); \
+       BFD_ASSERT (s != NULL); \
+       do_it = TRUE; \
+      } \
+    break;
+
+/* Function :  elf_arc_finish_dynamic_sections
+   Brief    :  Finish up the dynamic sections handling.
+   Args     :  output_bfd :
+              info       :
+              h          :
+              sym        :
+   Returns  : True/False as the return status.  */
+static bfd_boolean
+elf_arc_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info *info)
+{
+  struct dynamic_sections ds = arc_create_dynamic_sections (output_bfd, info);
+  bfd *dynobj = (elf_hash_table (info))->dynobj;
+
+  if (ds.sdyn)
+    {
+      Elf32_External_Dyn *dyncon, *dynconend;
+
+      dyncon = (Elf32_External_Dyn *) ds.sdyn->contents;
+      dynconend =
+         (Elf32_External_Dyn *) (ds.sdyn->contents + ds.sdyn->size);
+      for (; dyncon < dynconend; dyncon++)
+       {
+         Elf_Internal_Dyn internal_dyn;
+         bfd_boolean     do_it = FALSE;
+
+         struct elf_link_hash_entry *h = NULL;
+         asection       *s = NULL;
+
+         bfd_elf32_swap_dyn_in (dynobj, dyncon, &internal_dyn);
+
+         switch (internal_dyn.d_tag)
+           {
+             GET_SYMBOL_OR_SECTION (DT_INIT, "_init", NULL)
+             GET_SYMBOL_OR_SECTION (DT_FINI, "_fini", NULL)
+             GET_SYMBOL_OR_SECTION (DT_PLTGOT, NULL, ".plt")
+             GET_SYMBOL_OR_SECTION (DT_JMPREL, NULL, ".rela.plt")
+             GET_SYMBOL_OR_SECTION (DT_PLTRELSZ, NULL, ".rela.plt")
+             GET_SYMBOL_OR_SECTION (DT_RELASZ, NULL, ".rela.plt")
+             default:
+               break;
+           }
+
+         /* In case the dynamic symbols should be updated with a
+            symbol.  */
+         if (h != NULL
+             && (h->root.type == bfd_link_hash_defined
+                 || h->root.type == bfd_link_hash_defweak)
+             )
+           {
+             asection       *asec_ptr;
+
+             internal_dyn.d_un.d_val = h->root.u.def.value;
+             asec_ptr = h->root.u.def.section;
+             if (asec_ptr->output_section != NULL)
+               {
+                 internal_dyn.d_un.d_val +=
+                   (asec_ptr->output_section->vma +
+                    asec_ptr->output_offset);
+               }
+             else
+               {
+                 /* The symbol is imported from another
+                    shared library and does not apply to this
+                    one.  */
+                 internal_dyn.d_un.d_val = 0;
+               }
+             do_it = TRUE;
+           }
+         else if (s != NULL) /* With a section information.  */
+           {
+             switch (internal_dyn.d_tag)
+               {
+                 case DT_PLTGOT:
+                 case DT_JMPREL:
+                   internal_dyn.d_un.d_ptr = s->vma;
+                   do_it = TRUE;
+                   break;
+
+                 case DT_PLTRELSZ:
+                   internal_dyn.d_un.d_val = s->size;
+                   do_it = TRUE;
+                   break;
+
+                 case DT_RELASZ:
+                   internal_dyn.d_un.d_val -= s->size;
+                   do_it = TRUE;
+                   break;
+
+                 default:
+                   break;
+               }
+           }
+
+         if (do_it == TRUE)
+           bfd_elf32_swap_dyn_out (output_bfd, &internal_dyn, dyncon);
+       }
+
+      if (ds.splt->size > 0)
+       {
+         relocate_plt_for_entry (info);
+       }
+
+      elf_section_data (ds.srelplt->output_section)->this_hdr.sh_entsize = 0xc;
+    }
+
+  /* Fill in the first three entries in the global offset table.  */
+  if (ds.sgot)
+    {
+      if (ds.sgot->size > 0)
+       {
+         if (ds.sdyn == NULL)
+           bfd_put_32 (output_bfd, (bfd_vma) 0,
+                       ds.sgotplt->contents);
+         else
+           bfd_put_32 (output_bfd,
+                       ds.sdyn->output_section->vma + ds.sdyn->output_offset,
+                       ds.sgotplt->contents);
+         bfd_put_32 (output_bfd, (bfd_vma) 0, ds.sgotplt->contents + 4);
+         bfd_put_32 (output_bfd, (bfd_vma) 0, ds.sgotplt->contents + 8);
+
+         elf_section_data (ds.sgot->output_section)->this_hdr.sh_entsize = 4;
+       }
+    }
+
+  if (ds.srelgot
+      /* Check that the linker script has not dumped the .srelgot section.  */
+      && ds.srelgot->output_section
+      && elf_section_data (ds.srelgot->output_section))
+    {
+      /* TODO: Make it work even if I remove this.  */
+      elf_section_data (ds.srelgot->output_section)->this_hdr.sh_entsize = 0xc;
+    }
+
+  return TRUE;
+}
+
+#define ADD_DYNAMIC_SYMBOL(NAME, TAG) \
+  h =  elf_link_hash_lookup (elf_hash_table (info), NAME, FALSE, FALSE, FALSE); \
+  if ((h != NULL && (h->ref_regular || h->def_regular))) \
+    if (! _bfd_elf_add_dynamic_entry (info, TAG, 0)) \
+      return FALSE;
+
+/* Set the sizes of the dynamic sections.  */
+static bfd_boolean
+elf_arc_size_dynamic_sections (bfd * output_bfd, struct bfd_link_info *info)
+{
+  bfd *           dynobj;
+  asection *      s;
+  bfd_boolean    relocs_exist;
+  bfd_boolean    reltext_exist;
+  struct dynamic_sections ds = arc_create_dynamic_sections (output_bfd, info);
+
+  dynobj = (elf_hash_table (info))->dynobj;
+  BFD_ASSERT (dynobj != NULL);
+
+  if ((elf_hash_table (info))->dynamic_sections_created)
+    {
+      struct elf_link_hash_entry *h;
+
+      /* Set the contents of the .interp section to the interpreter.  */
+      if (!bfd_link_pic (info))
+       {
+         s = bfd_get_section_by_name (dynobj, ".interp");
+         BFD_ASSERT (s != NULL);
+         s->size = sizeof ELF_DYNAMIC_INTERPRETER;
+         s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
+       }
+
+      /* Add some entries to the .dynamic section.  We fill in some of the
+         values later, in elf_bfd_final_link, but we must add the entries
+         now so that we know the final size of the .dynamic section.
+         Checking if the .init section is present.  We also create DT_INIT
+         and DT_FINI entries if the init_str has been changed by the user.  */
+
+      ADD_DYNAMIC_SYMBOL ("init", DT_INIT);
+      ADD_DYNAMIC_SYMBOL ("fini", DT_FINI);
+    }
+  else
+    {
+      /* We may have created entries in the .rela.got section.  However, if
+         we are not creating the dynamic sections, we will not actually
+         use these entries.  Reset the size of .rela.got, which will cause
+         it to get stripped from the output file below.  */
+      ds.srelgot->size = 0;
+    }
+
+  for (s = dynobj->sections; s != NULL; s = s->next)
+    {
+       bfd_boolean     is_dynamic_section = FALSE;
+
+       /* Skip any non dynamic section.  */
+       if (strstr (s->name, ".plt") != NULL
+           || strstr (s->name, ".got") != NULL
+         || strstr (s->name, ".rel") != NULL)
+       is_dynamic_section = TRUE;
+
+      /* Allocate memory for the section contents.  */
+      if (!is_dynamic_section)
+       continue;
+
+      s->contents = (bfd_byte *) bfd_alloc (dynobj, s->size);
+      if (s->contents == NULL && s->size != 0)
+         return FALSE;
+
+      if (s->size == 0)
+       {
+         s->flags |= SEC_EXCLUDE;
+         continue;
+       }
+
+      if (strcmp (s->name, ".rela.plt") != 0)
+       {
+         const char *outname = bfd_get_section_name (output_bfd,
+                                                     s->output_section);
+         asection *target = bfd_get_section_by_name (output_bfd,
+                                                     outname + 4);
+
+         relocs_exist = TRUE;
+         if (target != NULL && target->size != 0
+             && (target->flags & SEC_READONLY) != 0
+             && (target->flags & SEC_ALLOC) != 0)
+           reltext_exist = TRUE;
+       }
+    }
+
+  if (ds.sdyn)
+    {
+      if (ds.splt && ds.splt->size != 0)
+       if (!_bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0)
+           || !_bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0)
+           || !_bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_RELA)
+           || !_bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0)
+          )
+         return FALSE;
+
+      if (relocs_exist == TRUE)
+       if (!_bfd_elf_add_dynamic_entry (info, DT_RELA, 0)
+           || !_bfd_elf_add_dynamic_entry (info, DT_RELASZ, 0)
+           || !_bfd_elf_add_dynamic_entry (info, DT_RELENT,
+                                           sizeof (Elf32_External_Rela))
+          )
+         return FALSE;
+
+      if (reltext_exist == TRUE)
+       if (!_bfd_elf_add_dynamic_entry (info, DT_TEXTREL, 0))
+         return FALSE;
+    }
+
+  return TRUE;
+}
+
+
 #define TARGET_LITTLE_SYM   arc_elf32_le_vec
 #define TARGET_LITTLE_NAME  "elf32-littlearc"
-#define TARGET_BIG_SYM      arc_elf32_be_vec
-#define TARGET_BIG_NAME            "elf32-bigarc"
-#define ELF_ARCH            bfd_arch_arc
-#define ELF_MACHINE_CODE    EM_ARC
-#define ELF_MAXPAGESIZE     0x1000
-
-#define elf_info_to_howto                   0
-#define elf_info_to_howto_rel               arc_info_to_howto_rel
-#define elf_backend_object_p                arc_elf_object_p
-#define elf_backend_final_write_processing  arc_elf_final_write_processing
+#define TARGET_BIG_SYM     arc_elf32_be_vec
+#define TARGET_BIG_NAME     "elf32-bigarc"
+#define ELF_ARCH           bfd_arch_arc
+#define ELF_MACHINE_CODE    EM_ARC_COMPACT
+#define ELF_MACHINE_ALT1    EM_ARC_COMPACT2
+#define ELF_MAXPAGESIZE     0x2000
+
+#define elf_info_to_howto_rel               arc_info_to_howto_rel
+#define elf_backend_object_p                arc_elf_object_p
+#define elf_backend_final_write_processing   arc_elf_final_write_processing
+
+#define elf_backend_relocate_section        elf_arc_relocate_section
+#define elf_backend_check_relocs            elf_arc_check_relocs
+#define elf_backend_create_dynamic_sections  _bfd_elf_create_dynamic_sections
+
+#define elf_backend_adjust_dynamic_symbol    elf_arc_adjust_dynamic_symbol
+#define elf_backend_finish_dynamic_symbol    elf_arc_finish_dynamic_symbol
+
+#define elf_backend_finish_dynamic_sections  elf_arc_finish_dynamic_sections
+#define elf_backend_size_dynamic_sections    elf_arc_size_dynamic_sections
+
+#define elf_backend_can_gc_sections    1
+#define elf_backend_want_got_plt       1
+#define elf_backend_plt_readonly       1
+#define elf_backend_want_plt_sym       0
+#define elf_backend_got_header_size    12
+
+#define elf_backend_may_use_rel_p      0
+#define elf_backend_may_use_rela_p     1
+#define elf_backend_default_use_rela_p 1
 
 #include "elf32-target.h"

diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index db0d4f1..3e45461 100644 (file)
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -3468,9 +3468,9 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
                memset (&outrel, 0, sizeof outrel);
              /* h->dynindx may be -1 if the symbol was marked to
                 become local.  */
-             else if (h != NULL &&
-                      h->dynindx != -1
-                      && (! is_plt
+             else if (h != NULL
+                      && h->dynindx != -1
+                      && (_bfd_sparc_elf_howto_table[r_type].pc_relative
                           || !bfd_link_pic (info)
                           || !SYMBOLIC_BIND (info, h)
                           || !h->def_regular))

diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 03bb057..9ae9ba2 100644 (file)
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1663,8 +1663,71 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_SH_GOTOFFFUNCDESC",
   "BFD_RELOC_SH_GOTOFFFUNCDESC20",
   "BFD_RELOC_SH_FUNCDESC",
-  "BFD_RELOC_ARC_B22_PCREL",
-  "BFD_RELOC_ARC_B26",
+  "BFD_RELOC_ARC_NONE",
+  "BFD_RELOC_ARC_8",
+  "BFD_RELOC_ARC_16",
+  "BFD_RELOC_ARC_24",
+  "BFD_RELOC_ARC_32",
+  "BFD_RELOC_ARC_N8",
+  "BFD_RELOC_ARC_N16",
+  "BFD_RELOC_ARC_N24",
+  "BFD_RELOC_ARC_N32",
+  "BFD_RELOC_ARC_SDA",
+  "BFD_RELOC_ARC_SECTOFF",
+  "BFD_RELOC_ARC_S21H_PCREL",
+  "BFD_RELOC_ARC_S21W_PCREL",
+  "BFD_RELOC_ARC_S25H_PCREL",
+  "BFD_RELOC_ARC_S25W_PCREL",
+  "BFD_RELOC_ARC_SDA32",
+  "BFD_RELOC_ARC_SDA_LDST",
+  "BFD_RELOC_ARC_SDA_LDST1",
+  "BFD_RELOC_ARC_SDA_LDST2",
+  "BFD_RELOC_ARC_SDA16_LD",
+  "BFD_RELOC_ARC_SDA16_LD1",
+  "BFD_RELOC_ARC_SDA16_LD2",
+  "BFD_RELOC_ARC_S13_PCREL",
+  "BFD_RELOC_ARC_W",
+  "BFD_RELOC_ARC_32_ME",
+  "BFD_RELOC_ARC_32_ME_S",
+  "BFD_RELOC_ARC_N32_ME",
+  "BFD_RELOC_ARC_SECTOFF_ME",
+  "BFD_RELOC_ARC_SDA32_ME",
+  "BFD_RELOC_ARC_W_ME",
+  "BFD_RELOC_AC_SECTOFF_U8",
+  "BFD_RELOC_AC_SECTOFF_U8_1",
+  "BFD_RELOC_AC_SECTOFF_U8_2",
+  "BFD_RELOC_AC_SECTFOFF_S9",
+  "BFD_RELOC_AC_SECTFOFF_S9_1",
+  "BFD_RELOC_AC_SECTFOFF_S9_2",
+  "BFD_RELOC_ARC_SECTOFF_ME_1",
+  "BFD_RELOC_ARC_SECTOFF_ME_2",
+  "BFD_RELOC_ARC_SECTOFF_1",
+  "BFD_RELOC_ARC_SECTOFF_2",
+  "BFD_RELOC_ARC_SDA16_ST2",
+  "BFD_RELOC_ARC_PC32",
+  "BFD_RELOC_ARC_GOT32",
+  "BFD_RELOC_ARC_GOTPC32",
+  "BFD_RELOC_ARC_PLT32",
+  "BFD_RELOC_ARC_COPY",
+  "BFD_RELOC_ARC_GLOB_DAT",
+  "BFD_RELOC_ARC_JMP_SLOT",
+  "BFD_RELOC_ARC_RELATIVE",
+  "BFD_RELOC_ARC_GOTOFF",
+  "BFD_RELOC_ARC_GOTPC",
+  "BFD_RELOC_ARC_S21W_PCREL_PLT",
+  "BFD_RELOC_ARC_S25H_PCREL_PLT",
+  "BFD_RELOC_ARC_TLS_DTPMOD",
+  "BFD_RELOC_ARC_TLS_TPOFF",
+  "BFD_RELOC_ARC_TLS_GD_GOT",
+  "BFD_RELOC_ARC_TLS_GD_LD",
+  "BFD_RELOC_ARC_TLS_GD_CALL",
+  "BFD_RELOC_ARC_TLS_IE_GOT",
+  "BFD_RELOC_ARC_TLS_DTPOFF",
+  "BFD_RELOC_ARC_TLS_DTPOFF_S9",
+  "BFD_RELOC_ARC_TLS_LE_S9",
+  "BFD_RELOC_ARC_TLS_LE_32",
+  "BFD_RELOC_ARC_S25W_PCREL_PLT",
+  "BFD_RELOC_ARC_S21H_PCREL_PLT",
   "BFD_RELOC_BFIN_16_IMM",
   "BFD_RELOC_BFIN_16_HIGH",
   "BFD_RELOC_BFIN_4_PCREL",

diff --git a/bfd/reloc.c b/bfd/reloc.c
index 18ca7bb..886c63e 100644 (file)
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3515,18 +3515,137 @@ ENUMDOC
   Renesas / SuperH SH relocs.  Not all of these appear in object files.
 
 ENUM
-  BFD_RELOC_ARC_B22_PCREL
-ENUMDOC
-  ARC Cores relocs.
-  ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
-  not stored in the instruction.  The high 20 bits are installed in bits 26
-  through 7 of the instruction.
-ENUM
-  BFD_RELOC_ARC_B26
+  BFD_RELOC_ARC_NONE
+ENUMX
+  BFD_RELOC_ARC_8
+ENUMX
+  BFD_RELOC_ARC_16
+ENUMX
+  BFD_RELOC_ARC_24
+ENUMX
+  BFD_RELOC_ARC_32
+ENUMX
+  BFD_RELOC_ARC_N8
+ENUMX
+  BFD_RELOC_ARC_N16
+ENUMX
+  BFD_RELOC_ARC_N24
+ENUMX
+  BFD_RELOC_ARC_N32
+ENUMX
+  BFD_RELOC_ARC_SDA
+ENUMX
+  BFD_RELOC_ARC_SECTOFF
+ENUMX
+  BFD_RELOC_ARC_S21H_PCREL
+ENUMX
+  BFD_RELOC_ARC_S21W_PCREL
+ENUMX
+  BFD_RELOC_ARC_S25H_PCREL
+ENUMX
+  BFD_RELOC_ARC_S25W_PCREL
+ENUMX
+  BFD_RELOC_ARC_SDA32
+ENUMX
+  BFD_RELOC_ARC_SDA_LDST
+ENUMX
+  BFD_RELOC_ARC_SDA_LDST1
+ENUMX
+  BFD_RELOC_ARC_SDA_LDST2
+ENUMX
+  BFD_RELOC_ARC_SDA16_LD
+ENUMX
+  BFD_RELOC_ARC_SDA16_LD1
+ENUMX
+  BFD_RELOC_ARC_SDA16_LD2
+ENUMX
+  BFD_RELOC_ARC_S13_PCREL
+ENUMX
+  BFD_RELOC_ARC_W
+ENUMX
+  BFD_RELOC_ARC_32_ME
+ENUMX
+  BFD_RELOC_ARC_32_ME_S
+ENUMX
+  BFD_RELOC_ARC_N32_ME
+ENUMX
+  BFD_RELOC_ARC_SECTOFF_ME
+ENUMX
+  BFD_RELOC_ARC_SDA32_ME
+ENUMX
+  BFD_RELOC_ARC_W_ME
+ENUMX
+  BFD_RELOC_AC_SECTOFF_U8
+ENUMX
+  BFD_RELOC_AC_SECTOFF_U8_1
+ENUMX
+  BFD_RELOC_AC_SECTOFF_U8_2
+ENUMX
+  BFD_RELOC_AC_SECTFOFF_S9
+ENUMX
+  BFD_RELOC_AC_SECTFOFF_S9_1
+ENUMX
+  BFD_RELOC_AC_SECTFOFF_S9_2
+ENUMX
+  BFD_RELOC_ARC_SECTOFF_ME_1
+ENUMX
+  BFD_RELOC_ARC_SECTOFF_ME_2
+ENUMX
+  BFD_RELOC_ARC_SECTOFF_1
+ENUMX
+  BFD_RELOC_ARC_SECTOFF_2
+ENUMX
+  BFD_RELOC_ARC_SDA16_ST2
+ENUMX
+  BFD_RELOC_ARC_PC32
+ENUMX
+  BFD_RELOC_ARC_GOT32
+ENUMX
+  BFD_RELOC_ARC_GOTPC32
+ENUMX
+  BFD_RELOC_ARC_PLT32
+ENUMX
+  BFD_RELOC_ARC_COPY
+ENUMX
+  BFD_RELOC_ARC_GLOB_DAT
+ENUMX
+  BFD_RELOC_ARC_JMP_SLOT
+ENUMX
+  BFD_RELOC_ARC_RELATIVE
+ENUMX
+  BFD_RELOC_ARC_GOTOFF
+ENUMX
+  BFD_RELOC_ARC_GOTPC
+ENUMX
+  BFD_RELOC_ARC_S21W_PCREL_PLT
+ENUMX
+  BFD_RELOC_ARC_S25H_PCREL_PLT
+ENUMX
+  BFD_RELOC_ARC_TLS_DTPMOD
+ENUMX
+  BFD_RELOC_ARC_TLS_TPOFF
+ENUMX
+  BFD_RELOC_ARC_TLS_GD_GOT
+ENUMX
+  BFD_RELOC_ARC_TLS_GD_LD
+ENUMX
+  BFD_RELOC_ARC_TLS_GD_CALL
+ENUMX
+  BFD_RELOC_ARC_TLS_IE_GOT
+ENUMX
+  BFD_RELOC_ARC_TLS_DTPOFF
+ENUMX
+  BFD_RELOC_ARC_TLS_DTPOFF_S9
+ENUMX
+  BFD_RELOC_ARC_TLS_LE_S9
+ENUMX
+  BFD_RELOC_ARC_TLS_LE_32
+ENUMX
+  BFD_RELOC_ARC_S25W_PCREL_PLT
+ENUMX
+  BFD_RELOC_ARC_S21H_PCREL_PLT
 ENUMDOC
-  ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
-  stored in the instruction.  The high 24 bits are installed in bits 23
-  through 0.
+  ARC relocs.
 
 ENUM
   BFD_RELOC_BFIN_16_IMM

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 16ed7c4..e40926b 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,16 @@
+2015-09-01  Claudiu Zissulescu  <claziss@synopsys.com>
+           Cupertino Miranda  <cmiranda@synopsys.com>
+
+       * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
+       and ARCv2.
+       (get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
+       (guess_is_rela): Likewise.
+       (dump_relocations): Likewise.
+       (is_32bit_abs_reloc): Likewise.
+       (is_16bit_abs_reloc): Likewise.
+       (is_none_reloc): Likewise.
+       * NEWS: Mention the new feature.
+
 2015-09-29  Andrew Stubbs  <ams@codesourcery.com>
            H.J. Lu  <hongjiu.lu@intel.com>
 

diff --git a/binutils/NEWS b/binutils/NEWS
index afcd7c9..fb36cf1 100644 (file)
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the ARC EM/HS, and ARC600/700 architectures.
+
 * Extend objcopy --compress-debug-sections option to support
   --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF
   targets.

diff --git a/binutils/readelf.c b/binutils/readelf.c
index bbf5b02..e8c215d 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -728,6 +728,9 @@ guess_is_rela (unsigned int e_machine)
     case EM_ADAPTEVA_EPIPHANY:
     case EM_ALPHA:
     case EM_ALTERA_NIOS2:
+    case EM_ARC:
+    case EM_ARC_COMPACT:
+    case EM_ARC_COMPACT2:
     case EM_AVR:
     case EM_AVR_OLD:
     case EM_BLACKFIN:
@@ -1315,6 +1318,8 @@ dump_relocations (FILE * file,
          break;
 
        case EM_ARC:
+       case EM_ARC_COMPACT:
+       case EM_ARC_COMPACT2:
          rtype = elf_arc_reloc_type (type);
          break;
 
@@ -2115,6 +2120,8 @@ get_machine_name (unsigned e_machine)
     case EM_SPARCV9:           return "Sparc v9";
     case EM_TRICORE:           return "Siemens Tricore";
     case EM_ARC:               return "ARC";
+    case EM_ARC_COMPACT:       return "ARCompact";
+    case EM_ARC_COMPACT2:      return "ARCv2";
     case EM_H8_300:            return "Renesas H8/300";
     case EM_H8_300H:           return "Renesas H8/300H";
     case EM_H8S:               return "Renesas H8S";
@@ -2182,7 +2189,6 @@ get_machine_name (unsigned e_machine)
     case EM_SCORE:             return "SUNPLUS S+Core";
     case EM_XSTORMY16:         return "Sanyo XStormy16 CPU core";
     case EM_OR1K:              return "OpenRISC 1000";
-    case EM_ARC_A5:            return "ARC International ARCompact processor";
     case EM_CRX:               return "National Semiconductor CRX microprocessor";
     case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY";
     case EM_DLX:               return "OpenDLX";
@@ -2761,6 +2767,63 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
        default:
          break;
 
+       case EM_ARC_COMPACT2:
+         switch (e_flags & EF_ARC_MACH_MSK)
+           {
+           case EF_ARC_CPU_ARCV2EM:
+             strcat (buf, ", ARC EM");
+             break;
+           case EF_ARC_CPU_ARCV2HS:
+             strcat (buf, ", ARC HS");
+             break;
+           default:
+             strcat (buf, ", unrecognized flag for ARCv2");
+             break;
+           }
+         switch (e_flags & EF_ARC_OSABI_MSK)
+           {
+             /* Only upstream 3.9+ kernels will support ARCv2
+                ISA.  */
+           case E_ARC_OSABI_V3:
+             strcat (buf, ", v3 no-legacy-syscalls ABI");
+             break;
+           }
+         break;
+
+       case EM_ARC_COMPACT:
+         switch (e_flags & EF_ARC_MACH_MSK)
+           {
+           case E_ARC_MACH_ARC600:
+             strcat (buf, ", ARC 600");
+             break;
+           case E_ARC_MACH_ARC601:
+             strcat (buf, ", ARC 601");
+             break;
+           case E_ARC_MACH_ARC700:
+             strcat (buf, ", ARC 700");
+             break;
+           default:
+             strcat (buf, ", Generic ARCompact");
+             break;
+           }
+         switch (e_flags & EF_ARC_OSABI_MSK)
+           {
+           case E_ARC_OSABI_ORIG:
+             strcat (buf, ", legacy syscall ABI");
+             break;
+           case E_ARC_OSABI_V2:
+             /* For 3.2+ Linux kernels which use asm-generic
+                hdrs.  */
+             strcat (buf, ", v2 syscall ABI");
+             break;
+           case E_ARC_OSABI_V3:
+             /* Upstream 3.9+ kernels which don't use any legacy
+                syscalls.  */
+             strcat (buf, ", v3 no-legacy-syscalls ABI");
+             break;
+           }
+         break;
+
        case EM_ARM:
          decode_ARM_machine_flags (e_flags, buf);
          break;
@@ -11302,6 +11365,9 @@ is_32bit_abs_reloc (unsigned int reloc_type)
       return reloc_type == 1; /* R_ALPHA_REFLONG.  */
     case EM_ARC:
       return reloc_type == 1; /* R_ARC_32.  */
+    case EM_ARC_COMPACT:
+    case EM_ARC_COMPACT2:
+      return reloc_type == 4; /* R_ARC_32.  */
     case EM_ARM:
       return reloc_type == 2; /* R_ARM_ABS32 */
     case EM_AVR_OLD:
@@ -11620,6 +11686,10 @@ is_16bit_abs_reloc (unsigned int reloc_type)
 {
   switch (elf_header.e_machine)
     {
+    case EM_ARC:
+    case EM_ARC_COMPACT:
+    case EM_ARC_COMPACT2:
+      return reloc_type == 2; /* R_ARC_16.  */
     case EM_AVR_OLD:
     case EM_AVR:
       return reloc_type == 4; /* R_AVR_16.  */
@@ -11690,6 +11760,9 @@ is_none_reloc (unsigned int reloc_type)
     case EM_ADAPTEVA_EPIPHANY:
     case EM_PPC:     /* R_PPC_NONE.  */
     case EM_PPC64:   /* R_PPC64_NONE.  */
+    case EM_ARC:     /* R_ARC_NONE.  */
+    case EM_ARC_COMPACT: /* R_ARC_NONE.  */
+    case EM_ARC_COMPACT2: /* R_ARC_NONE.  */
     case EM_ARM:     /* R_ARM_NONE.  */
     case EM_IA_64:   /* R_IA64_NONE.  */
     case EM_SH:      /* R_SH_NONE.  */

diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 62c91d8..c3cbb13 100644 (file)
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
 set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
 
 set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc arm cris
+lappend cpus_expected aarch64 alpha arc HS arm cris
 lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
 lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
 lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2ece5c0..14b1647 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+        * config/tc-arc.c: Revamped file for ARC support.
+        * config/tc-arc.h: Likewise.
+        * doc/as.texinfo: Add new ARC options.
+        * doc/c-arc.texi: Likewise.
+
 2015-10-02  Renlin Li <renlin.li@arm.com>
 
        * config/tc-aarch64.c (s_tlsdescadd): New.

diff --git a/gas/NEWS b/gas/NEWS
index 13a1911..03cfa64 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
 -*- text -*-
 
+* Add support for the ARC EM/HS, and ARC600/700 architectures.  Remove
+  assembler support for Argonaut RISC architectures.
+
 Changes in 2.26:
 
 * Symbol and label names can now be enclosed in double quotes (") which allows

diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 4806ed8..cc56797 100644 (file)
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1,6 +1,7 @@
 /* tc-arc.c -- Assembler for the ARC
    Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+
+   Contributor: Claudiu Zissulescu <claziss@synopsys.com>
 
    This file is part of GAS, the GNU Assembler.
 
@@ -20,62 +21,57 @@
    02110-1301, USA.  */
 
 #include "as.h"
+#include "subsegs.h"
 #include "struc-symbol.h"
+#include "dwarf2dbg.h"
 #include "safe-ctype.h"
-#include "subsegs.h"
+
 #include "opcode/arc.h"
-#include "../opcodes/arc-ext.h"
 #include "elf/arc.h"
-#include "dwarf2dbg.h"
 
-const struct suffix_classes
-{
-  char *name;
-  int  len;
-} suffixclass[] =
-{
-  { "SUFFIX_COND|SUFFIX_FLAG",23 },
-  { "SUFFIX_FLAG", 11 },
-  { "SUFFIX_COND", 11 },
-  { "SUFFIX_NONE", 11 }
-};
+/* Defines section.  */
 
-#define MAXSUFFIXCLASS (sizeof (suffixclass) / sizeof (struct suffix_classes))
+#define MAX_FLAG_NAME_LENGHT 3
+#define MAX_INSN_FIXUPS      2
+#define MAX_CONSTR_STR       20
 
-const struct syntax_classes
-{
-  char *name;
-  int  len;
-  int  s_class;
-} syntaxclass[] =
-{
-  { "SYNTAX_3OP|OP1_MUST_BE_IMM", 26, SYNTAX_3OP|OP1_MUST_BE_IMM|SYNTAX_VALID },
-  { "OP1_MUST_BE_IMM|SYNTAX_3OP", 26, OP1_MUST_BE_IMM|SYNTAX_3OP|SYNTAX_VALID },
-  { "SYNTAX_2OP|OP1_IMM_IMPLIED", 26, SYNTAX_2OP|OP1_IMM_IMPLIED|SYNTAX_VALID },
-  { "OP1_IMM_IMPLIED|SYNTAX_2OP", 26, OP1_IMM_IMPLIED|SYNTAX_2OP|SYNTAX_VALID },
-  { "SYNTAX_3OP",                 10, SYNTAX_3OP|SYNTAX_VALID },
-  { "SYNTAX_2OP",                 10, SYNTAX_2OP|SYNTAX_VALID }
-};
+#ifdef DEBUG
+# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
+#else
+# define pr_debug(fmt, args...)
+#endif
+
+#define MAJOR_OPCODE(x)  (((x) & 0xF8000000) >> 27)
+#define SUB_OPCODE(x)   (((x) & 0x003F0000) >> 16)
+#define LP_INSN(x)      ((MAJOR_OPCODE (x) == 0x4) &&  \
+                         (SUB_OPCODE (x) == 0x28))
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+/* Macros section.  */
+
+#define regno(x)               ((x) & 0x3F)
+#define is_ir_num(x)           (((x) & ~0x3F) == 0)
+#define is_code_density_p(op)   (((op)->subclass == CD1 || (op)->subclass == CD2))
+#define is_br_jmp_insn_p(op)    (((op)->class == BRANCH || (op)->class == JUMP))
+#define is_kernel_insn_p(op)    (((op)->class == KERNEL))
 
-#define MAXSYNTAXCLASS (sizeof (syntaxclass) / sizeof (struct syntax_classes))
+/* Generic assembler global variables which must be defined by all
+   targets.  */
 
-/* This array holds the chars that always start a comment.  If the
-   pre-processor is disabled, these aren't very useful.  */
+/* Characters which always start a comment.  */
 const char comment_chars[] = "#;";
 
-/* This array holds the chars that only start a comment at the beginning of
-   a line.  If the line seems to have the form '# 123 filename'
-   .line and .file directives will appear in the pre-processed output */
-/* Note that input_file.c hand checks for '#' at the beginning of the
-   first line of the input file.  This is because the compiler outputs
-   #NO_APP at the beginning of its output.  */
-/* Also note that comments started like this one will always
-   work if '/' isn't otherwise defined.  */
+/* Characters which start a comment at the beginning of a line.  */
 const char line_comment_chars[] = "#";
 
-const char line_separator_chars[] = "";
+/* Characters which may be used to separate multiple commands on a
+   single line.  */
+const char line_separator_chars[] = "`";
 
-/* Chars that can be used to separate mant from exp in floating point nums.  */
+/* Characters which are used to indicate an exponent in a floating
+   point number.  */
 const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant
@@ -87,925 +83,949 @@ extern int target_big_endian;
 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
 static int byte_order = DEFAULT_BYTE_ORDER;
 
-static segT arcext_section;
+extern int arc_get_mach (char *);
 
-/* One of bfd_mach_arc_n.  */
-static int arc_mach_type = bfd_mach_arc_6;
+/* Forward declaration.  */
+static void arc_lcomm (int);
+static void arc_option (int);
+static void arc_extra_reloc (int);
 
-/* Non-zero if the cpu type has been explicitly specified.  */
-static int mach_type_specified_p = 0;
+const pseudo_typeS md_pseudo_table[] =
+  {
+    /* Make sure that .word is 32 bits.  */
+    { "word", cons, 4 },
+
+    { "align",   s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
+    { "lcomm",   arc_lcomm, 0 },
+    { "lcommon", arc_lcomm, 0 },
+    { "cpu",     arc_option, 0 },
 
-/* Non-zero if opcode tables have been initialized.
-   A .option command must appear before any instructions.  */
-static int cpu_tables_init_p = 0;
+    { "tls_gd_ld",   arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
+    { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
+
+    { NULL, NULL, 0 }
+  };
 
-static struct hash_control *arc_suffix_hash = NULL;
-\f
 const char *md_shortopts = "";
 
 enum options
-{
-  OPTION_EB = OPTION_MD_BASE,
-  OPTION_EL,
-  OPTION_ARC5,
-  OPTION_ARC6,
-  OPTION_ARC7,
-  OPTION_ARC8,
-  OPTION_ARC
-};
+  {
+    OPTION_EB = OPTION_MD_BASE,
+    OPTION_EL,
+
+    OPTION_ARC600,
+    OPTION_ARC601,
+    OPTION_ARC700,
+    OPTION_ARCEM,
+    OPTION_ARCHS,
+
+    OPTION_MCPU,
+    OPTION_CD,
+
+    /* The following options are deprecated and provided here only for
+       compatibility reasons.  */
+    OPTION_USER_MODE,
+    OPTION_LD_EXT_MASK,
+    OPTION_SWAP,
+    OPTION_NORM,
+    OPTION_BARREL_SHIFT,
+    OPTION_MIN_MAX,
+    OPTION_NO_MPY,
+    OPTION_EA,
+    OPTION_MUL64,
+    OPTION_SIMD,
+    OPTION_SPFP,
+    OPTION_DPFP,
+    OPTION_XMAC_D16,
+    OPTION_XMAC_24,
+    OPTION_DSP_PACKA,
+    OPTION_CRC,
+    OPTION_DVBF,
+    OPTION_TELEPHONY,
+    OPTION_XYMEMORY,
+    OPTION_LOCK,
+    OPTION_SWAPE,
+    OPTION_RTSC,
+    OPTION_FPUDA
+  };
 
 struct option md_longopts[] =
-{
-  { "EB", no_argument, NULL, OPTION_EB },
-  { "EL", no_argument, NULL, OPTION_EL },
-  { "marc5", no_argument, NULL, OPTION_ARC5 },
-  { "pre-v6", no_argument, NULL, OPTION_ARC5 },
-  { "marc6", no_argument, NULL, OPTION_ARC6 },
-  { "marc7", no_argument, NULL, OPTION_ARC7 },
-  { "marc8", no_argument, NULL, OPTION_ARC8 },
-  { "marc", no_argument, NULL, OPTION_ARC },
-  { NULL, no_argument, NULL, 0 }
-};
-size_t md_longopts_size = sizeof (md_longopts);
+  {
+    { "EB",            no_argument,       NULL, OPTION_EB },
+    { "EL",            no_argument,       NULL, OPTION_EL },
+    { "mcpu",          required_argument, NULL, OPTION_MCPU },
+    { "mA6",           no_argument,       NULL, OPTION_ARC600 },
+    { "mARC600",       no_argument,       NULL, OPTION_ARC600 },
+    { "mARC601",       no_argument,       NULL, OPTION_ARC601 },
+    { "mARC700",       no_argument,       NULL, OPTION_ARC700 },
+    { "mA7",           no_argument,       NULL, OPTION_ARC700 },
+    { "mEM",           no_argument,       NULL, OPTION_ARCEM },
+    { "mHS",           no_argument,       NULL, OPTION_ARCHS },
+    { "mcode-density", no_argument,       NULL, OPTION_CD },
+
+    /* The following options are deprecated and provided here only for
+       compatibility reasons.  */
+    { "mav2em", no_argument, NULL, OPTION_ARCEM },
+    { "mav2hs", no_argument, NULL, OPTION_ARCHS },
+    { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
+    { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
+    { "mswap", no_argument, NULL, OPTION_SWAP },
+    { "mnorm", no_argument, NULL, OPTION_NORM },
+    { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
+    { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
+    { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
+    { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
+    { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
+    { "mea", no_argument, NULL, OPTION_EA },
+    { "mEA", no_argument, NULL, OPTION_EA },
+    { "mmul64", no_argument, NULL, OPTION_MUL64 },
+    { "msimd", no_argument, NULL, OPTION_SIMD},
+    { "mspfp", no_argument, NULL, OPTION_SPFP},
+    { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
+    { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
+    { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
+    { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
+    { "mdpfp", no_argument, NULL, OPTION_DPFP},
+    { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
+    { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
+    { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
+    { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
+    { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
+    { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
+    { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
+    { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
+    { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
+    { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
+    { "mcrc", no_argument, NULL, OPTION_CRC},
+    { "mdvbf", no_argument, NULL, OPTION_DVBF},
+    { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
+    { "mxy", no_argument, NULL, OPTION_XYMEMORY},
+    { "mlock", no_argument, NULL, OPTION_LOCK},
+    { "mswape", no_argument, NULL, OPTION_SWAPE},
+    { "mrtsc", no_argument, NULL, OPTION_RTSC},
+    { "mfpuda", no_argument, NULL, OPTION_FPUDA},
+
+    { NULL,            no_argument, NULL, 0 }
+  };
 
-#define IS_SYMBOL_OPERAND(o) \
- ((o) == 'b' || (o) == 'c' || (o) == 's' || (o) == 'o' || (o) == 'O')
-
-struct arc_operand_value *get_ext_suffix (char *s);
+size_t md_longopts_size = sizeof (md_longopts);
 
-/* Invocation line includes a switch not recognized by the base assembler.
-   See if it's a processor-specific option.  */
+/* Local data and data types.  */
 
-int
-md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
-{
-  switch (c)
-    {
-    case OPTION_ARC5:
-      arc_mach_type = bfd_mach_arc_5;
-      break;
-    case OPTION_ARC:
-    case OPTION_ARC6:
-      arc_mach_type = bfd_mach_arc_6;
-      break;
-    case OPTION_ARC7:
-      arc_mach_type = bfd_mach_arc_7;
-      break;
-    case OPTION_ARC8:
-      arc_mach_type = bfd_mach_arc_8;
-      break;
-    case OPTION_EB:
-      byte_order = BIG_ENDIAN;
-      arc_target_format = "elf32-bigarc";
-      break;
-    case OPTION_EL:
-      byte_order = LITTLE_ENDIAN;
-      arc_target_format = "elf32-littlearc";
-      break;
-    default:
-      return 0;
-    }
-  return 1;
-}
+/* Used since new relocation types are introduced in this
+   file (DUMMY_RELOC_LITUSE_*).  */
+typedef int extended_bfd_reloc_code_real_type;
 
-void
-md_show_usage (FILE *stream)
+struct arc_fixup
 {
-  fprintf (stream, "\
-ARC Options:\n\
-  -marc[5|6|7|8]          select processor variant (default arc%d)\n\
-  -EB                     assemble code for a big endian cpu\n\
-  -EL                     assemble code for a little endian cpu\n", arc_mach_type + 5);
-}
+  expressionS exp;
 
-/* This function is called once, at assembler startup time.  It should
-   set up all the tables, etc. that the MD part of the assembler will need.
-   Opcode selection is deferred until later because we might see a .option
-   command.  */
+  extended_bfd_reloc_code_real_type reloc;
 
-void
-md_begin (void)
-{
-  /* The endianness can be chosen "at the factory".  */
-  target_big_endian = byte_order == BIG_ENDIAN;
+  /* index into arc_operands.  */
+  unsigned int opindex;
 
-  if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
-    as_warn (_("could not set architecture and machine"));
+  /* PC-relative, used by internals fixups.  */
+  unsigned char pcrel;
 
-  /* This call is necessary because we need to initialize `arc_operand_map'
-     which may be needed before we see the first insn.  */
-  arc_opcode_init_tables (arc_get_opcode_mach (arc_mach_type,
-                                              target_big_endian));
-}
+  /* TRUE if this fixup is for LIMM operand.  */
+  bfd_boolean islong;
+};
 
-/* Initialize the various opcode and operand tables.
-   MACH is one of bfd_mach_arc_xxx.  */
+struct arc_insn
+{
+  unsigned int insn;
+  int nfixups;
+  struct arc_fixup fixups[MAX_INSN_FIXUPS];
+  long limm;
+  bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
+                            short.  */
+  bfd_boolean has_limm;   /* Boolean value: TRUE if limm field is
+                            valid.  */
+};
 
-static void
-init_opcode_tables (int mach)
+/* Structure to hold any last two instructions.  */
+static struct arc_last_insn
 {
-  int i;
-  char *last;
+  /* Saved instruction opcode.  */
+  const struct arc_opcode *opcode;
 
-  if ((arc_suffix_hash = hash_new ()) == NULL)
-    as_fatal (_("virtual memory exhausted"));
+  /* Boolean value: TRUE if current insn is short.  */
+  bfd_boolean has_limm;
 
-  if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
-    as_warn (_("could not set architecture and machine"));
+  /* Boolean value: TRUE if current insn has delay slot.  */
+  bfd_boolean has_delay_slot;
+} arc_last_insns[2];
 
-  /* This initializes a few things in arc-opc.c that we need.
-     This must be called before the various arc_xxx_supported fns.  */
-  arc_opcode_init_tables (arc_get_opcode_mach (mach, target_big_endian));
+/* The cpu for which we are generating code.  */
+static unsigned arc_target = ARC_OPCODE_BASE;
+static const char *arc_target_name = "<all>";
+static unsigned arc_features = 0x00;
 
-  /* Only put the first entry of each equivalently named suffix in the
-     table.  */
-  last = "";
-  for (i = 0; i < arc_suffixes_count; i++)
-    {
-      if (strcmp (arc_suffixes[i].name, last) != 0)
-       hash_insert (arc_suffix_hash, arc_suffixes[i].name, (void *) (arc_suffixes + i));
-      last = arc_suffixes[i].name;
-    }
+/* The default architecture.  */
+static int arc_mach_type = bfd_mach_arc_arcv2;
 
-  /* Since registers don't have a prefix, we put them in the symbol table so
-     they can't be used as symbols.  This also simplifies argument parsing as
-     we can let gas parse registers for us.  The recorded register number is
-     the address of the register's entry in arc_reg_names.
+/* Non-zero if the cpu type has been explicitly specified.  */
+static int mach_type_specified_p = 0;
 
-     If the register name is already in the table, then the existing
-     definition is assumed to be from an .ExtCoreRegister pseudo-op.  */
+/* The hash table of instruction opcodes.  */
+static struct hash_control *arc_opcode_hash;
 
-  for (i = 0; i < arc_reg_names_count; i++)
-    {
-      if (symbol_find (arc_reg_names[i].name))
-       continue;
-      /* Use symbol_create here instead of symbol_new so we don't try to
-        output registers into the object file's symbol table.  */
-      symbol_table_insert (symbol_create (arc_reg_names[i].name,
-                                         reg_section,
-                                         (valueT) &arc_reg_names[i],
-                                         &zero_address_frag));
-    }
+/* The hash table of register symbols.  */
+static struct hash_control *arc_reg_hash;
 
-  /* Tell `.option' it's too late.  */
-  cpu_tables_init_p = 1;
+/* A table of CPU names and opcode sets.  */
+static const struct cpu_type
+{
+  const char *name;
+  unsigned flags;
+  int mach;
+  unsigned eflags;
+  unsigned features;
 }
-\f
-/* Insert an operand value into an instruction.
-   If REG is non-NULL, it is a register number and ignore VAL.  */
-
-static arc_insn
-arc_insert_operand (arc_insn insn,
-                   const struct arc_operand *operand,
-                   int mods,
-                   const struct arc_operand_value *reg,
-                   offsetT val,
-                   char *file,
-                   unsigned int line)
+  cpu_types[] =
 {
-  if (operand->bits != 32)
-    {
-      long min, max;
-      offsetT test;
-
-      if ((operand->flags & ARC_OPERAND_SIGNED) != 0)
-       {
-         if ((operand->flags & ARC_OPERAND_SIGNOPT) != 0)
-           max = (1 << operand->bits) - 1;
-         else
-           max = (1 << (operand->bits - 1)) - 1;
-         min = - (1 << (operand->bits - 1));
-       }
-      else
-       {
-         max = (1 << operand->bits) - 1;
-         min = 0;
-       }
+  { "arc600", ARC_OPCODE_ARC600,  bfd_mach_arc_arc600,
+    E_ARC_MACH_ARC600,  0x00},
+  { "arc700", ARC_OPCODE_ARC700,  bfd_mach_arc_arc700,
+    E_ARC_MACH_ARC700,  0x00},
+  { "arcem",  ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
+    EF_ARC_CPU_ARCV2EM, 0x00},
+  { "archs",  ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
+    EF_ARC_CPU_ARCV2HS, ARC_CD},
+  { "all",    ARC_OPCODE_BASE,    bfd_mach_arc_arcv2,
+    0x00, 0x00 },
+  { 0, 0, 0, 0, 0 }
+};
 
-      if ((operand->flags & ARC_OPERAND_NEGATIVE) != 0)
-       test = - val;
-      else
-       test = val;
+struct arc_flags
+{
+  /* Name of the parsed flag.  */
+  char name[MAX_FLAG_NAME_LENGHT+1];
 
-      if (test < (offsetT) min || test > (offsetT) max)
-       as_warn_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
-    }
+  /* The code of the parsed flag.  Valid when is not zero.  */
+  unsigned char code;
+};
 
-  if (operand->insert)
+/* Used by the arc_reloc_op table.  Order is important.  */
+#define O_gotoff  O_md1     /* @gotoff relocation.  */
+#define O_gotpc   O_md2     /* @gotpc relocation.  */
+#define O_plt     O_md3     /* @plt relocation.  */
+#define O_sda     O_md4     /* @sda relocation.  */
+#define O_pcl     O_md5     /* @pcl relocation.  */
+#define O_tlsgd   O_md6     /* @tlsgd relocation.  */
+#define O_tlsie   O_md7     /* @tlsie relocation.  */
+#define O_tpoff9  O_md8     /* @tpoff9 relocation.  */
+#define O_tpoff   O_md9     /* @tpoff relocation.  */
+#define O_dtpoff9 O_md10    /* @dtpoff9 relocation.  */
+#define O_dtpoff  O_md11    /* @dtpoff relocation.  */
+#define O_last    O_dtpoff
+
+/* Used to define a bracket as operand in tokens.  */
+#define O_bracket O_md32
+
+/* Dummy relocation, to be sorted out.  */
+#define DUMMY_RELOC_ARC_ENTRY     (BFD_RELOC_UNUSED + 1)
+
+#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
+
+/* A table to map the spelling of a relocation operand into an appropriate
+   bfd_reloc_code_real_type type.  The table is assumed to be ordered such
+   that op-O_literal indexes into it.  */
+#define ARC_RELOC_TABLE(op)                            \
+  (&arc_reloc_op[ ((!USER_RELOC_P (op))                        \
+                  ? (abort (), 0)                      \
+                  : (int) (op) - (int) O_gotoff) ])
+
+#define DEF(NAME, RELOC, REQ)                          \
+  { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
+
+static const struct arc_reloc_op_tag
+{
+  /* String to lookup.  */
+  const char *name;
+  /* Size of the string.  */
+  size_t length;
+  /* Which operator to use.  */
+  operatorT op;
+  extended_bfd_reloc_code_real_type reloc;
+  /* Allows complex relocation expression like identifier@reloc +
+     const.  */
+  unsigned int complex_expr : 1;
+}
+  arc_reloc_op[] =
     {
-      const char *errmsg;
+      DEF (gotoff,  BFD_RELOC_ARC_GOTOFF,       1),
+      DEF (gotpc,   BFD_RELOC_ARC_GOTPC32,      0),
+      DEF (plt,            BFD_RELOC_ARC_PLT32,         0),
+      DEF (sda,            DUMMY_RELOC_ARC_ENTRY,       1),
+      DEF (pcl,            BFD_RELOC_ARC_PC32,          1),
+      DEF (tlsgd,   BFD_RELOC_ARC_TLS_GD_GOT,   0),
+      DEF (tlsie,   BFD_RELOC_ARC_TLS_IE_GOT,   0),
+      DEF (tpoff9,  BFD_RELOC_ARC_TLS_LE_S9,    0),
+      DEF (tpoff,   BFD_RELOC_ARC_TLS_LE_32,    0),
+      DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
+      DEF (dtpoff,  BFD_RELOC_ARC_TLS_DTPOFF,   0),
+    };
 
-      errmsg = NULL;
-      insn = (*operand->insert) (insn, operand, mods, reg, (long) val, &errmsg);
-      if (errmsg != (const char *) NULL)
-       as_warn ("%s", errmsg);
+static const int arc_num_reloc_op
+= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
+
+/* Flags to set in the elf header.  */
+static flagword arc_eflag = 0x00;
+
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
+symbolS * GOT_symbol = 0;
+
+/* Set to TRUE when we assemble instructions.  */
+static bfd_boolean assembling_insn = FALSE;
+
+/* Functions declaration.  */
+
+static void assemble_tokens (const char *, expressionS *, int,
+                            struct arc_flags *, int);
+static const struct arc_opcode *find_opcode_match (const struct arc_opcode *,
+                                                  expressionS *, int *,
+                                                  struct arc_flags *,
+                                                  int, int *);
+static void assemble_insn (const struct arc_opcode *, const expressionS *,
+                          int, const struct arc_flags *, int,
+                          struct arc_insn *);
+static void emit_insn (struct arc_insn *);
+static unsigned insert_operand (unsigned, const struct arc_operand *,
+                               offsetT, char *, unsigned);
+static const struct arc_opcode *find_special_case_flag (const char *,
+                                                       int *,
+                                                       struct arc_flags *);
+static const struct arc_opcode *find_special_case (const char *,
+                                                  int *,
+                                                  struct arc_flags *,
+                                                  expressionS *, int *);
+static const struct arc_opcode *find_special_case_pseudo (const char *,
+                                                         int *,
+                                                         expressionS *,
+                                                         int *,
+                                                         struct arc_flags *);
+
+/* Functions implementation.  */
+
+/* Like md_number_to_chars but used for limms.  The 4-byte limm value,
+   is encoded as 'middle-endian' for a little-endian target.  FIXME!
+   this function is used for regular 4 byte instructions as well.  */
+
+static void
+md_number_to_chars_midend (char *buf,
+                          valueT val,
+                          int n)
+{
+  if (n == 4)
+    {
+      md_number_to_chars (buf,     (val & 0xffff0000) >> 16, 2);
+      md_number_to_chars (buf + 2, (val & 0xffff), 2);
     }
   else
-    insn |= (((long) val & ((1 << operand->bits) - 1))
-            << operand->shift);
-
-  return insn;
+    {
+      md_number_to_chars (buf, val, n);
+    }
 }
 
-/* We need to keep a list of fixups.  We can't simply generate them as
-   we go, because that would require us to first create the frag, and
-   that would screw up references to ``.''.  */
+/* Here ends all the ARCompact extension instruction assembling
+   stuff.  */
 
-struct arc_fixup
+static void
+arc_extra_reloc (int r_type)
 {
-  /* index into `arc_operands'  */
-  int opindex;
-  expressionS exp;
-};
+  char *sym_name, c;
+  symbolS *sym, *lab = NULL;
+
+  if (*input_line_pointer == '@')
+    input_line_pointer++;
+  c = get_symbol_name (&sym_name);
+  sym = symbol_find_or_make (sym_name);
+  restore_line_pointer (c);
+  if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
+    {
+      ++input_line_pointer;
+      char *lab_name;
+      c = get_symbol_name (&lab_name);
+      lab = symbol_find_or_make (lab_name);
+      restore_line_pointer (c);
+    }
+  fixS *fixP
+    = fix_new (frag_now,       /* Which frag?  */
+              frag_now_fix (), /* Where in that frag?  */
+              2,               /* size: 1, 2, or 4 usually.  */
+              sym,             /* X_add_symbol.  */
+              0,               /* X_add_number.  */
+              FALSE,           /* TRUE if PC-relative relocation.  */
+              r_type           /* Relocation type.  */);
+  fixP->fx_subsy = lab;
+}
 
-#define MAX_FIXUPS 5
+static symbolS *
+arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
+                   symbolS *symbolP, addressT size)
+{
+  addressT align = 0;
+  SKIP_WHITESPACE ();
 
-#define MAX_SUFFIXES 5
+  if (*input_line_pointer == ',')
+    {
+      align = parse_align (1);
 
-/* Compute the reloc type of an expression.
-   The possibly modified expression is stored in EXPNEW.
+      if (align == (addressT) -1)
+       return NULL;
+    }
+  else
+    {
+      if (size >= 8)
+       align = 3;
+      else if (size >= 4)
+       align = 2;
+      else if (size >= 2)
+       align = 1;
+      else
+       align = 0;
+    }
 
-   This is used to convert the expressions generated by the %-op's into
-   the appropriate operand type.  It is called for both data in instructions
-   (operands) and data outside instructions (variables, debugging info, etc.).
+  bss_alloc (symbolP, size, align);
+  S_CLEAR_EXTERNAL (symbolP);
 
-   Currently supported %-ops:
+  return symbolP;
+}
 
-   %st(symbol): represented as "symbol >> 2"
-                "st" is short for STatus as in the status register (pc)
+static void
+arc_lcomm (int ignore)
+{
+  symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
 
-   DEFAULT_TYPE is the type to use if no special processing is required.
+  if (symbolP)
+    symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
+}
 
-   DATA_P is non-zero for data or limm values, zero for insn operands.
-   Remember that the opcode "insertion fns" cannot be used on data, they're
-   only for inserting operands into insns.  They also can't be used for limm
-   values as the insertion routines don't handle limm values.  When called for
-   insns we return fudged reloc types (real_value - BFD_RELOC_UNUSED).  When
-   called for data or limm values we use real reloc types.  */
+/* Select the cpu we're assembling for.  */
 
-static int
-get_arc_exp_reloc_type (int data_p,
-                       int default_type,
-                       expressionS *exp,
-                       expressionS *expnew)
+static void
+arc_option (int ignore ATTRIBUTE_UNUSED)
 {
-  /* If the expression is "symbol >> 2" we must change it to just "symbol",
-     as fix_new_exp can't handle it.  Similarly for (symbol - symbol) >> 2.
-     That's ok though.  What's really going on here is that we're using
-     ">> 2" as a special syntax for specifying BFD_RELOC_ARC_B26.  */
+  int mach = -1;
+  char c;
+  char *cpu;
 
-  if (exp->X_op == O_right_shift
-      && exp->X_op_symbol != NULL
-      && exp->X_op_symbol->sy_value.X_op == O_constant
-      && exp->X_op_symbol->sy_value.X_add_number == 2
-      && exp->X_add_number == 0)
-    {
-      if (exp->X_add_symbol != NULL
-         && (exp->X_add_symbol->sy_value.X_op == O_constant
-             || exp->X_add_symbol->sy_value.X_op == O_symbol))
-       {
-         *expnew = *exp;
-         expnew->X_op = O_symbol;
-         expnew->X_op_symbol = NULL;
-         return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
-       }
-      else if (exp->X_add_symbol != NULL
-              && exp->X_add_symbol->sy_value.X_op == O_subtract)
-       {
-         *expnew = exp->X_add_symbol->sy_value;
-         return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
-       }
-    }
+  c = get_symbol_name (&cpu);
+  mach = arc_get_mach (cpu);
+  restore_line_pointer (c);
 
-  *expnew = *exp;
-  return default_type;
-}
-\f
-static int
-arc_set_ext_seg (void)
-{
-  if (!arcext_section)
+  if (mach == -1)
+    goto bad_cpu;
+
+  if (!mach_type_specified_p)
     {
-      arcext_section = subseg_new (".arcextmap", 0);
-      bfd_set_section_flags (stdoutput, arcext_section,
-                            SEC_READONLY | SEC_HAS_CONTENTS);
+      arc_mach_type = mach;
+      if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
+       as_fatal ("could not set architecture and machine");
+
+      mach_type_specified_p = 1;
     }
   else
-    subseg_set (arcext_section, 0);
-  return 1;
+    if (arc_mach_type != mach)
+      as_warn ("Command-line value overrides \".cpu\" directive");
+
+  demand_empty_rest_of_line ();
+
+  return;
+
+ bad_cpu:
+  as_bad ("invalid identifier for \".cpu\"");
+  ignore_rest_of_line ();
 }
 
+/* Smartly print an expression.  */
+
 static void
-arc_extoper (int opertype)
+debug_exp (expressionS *t)
 {
-  char *name;
-  char *mode;
-  char c;
-  char *p;
-  int imode = 0;
-  int number;
-  struct arc_ext_operand_value *ext_oper;
-  symbolS *symbolP;
+  const char *name ATTRIBUTE_UNUSED;
+  const char *namemd ATTRIBUTE_UNUSED;
 
-  segT old_sec;
-  int old_subsec;
+  pr_debug ("debug_exp: ");
 
-  c = get_symbol_name (&name);
-  name = xstrdup (name);
-
-  p = name;
-  while (*p)
+  switch (t->X_op)
     {
-      *p = TOLOWER (*p);
-      p++;
+    default:                   name = "unknown";               break;
+    case O_illegal:            name = "O_illegal";             break;
+    case O_absent:             name = "O_absent";              break;
+    case O_constant:           name = "O_constant";            break;
+    case O_symbol:             name = "O_symbol";              break;
+    case O_symbol_rva:         name = "O_symbol_rva";          break;
+    case O_register:           name = "O_register";            break;
+    case O_big:                        name = "O_big";                 break;
+    case O_uminus:             name = "O_uminus";              break;
+    case O_bit_not:            name = "O_bit_not";             break;
+    case O_logical_not:                name = "O_logical_not";         break;
+    case O_multiply:           name = "O_multiply";            break;
+    case O_divide:             name = "O_divide";              break;
+    case O_modulus:            name = "O_modulus";             break;
+    case O_left_shift:         name = "O_left_shift";          break;
+    case O_right_shift:                name = "O_right_shift";         break;
+    case O_bit_inclusive_or:   name = "O_bit_inclusive_or";    break;
+    case O_bit_or_not:         name = "O_bit_or_not";          break;
+    case O_bit_exclusive_or:   name = "O_bit_exclusive_or";    break;
+    case O_bit_and:            name = "O_bit_and";             break;
+    case O_add:                        name = "O_add";                 break;
+    case O_subtract:           name = "O_subtract";            break;
+    case O_eq:                 name = "O_eq";                  break;
+    case O_ne:                 name = "O_ne";                  break;
+    case O_lt:                 name = "O_lt";                  break;
+    case O_le:                 name = "O_le";                  break;
+    case O_ge:                 name = "O_ge";                  break;
+    case O_gt:                 name = "O_gt";                  break;
+    case O_logical_and:                name = "O_logical_and";         break;
+    case O_logical_or:         name = "O_logical_or";          break;
+    case O_index:              name = "O_index";               break;
+    case O_bracket:            name = "O_bracket";             break;
     }
 
-  /* just after name is now '\0'  */
-  p = input_line_pointer;
-  (void) restore_line_pointer (c);
-  SKIP_WHITESPACE ();
-
-  if (*input_line_pointer != ',')
+  switch (t->X_md)
     {
-      as_bad (_("expected comma after operand name"));
-      ignore_rest_of_line ();
-      free (name);
-      return;
+    default:                   namemd = "unknown";             break;
+    case O_gotoff:             namemd = "O_gotoff";            break;
+    case O_gotpc:              namemd = "O_gotpc";             break;
+    case O_plt:                        namemd = "O_plt";               break;
+    case O_sda:                        namemd = "O_sda";               break;
+    case O_pcl:                        namemd = "O_pcl";               break;
+    case O_tlsgd:              namemd = "O_tlsgd";             break;
+    case O_tlsie:              namemd = "O_tlsie";             break;
+    case O_tpoff9:             namemd = "O_tpoff9";            break;
+    case O_tpoff:              namemd = "O_tpoff";             break;
+    case O_dtpoff9:            namemd = "O_dtpoff9";           break;
+    case O_dtpoff:             namemd = "O_dtpoff";            break;
     }
 
-  input_line_pointer++;                /* skip ','  */
-  number = get_absolute_expression ();
+  pr_debug ("%s (%s, %s, %d, %s)", name,
+           (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
+           (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
+           (int) t->X_add_number,
+           (t->X_md) ? namemd : "--");
+  pr_debug ("\n");
+  fflush (stderr);
+}
 
-  if (number < 0)
-    {
-      as_bad (_("negative operand number %d"), number);
-      ignore_rest_of_line ();
-      free (name);
-      return;
-    }
+/* Parse the arguments to an opcode.  */
+
+static int
+tokenize_arguments (char *str,
+                   expressionS *tok,
+                   int ntok)
+{
+  char *old_input_line_pointer;
+  bfd_boolean saw_comma = FALSE;
+  bfd_boolean saw_arg = FALSE;
+  int brk_lvl = 0;
+  int num_args = 0;
+  const char *p;
+  int i;
+  size_t len;
+  const struct arc_reloc_op_tag *r;
+  expressionS tmpE;
+
+  memset (tok, 0, sizeof (*tok) * ntok);
+
+  /* Save and restore input_line_pointer around this function.  */
+  old_input_line_pointer = input_line_pointer;
+  input_line_pointer = str;
 
-  if (opertype)
+  while (*input_line_pointer)
     {
       SKIP_WHITESPACE ();
-
-      if (*input_line_pointer != ',')
+      switch (*input_line_pointer)
        {
-         as_bad (_("expected comma after register-number"));
-         ignore_rest_of_line ();
-         free (name);
-         return;
-       }
+       case '\0':
+         goto fini;
+
+       case ',':
+         input_line_pointer++;
+         if (saw_comma || !saw_arg)
+           goto err;
+         saw_comma = TRUE;
+         break;
 
-      input_line_pointer++;            /* skip ','  */
-      mode = input_line_pointer;
+       case '}':
+       case ']':
+         ++input_line_pointer;
+         --brk_lvl;
+         if (!saw_arg)
+           goto err;
+         tok->X_op = O_bracket;
+         ++tok;
+         ++num_args;
+         break;
 
-      if (!strncmp (mode, "r|w", 3))
-       {
-         imode = 0;
-         input_line_pointer += 3;
-       }
-      else
-       {
-         if (!strncmp (mode, "r", 1))
-           {
-             imode = ARC_REGISTER_READONLY;
-             input_line_pointer += 1;
-           }
-         else
+       case '{':
+       case '[':
+         input_line_pointer++;
+         if (brk_lvl)
+           goto err;
+         ++brk_lvl;
+         tok->X_op = O_bracket;
+         ++tok;
+         ++num_args;
+         break;
+
+       case '@':
+         /* We have labels, function names and relocations, all
+            starting with @ symbol.  Sort them out.  */
+         if (saw_arg && !saw_comma)
+           goto err;
+
+         /* Parse @label.  */
+         tok->X_op = O_symbol;
+         tok->X_md = O_absent;
+         expression (tok);
+         if (*input_line_pointer != '@')
+           goto normalsymbol; /* This is not a relocation.  */
+
+         /* A relocation opernad has the following form
+            @identifier@relocation_type.  The identifier is already
+            in tok!  */
+         if (tok->X_op != O_symbol)
            {
-             if (strncmp (mode, "w", 1))
-               {
-                 as_bad (_("invalid mode"));
-                 ignore_rest_of_line ();
-                 free (name);
-                 return;
-               }
-             else
-               {
-                 imode = ARC_REGISTER_WRITEONLY;
-                 input_line_pointer += 1;
-               }
+             as_bad (_("No valid label relocation operand"));
+             goto err;
            }
-       }
-      SKIP_WHITESPACE ();
-      if (1 == opertype)
-       {
-         if (*input_line_pointer != ',')
+
+         /* Parse @relocation_type.  */
+         memset (&tmpE, 0, sizeof (tmpE));
+         tmpE.X_op = O_symbol;
+         expression (&tmpE);
+
+         if (tmpE.X_op != O_symbol)
            {
-             as_bad (_("expected comma after register-mode"));
-             ignore_rest_of_line ();
-             free (name);
-             return;
+             as_bad (_("No relocation operand"));
+             goto err;
            }
+         p = S_GET_NAME (tmpE.X_add_symbol);
+         len = strlen (p);
 
-         input_line_pointer++;         /* skip ','  */
+         /* Go through known relocation and try to find a match.  */
+         r = &arc_reloc_op[0];
+         for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
+           if (len == r->length && memcmp (p, r->name, len) == 0)
+             break;
 
-         if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
+         if (i < 0)
            {
-             imode |= arc_get_noshortcut_flag ();
-             input_line_pointer += 15;
+             as_bad (_("Unknown relocation operand: @%s"), p);
+             goto err;
            }
-         else
+         tok->X_md = r->op;
+         tok->X_add_number = tmpE.X_add_number;
+         if (tmpE.X_add_number && !r->complex_expr)
            {
-             if (strncmp (input_line_pointer, "can_shortcut", 12))
-               {
-                 as_bad (_("shortcut designator invalid"));
-                 ignore_rest_of_line ();
-                 free (name);
-                 return;
-               }
-             else
+             as_bad (_("Complex relocation operand."));
+             goto err;
+           }
+
+         /* Extra check for TLS: base.  */
+         if (*input_line_pointer == '@')
+           {
+             symbolS *base;
+             if (tok->X_op_symbol != NULL
+                 || tok->X_op != O_symbol)
                {
-                 input_line_pointer += 12;
+                 as_bad (_("Unable to parse this reloc"));
+                 goto err;
                }
+             input_line_pointer++;
+             char *sym_name;
+             char c = get_symbol_name (&sym_name);
+             base = symbol_find_or_make (sym_name);
+             tok->X_op = O_subtract;
+             tok->X_op_symbol = base;
+             restore_line_pointer (c);
            }
-       }
-    }
-
-  if ((opertype == 1) && number > 60)
-    {
-      as_bad (_("core register value (%d) too large"), number);
-      ignore_rest_of_line ();
-      free (name);
-      return;
-    }
-
-  if ((opertype == 0) && number > 31)
-    {
-      as_bad (_("condition code value (%d) too large"), number);
-      ignore_rest_of_line ();
-      free (name);
-      return;
-    }
 
-  ext_oper = (struct arc_ext_operand_value *)
-      xmalloc (sizeof (struct arc_ext_operand_value));
+         debug_exp (tok);
 
-  if (opertype)
-    {
-      /* If the symbol already exists, point it at the new definition.  */
-      if ((symbolP = symbol_find (name)))
-       {
-         if (S_GET_SEGMENT (symbolP) == reg_section)
-           S_SET_VALUE (symbolP, (valueT) &ext_oper->operand);
-         else
-           {
-             as_bad (_("attempt to override symbol: %s"), name);
-             ignore_rest_of_line ();
-             free (name);
-             free (ext_oper);
-             return;
-           }
-       }
-      else
-       {
-         /* If its not there, add it.  */
-         symbol_table_insert (symbol_create (name, reg_section,
-                                             (valueT) &ext_oper->operand,
-                                             &zero_address_frag));
-       }
-    }
+         saw_comma = FALSE;
+         saw_arg = TRUE;
+         tok++;
+         num_args++;
+         break;
 
-  ext_oper->operand.name  = name;
-  ext_oper->operand.value = number;
-  ext_oper->operand.type  = arc_operand_type (opertype);
-  ext_oper->operand.flags = imode;
+       case '%':
+         /* Can be a register.  */
+         ++input_line_pointer;
+         /* Fall through.  */
+       default:
 
-  ext_oper->next = arc_ext_operands;
-  arc_ext_operands = ext_oper;
+         if (saw_arg && !saw_comma)
+           goto err;
 
-  /* OK, now that we know what this operand is, put a description in
-     the arc extension section of the output file.  */
+         tok->X_op = O_absent;
+         expression (tok);
 
-  old_sec    = now_seg;
-  old_subsec = now_subseg;
+       normalsymbol:
+         debug_exp (tok);
 
-  arc_set_ext_seg ();
+         if (tok->X_op == O_illegal || tok->X_op == O_absent)
+           goto err;
 
-  switch (opertype)
-    {
-    case 0:
-      p = frag_more (1);
-      *p = 3 + strlen (name) + 1;
-      p = frag_more (1);
-      *p = EXT_COND_CODE;
-      p = frag_more (1);
-      *p = number;
-      p = frag_more (strlen (name) + 1);
-      strcpy (p, name);
-      break;
-    case 1:
-      p = frag_more (1);
-      *p = 3 + strlen (name) + 1;
-      p = frag_more (1);
-      *p = EXT_CORE_REGISTER;
-      p = frag_more (1);
-      *p = number;
-      p = frag_more (strlen (name) + 1);
-      strcpy (p, name);
-      break;
-    case 2:
-      p = frag_more (1);
-      *p = 6 + strlen (name) + 1;
-      p = frag_more (1);
-      *p = EXT_AUX_REGISTER;
-      p = frag_more (1);
-      *p = number >> 24 & 0xff;
-      p = frag_more (1);
-      *p = number >> 16 & 0xff;
-      p = frag_more (1);
-      *p = number >>  8 & 0xff;
-      p = frag_more (1);
-      *p = number       & 0xff;
-      p = frag_more (strlen (name) + 1);
-      strcpy (p, name);
-      break;
-    default:
-      as_bad (_("invalid opertype"));
-      ignore_rest_of_line ();
-      free (name);
-      return;
-      break;
+         saw_comma = FALSE;
+         saw_arg = TRUE;
+         tok++;
+         num_args++;
+         break;
+       }
     }
 
-  subseg_set (old_sec, old_subsec);
+ fini:
+  if (saw_comma || brk_lvl)
+    goto err;
+  input_line_pointer = old_input_line_pointer;
 
-  /* Enter all registers into the symbol table.  */
+  return num_args;
 
-  demand_empty_rest_of_line ();
+ err:
+  if (brk_lvl)
+    as_bad (_("Brackets in operand field incorrect"));
+  else if (saw_comma)
+    as_bad (_("extra comma"));
+  else if (!saw_arg)
+    as_bad (_("missing argument"));
+  else
+    as_bad (_("missing comma or colon"));
+  input_line_pointer = old_input_line_pointer;
+  return -1;
 }
 
-static void
-arc_extinst (int ignore ATTRIBUTE_UNUSED)
+/* Parse the flags to a structure.  */
+
+static int
+tokenize_flags (const char *str,
+               struct arc_flags flags[],
+               int nflg)
 {
-  char syntax[129];
-  char *name;
-  char *p;
-  char c;
-  int suffixcode = -1;
-  int opcode, subopcode;
-  int i;
-  int s_class = 0;
-  int name_len;
-  struct arc_opcode *ext_op;
+  char *old_input_line_pointer;
+  bfd_boolean saw_flg = FALSE;
+  bfd_boolean saw_dot = FALSE;
+  int num_flags  = 0;
+  size_t flgnamelen;
 
-  segT old_sec;
-  int old_subsec;
+  memset (flags, 0, sizeof (*flags) * nflg);
 
-  c = get_symbol_name (&name);
-  name = xstrdup (name);
-  strcpy (syntax, name);
-  name_len = strlen (name);
+  /* Save and restore input_line_pointer around this function.  */
+  old_input_line_pointer = input_line_pointer;
+  input_line_pointer = (char *) str;
 
-  /* just after name is now '\0'  */
-  p = input_line_pointer;
-  (void) restore_line_pointer (c);
+  while (*input_line_pointer)
+    {
+      switch (*input_line_pointer)
+       {
+       case ' ':
+       case '\0':
+         goto fini;
+
+       case '.':
+         input_line_pointer++;
+         if (saw_dot)
+           goto err;
+         saw_dot = TRUE;
+         saw_flg = FALSE;
+         break;
 
-  SKIP_WHITESPACE ();
+       default:
+         if (saw_flg && !saw_dot)
+           goto err;
 
-  if (*input_line_pointer != ',')
-    {
-      as_bad (_("expected comma after operand name"));
-      ignore_rest_of_line ();
-      return;
-    }
+         if (num_flags >= nflg)
+           goto err;
 
-  input_line_pointer++;                /* skip ','  */
-  opcode = get_absolute_expression ();
+         flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz");
+         if (flgnamelen > MAX_FLAG_NAME_LENGHT)
+           goto err;
 
-  SKIP_WHITESPACE ();
-
-  if (*input_line_pointer != ',')
-    {
-      as_bad (_("expected comma after opcode"));
-      ignore_rest_of_line ();
-      return;
-    }
-
-  input_line_pointer++;                /* skip ','  */
-  subopcode = get_absolute_expression ();
-
-  if (subopcode < 0)
-    {
-      as_bad (_("negative subopcode %d"), subopcode);
-      ignore_rest_of_line ();
-      return;
-    }
+         memcpy (flags->name, input_line_pointer, flgnamelen);
 
-  if (subopcode)
-    {
-      if (3 != opcode)
-       {
-         as_bad (_("subcode value found when opcode not equal 0x03"));
-         ignore_rest_of_line ();
-         return;
-       }
-      else
-       {
-         if (subopcode < 0x09 || subopcode == 0x3f)
-           {
-             as_bad (_("invalid subopcode %d"), subopcode);
-             ignore_rest_of_line ();
-             return;
-           }
+         input_line_pointer += flgnamelen;
+         flags++;
+         saw_dot = FALSE;
+         saw_flg = TRUE;
+         num_flags++;
+         break;
        }
     }
 
-  SKIP_WHITESPACE ();
-
-  if (*input_line_pointer != ',')
-    {
-      as_bad (_("expected comma after subopcode"));
-      ignore_rest_of_line ();
-      return;
-    }
+ fini:
+  input_line_pointer = old_input_line_pointer;
+  return num_flags;
 
-  input_line_pointer++;                /* skip ','  */
+ err:
+  if (saw_dot)
+    as_bad (_("extra dot"));
+  else if (!saw_flg)
+    as_bad (_("unrecognized flag"));
+  else
+    as_bad (_("failed to parse flags"));
+  input_line_pointer = old_input_line_pointer;
+  return -1;
+}
 
-  for (i = 0; i < (int) MAXSUFFIXCLASS; i++)
-    {
-      if (!strncmp (suffixclass[i].name,input_line_pointer, suffixclass[i].len))
-       {
-         suffixcode = i;
-         input_line_pointer += suffixclass[i].len;
-         break;
-       }
-    }
+/* The public interface to the instruction assembler.  */
 
-  if (-1 == suffixcode)
+void
+md_assemble (char *str)
+{
+  char *opname;
+  expressionS tok[MAX_INSN_ARGS];
+  int ntok, nflg;
+  size_t opnamelen;
+  struct arc_flags flags[MAX_INSN_FLGS];
+
+  /* Split off the opcode.  */
+  opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
+  opname = xmalloc (opnamelen + 1);
+  memcpy (opname, str, opnamelen);
+  opname[opnamelen] = '\0';
+
+  /* Signalize we are assmbling the instructions.  */
+  assembling_insn = TRUE;
+
+  /* Tokenize the flags.  */
+  if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
     {
-      as_bad (_("invalid suffix class"));
-      ignore_rest_of_line ();
+      as_bad (_("syntax error"));
       return;
     }
 
-  SKIP_WHITESPACE ();
+  /* Scan up to the end of the mnemonic which must end in space or end
+     of string.  */
+  str += opnamelen;
+  for (; *str != '\0'; str++)
+    if (*str == ' ')
+      break;
 
-  if (*input_line_pointer != ',')
+  /* Tokenize the rest of the line.  */
+  if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
     {
-      as_bad (_("expected comma after suffix class"));
-      ignore_rest_of_line ();
+      as_bad (_("syntax error"));
       return;
     }
 
-  input_line_pointer++;                /* skip ','  */
+  /* Finish it off.  */
+  assemble_tokens (opname, tok, ntok, flags, nflg);
+  assembling_insn = FALSE;
+}
 
-  for (i = 0; i < (int) MAXSYNTAXCLASS; i++)
-    {
-      if (!strncmp (syntaxclass[i].name,input_line_pointer, syntaxclass[i].len))
-       {
-         s_class = syntaxclass[i].s_class;
-         input_line_pointer += syntaxclass[i].len;
-         break;
-       }
-    }
+/* Callback to insert a register into the hash table.  */
 
-  if (0 == (SYNTAX_VALID & s_class))
-    {
-      as_bad (_("invalid syntax class"));
-      ignore_rest_of_line ();
-      return;
-    }
+static void
+declare_register (char *name, int number)
+{
+  const char *err;
+  symbolS *regS = symbol_create (name, reg_section,
+                                number, &zero_address_frag);
+
+  err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
+  if (err)
+    as_fatal ("Inserting \"%s\" into register table failed: %s",
+             name, err);
+}
 
-  if ((0x3 == opcode) & (s_class & SYNTAX_3OP))
-    {
-      as_bad (_("opcode 0x3 and SYNTAX_3OP invalid"));
-      ignore_rest_of_line ();
-      return;
-    }
+/* Construct symbols for each of the general registers.  */
 
-  switch (suffixcode)
+static void
+declare_register_set (void)
+{
+  int i;
+  for (i = 0; i < 32; ++i)
     {
-    case 0:
-      strcat (syntax, "%.q%.f ");
-      break;
-    case 1:
-      strcat (syntax, "%.f ");
-      break;
-    case 2:
-      strcat (syntax, "%.q ");
-      break;
-    case 3:
-      strcat (syntax, " ");
-      break;
-    default:
-      as_bad (_("unknown suffix class"));
-      ignore_rest_of_line ();
-      return;
-      break;
-    };
-
-  strcat (syntax, ((opcode == 0x3) ? "%a,%b" : ((s_class & SYNTAX_3OP) ? "%a,%b,%c" : "%b,%c")));
-  if (suffixcode < 2)
-    strcat (syntax, "%F");
-  strcat (syntax, "%S%L");
-
-  ext_op = (struct arc_opcode *) xmalloc (sizeof (struct arc_opcode));
-  ext_op->syntax = xstrdup (syntax);
-
-  ext_op->mask  = I (-1) | ((0x3 == opcode) ? C (-1) : 0);
-  ext_op->value = I (opcode) | ((0x3 == opcode) ? C (subopcode) : 0);
-  ext_op->flags = s_class;
-  ext_op->next_asm = arc_ext_opcodes;
-  ext_op->next_dis = arc_ext_opcodes;
-  arc_ext_opcodes = ext_op;
-
-  /* OK, now that we know what this inst is, put a description in the
-     arc extension section of the output file.  */
-
-  old_sec    = now_seg;
-  old_subsec = now_subseg;
-
-  arc_set_ext_seg ();
-
-  p = frag_more (1);
-  *p = 5 + name_len + 1;
-  p = frag_more (1);
-  *p = EXT_INSTRUCTION;
-  p = frag_more (1);
-  *p = opcode;
-  p = frag_more (1);
-  *p = subopcode;
-  p = frag_more (1);
-  *p = (s_class & (OP1_MUST_BE_IMM | OP1_IMM_IMPLIED) ? IGNORE_FIRST_OPD : 0);
-  p = frag_more (name_len);
-  strncpy (p, syntax, name_len);
-  p = frag_more (1);
-  *p = '\0';
-
-  subseg_set (old_sec, old_subsec);
+      char name[7];
 
-  demand_empty_rest_of_line ();
+      sprintf (name, "r%d", i);
+      declare_register (name, i);
+      if ((i & 0x01) == 0)
+       {
+         sprintf (name, "r%dr%d", i, i+1);
+         declare_register (name, i);
+       }
+    }
 }
 
-static void
-arc_common (int localScope)
+/* Port-specific assembler initialization.  This function is called
+   once, at assembler startup time.  */
+
+void
+md_begin (void)
 {
-  char *name;
-  char c;
-  char *p;
-  int align, size;
-  symbolS *symbolP;
-
-  c = get_symbol_name (&name);
-  /* just after name is now '\0'  */
-  p = input_line_pointer;
-  (void) restore_line_pointer (c);
-  SKIP_WHITESPACE ();
+  unsigned int i;
 
-  if (*input_line_pointer != ',')
-    {
-      as_bad (_("expected comma after symbol name"));
-      ignore_rest_of_line ();
-      return;
-    }
+  /* The endianness can be chosen "at the factory".  */
+  target_big_endian = byte_order == BIG_ENDIAN;
 
-  input_line_pointer++;                /* skip ','  */
-  size = get_absolute_expression ();
+  if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
+    as_warn (_("could not set architecture and machine"));
 
-  if (size < 0)
-    {
-      as_bad (_("negative symbol length"));
-      ignore_rest_of_line ();
-      return;
-    }
+  /* Set elf header flags.  */
+  bfd_set_private_flags (stdoutput, arc_eflag);
 
-  *p = 0;
-  symbolP = symbol_find_or_make (name);
-  *p = c;
+  /* Set up a hash table for the instructions.  */
+  arc_opcode_hash = hash_new ();
+  if (arc_opcode_hash == NULL)
+    as_fatal (_("Virtual memory exhausted"));
 
-  if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
-    {
-      as_bad (_("ignoring attempt to re-define symbol"));
-      ignore_rest_of_line ();
-      return;
-    }
-  if (((int) S_GET_VALUE (symbolP) != 0) \
-      && ((int) S_GET_VALUE (symbolP) != size))
+  /* Initialize the hash table with the insns.  */
+  for (i = 0; i < arc_num_opcodes;)
     {
-      as_warn (_("length of symbol \"%s\" already %ld, ignoring %d"),
-              S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
-    }
-  gas_assert (symbolP->sy_frag == &zero_address_frag);
+      const char *name, *retval;
 
-  /* Now parse the alignment field.  This field is optional for
-     local and global symbols. Default alignment is zero.  */
-  if (*input_line_pointer == ',')
-    {
-      input_line_pointer++;
-      align = get_absolute_expression ();
-      if (align < 0)
-       {
-         align = 0;
-         as_warn (_("assuming symbol alignment of zero"));
-       }
-    }
-  else
-    align = 0;
+      name = arc_opcodes[i].name;
+      retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]);
+      if (retval)
+       as_fatal (_("internal error: can't hash opcode '%s': %s"),
+                 name, retval);
 
-  if (localScope != 0)
-    {
-      segT old_sec;
-      int old_subsec;
-      char *pfrag;
-
-      old_sec    = now_seg;
-      old_subsec = now_subseg;
-      record_alignment (bss_section, align);
-      subseg_set (bss_section, 0);  /* ??? subseg_set (bss_section, 1); ???  */
-
-      if (align)
-       /* Do alignment.  */
-       frag_align (align, 0, 0);
-
-      /* Detach from old frag.  */
-      if (S_GET_SEGMENT (symbolP) == bss_section)
-       symbolP->sy_frag->fr_symbol = NULL;
-
-      symbolP->sy_frag = frag_now;
-      pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
-                       (offsetT) size, (char *) 0);
-      *pfrag = 0;
-
-      S_SET_SIZE       (symbolP, size);
-      S_SET_SEGMENT    (symbolP, bss_section);
-      S_CLEAR_EXTERNAL (symbolP);
-      symbol_get_obj (symbolP)->local = 1;
-      subseg_set (old_sec, old_subsec);
-    }
-  else
-    {
-      S_SET_VALUE    (symbolP, (valueT) size);
-      S_SET_ALIGN    (symbolP, align);
-      S_SET_EXTERNAL (symbolP);
-      S_SET_SEGMENT  (symbolP, bfd_com_section_ptr);
+      while (++i < arc_num_opcodes
+            && (arc_opcodes[i].name == name
+                || !strcmp (arc_opcodes[i].name, name)))
+       continue;
     }
 
-  symbolP->bsym->flags |= BSF_OBJECT;
-
-  demand_empty_rest_of_line ();
-}
-\f
-/* Select the cpu we're assembling for.  */
-
-static void
-arc_option (int ignore ATTRIBUTE_UNUSED)
-{
-  extern int arc_get_mach (char *);
-  int mach;
-  char c;
-  char *cpu;
+  /* Register declaration.  */
+  arc_reg_hash = hash_new ();
+  if (arc_reg_hash == NULL)
+    as_fatal (_("Virtual memory exhausted"));
 
-  c = get_symbol_name (&cpu);
-  mach = arc_get_mach (cpu);
-  (void) restore_line_pointer (c);
+  declare_register_set ();
+  declare_register ("gp", 26);
+  declare_register ("fp", 27);
+  declare_register ("sp", 28);
+  declare_register ("ilink", 29);
+  declare_register ("ilink1", 29);
+  declare_register ("ilink2", 30);
+  declare_register ("blink", 31);
 
-  /* If an instruction has already been seen, it's too late.  */
-  if (cpu_tables_init_p)
-    {
-      as_bad (_("\".option\" directive must appear before any instructions"));
-      ignore_rest_of_line ();
-      return;
-    }
+  declare_register ("mlo", 57);
+  declare_register ("mmid", 58);
+  declare_register ("mhi", 59);
 
-  if (mach == -1)
-    goto bad_cpu;
+  declare_register ("acc1", 56);
+  declare_register ("acc2", 57);
 
-  if (mach_type_specified_p && mach != arc_mach_type)
-    {
-      as_bad (_("\".option\" directive conflicts with initial definition"));
-      ignore_rest_of_line ();
-      return;
-    }
-  else
-    {
-      /* The cpu may have been selected on the command line.  */
-      if (mach != arc_mach_type)
-       as_warn (_("\".option\" directive overrides command-line (default) value"));
-      arc_mach_type = mach;
-      if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
-       as_fatal (_("could not set architecture and machine"));
-      mach_type_specified_p = 1;
-    }
-  demand_empty_rest_of_line ();
-  return;
+  declare_register ("lp_count", 60);
+  declare_register ("pcl", 63);
 
- bad_cpu:
-  as_bad (_("invalid identifier for \".option\""));
-  ignore_rest_of_line ();
-}
-\f
-char *
-md_atof (int type, char *litP, int *sizeP)
-{
-  return ieee_md_atof (type, litP, sizeP, TRUE);
+  /* Initialize the last instructions.  */
+  memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
 }
 
 /* Write a value out to the object file, using the appropriate
    endianness.  */
 
 void
-md_number_to_chars (char *buf, valueT val, int n)
+md_number_to_chars (char *buf,
+                   valueT val,
+                   int n)
 {
   if (target_big_endian)
     number_to_chars_bigendian (buf, val, n);
@@ -1016,878 +1036,2108 @@ md_number_to_chars (char *buf, valueT val, int n)
 /* Round up a section size to the appropriate boundary.  */
 
 valueT
-md_section_align (segT segment, valueT size)
+md_section_align (segT segment,
+                 valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
 
   return ((size + (1 << align) - 1) & (-1 << align));
 }
 
-/* We don't have any form of relaxing.  */
+/* The location from which a PC relative jump should be calculated,
+   given a PC relative reloc.  */
 
-int
-md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
-                              asection *seg ATTRIBUTE_UNUSED)
+long
+md_pcrel_from_section (fixS *fixP,
+                      segT sec)
 {
-  as_fatal (_("relaxation not supported\n"));
-  return 1;
-}
-
-/* Convert a machine dependent frag.  We never generate these.  */
+  offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
 
-void
-md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
-                asection *sec ATTRIBUTE_UNUSED,
-                fragS *fragp ATTRIBUTE_UNUSED)
-{
-  abort ();
-}
+  pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
 
-static void
-arc_code_symbol (expressionS *expressionP)
-{
-  if (expressionP->X_op == O_symbol && expressionP->X_add_number == 0)
-    {
-      expressionS two;
-
-      expressionP->X_op = O_right_shift;
-      expressionP->X_add_symbol->sy_value.X_op = O_constant;
-      two.X_op = O_constant;
-      two.X_add_symbol = two.X_op_symbol = NULL;
-      two.X_add_number = 2;
-      expressionP->X_op_symbol = make_expr_symbol (&two);
-    }
-  /* Allow %st(sym1-sym2)  */
-  else if (expressionP->X_op == O_subtract
-          && expressionP->X_add_symbol != NULL
-          && expressionP->X_op_symbol != NULL
-          && expressionP->X_add_number == 0)
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (!S_IS_DEFINED (fixP->fx_addsy)
+         || S_GET_SEGMENT (fixP->fx_addsy) != sec))
     {
-      expressionS two;
-
-      expressionP->X_add_symbol = make_expr_symbol (expressionP);
-      expressionP->X_op = O_right_shift;
-      two.X_op = O_constant;
-      two.X_add_symbol = two.X_op_symbol = NULL;
-      two.X_add_number = 2;
-      expressionP->X_op_symbol = make_expr_symbol (&two);
-    }
-  else
-    as_bad (_("expression too complex code symbol"));
-}
-
-/* Parse an operand that is machine-specific.
-
-   The ARC has a special %-op to adjust addresses so they're usable in
-   branches.  The "st" is short for the STatus register.
-   ??? Later expand this to take a flags value too.
-
-   ??? We can't create new expression types so we map the %-op's onto the
-   existing syntax.  This means that the user could use the chosen syntax
-   to achieve the same effect.  */
-
-void
-md_operand (expressionS *expressionP)
-{
-  char *p = input_line_pointer;
+      pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
 
-  if (*p != '%')
-    return;
+      /* The symbol is undefined (or is defined but not in this section).
+        Let the linker figure it out.  */
+      return 0;
+    }
 
-  if (strncmp (p, "%st(", 4) == 0)
+  if ((int) fixP->fx_r_type < 0)
     {
-      input_line_pointer += 4;
-      expression (expressionP);
-      if (*input_line_pointer != ')')
-       {
-         as_bad (_("missing ')' in %%-op"));
-         return;
-       }
-      ++input_line_pointer;
-      arc_code_symbol (expressionP);
+      /* These are the "internal" relocations.  Align them to
+        32 bit boundary (PCL), for the moment.  */
+      base &= ~3;
     }
   else
     {
-      /* It could be a register.  */
-      int i, l;
-      struct arc_ext_operand_value *ext_oper = arc_ext_operands;
-      p++;
-
-      while (ext_oper)
-       {
-         l = strlen (ext_oper->operand.name);
-         if (!strncmp (p, ext_oper->operand.name, l) && !ISALNUM (*(p + l)))
-           {
-             input_line_pointer += l + 1;
-             expressionP->X_op = O_register;
-             expressionP->X_add_number = (offsetT) &ext_oper->operand;
-             return;
-           }
-         ext_oper = ext_oper->next;
-       }
-      for (i = 0; i < arc_reg_names_count; i++)
+      switch (fixP->fx_r_type)
        {
-         l = strlen (arc_reg_names[i].name);
-         if (!strncmp (p, arc_reg_names[i].name, l) && !ISALNUM (*(p + l)))
-           {
-             input_line_pointer += l + 1;
-             expressionP->X_op = O_register;
-             expressionP->X_add_number = (offsetT) &arc_reg_names[i];
-             break;
-           }
+       case BFD_RELOC_ARC_PC32:
+         /* The hardware calculates relative to the start of the
+            insn, but this relocation is relative to location of the
+            LIMM, compensate.  TIP: the base always needs to be
+            substracted by 4 as we do not support this type of PCrel
+            relocation for short instructions.  */
+         base -= fixP->fx_where - fixP->fx_dot_value;
+         gas_assert ((fixP->fx_where - fixP->fx_dot_value) == 4);
+         /* Fall through.  */
+       case BFD_RELOC_ARC_PLT32:
+       case BFD_RELOC_ARC_S25H_PCREL_PLT:
+       case BFD_RELOC_ARC_S21H_PCREL_PLT:
+       case BFD_RELOC_ARC_S25W_PCREL_PLT:
+       case BFD_RELOC_ARC_S21W_PCREL_PLT:
+
+       case BFD_RELOC_ARC_S21H_PCREL:
+       case BFD_RELOC_ARC_S25H_PCREL:
+       case BFD_RELOC_ARC_S13_PCREL:
+       case BFD_RELOC_ARC_S21W_PCREL:
+       case BFD_RELOC_ARC_S25W_PCREL:
+         base &= ~3;
+         break;
+       default:
+         as_bad_where (fixP->fx_file, fixP->fx_line,
+                       _("unhandled reloc %s in md_pcrel_from_section"),
+                 bfd_get_reloc_code_name (fixP->fx_r_type));
+         break;
        }
     }
-}
-
-/* We have no need to default values of symbols.
-   We could catch register names here, but that is handled by inserting
-   them all in the symbol table to begin with.  */
-
-symbolS *
-md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-\f
-/* Functions concerning expressions.  */
-
-/* Parse a .byte, .word, etc. expression.
-
-   Values for the status register are specified with %st(label).
-   `label' will be right shifted by 2.  */
 
-bfd_reloc_code_real_type
-arc_parse_cons_expression (expressionS *exp,
-                          unsigned int nbytes ATTRIBUTE_UNUSED)
-{
-  char *p = input_line_pointer;
-  int code_symbol_fix = 0;
+  pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
+           fixP->fx_frag->fr_address, fixP->fx_where, base,
+           fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
+           fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
 
-  for (; ! is_end_of_line[(unsigned char) *p]; p++)
-    if (*p == '@' && !strncmp (p, "@h30", 4))
-      {
-       code_symbol_fix = 1;
-       strcpy (p, ";   ");
-      }
-  expression_and_evaluate (exp);
-  if (code_symbol_fix)
-    {
-      arc_code_symbol (exp);
-      input_line_pointer = p;
-    }
-  return BFD_RELOC_NONE;
+  return base;
 }
 
-/* Record a fixup for a cons expression.  */
+/* Given a BFD relocation find the coresponding operand.  */
 
-void
-arc_cons_fix_new (fragS *frag,
-                 int where,
-                 int nbytes,
-                 expressionS *exp,
-                 bfd_reloc_code_real_type r ATTRIBUTE_UNUSED)
+static const struct arc_operand *
+find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
 {
-  if (nbytes == 4)
-    {
-      int reloc_type;
-      expressionS exptmp;
-
-      /* This may be a special ARC reloc (eg: %st()).  */
-      reloc_type = get_arc_exp_reloc_type (1, BFD_RELOC_32, exp, &exptmp);
-      fix_new_exp (frag, where, nbytes, &exptmp, 0,
-                   (enum bfd_reloc_code_real) reloc_type);
-    }
-  else
-    {
-      fix_new_exp (frag, where, nbytes, exp, 0,
-                  nbytes == 2 ? BFD_RELOC_16
-                  : nbytes == 8 ? BFD_RELOC_64
-                  : BFD_RELOC_32);
-    }
-}
-\f
-/* Functions concerning relocs.  */
+  unsigned i;
 
-/* The location from which a PC relative jump should be calculated,
-   given a PC relative reloc.  */
-
-long
-md_pcrel_from (fixS *fixP)
-{
-  /* Return the address of the delay slot.  */
-  return fixP->fx_frag->fr_address + fixP->fx_where + fixP->fx_size;
+  for (i = 0; i < arc_num_operands; i++)
+    if (arc_operands[i].default_reloc == reloc)
+      return  &arc_operands[i];
+  return NULL;
 }
 
-/* Apply a fixup to the object code.  This is called for all the
-   fixups we generated by the call to fix_new_exp, above.  In the call
-   above we used a reloc code which was the largest legal reloc code
-   plus the operand index.  Here we undo that to recover the operand
-   index.  At this point all symbol values should be fully resolved,
-   and we attempt to completely resolve the reloc.  If we can not do
-   that, we determine the correct reloc code and put it back in the fixup.  */
+/* Apply a fixup to the object code.  At this point all symbol values
+   should be fully resolved, and we attempt to completely resolve the
+   reloc.  If we can not do that, we determine the correct reloc code
+   and put it back in the fixup.  To indicate that a fixup has been
+   eliminated, set fixP->fx_done.  */
 
 void
-md_apply_fix (fixS *fixP, valueT * valP, segT seg)
+md_apply_fix (fixS *fixP,
+             valueT *valP,
+             segT seg)
 {
-  valueT value = * valP;
-
-  if (fixP->fx_addsy == (symbolS *) NULL)
-    fixP->fx_done = 1;
-
-  else if (fixP->fx_pcrel)
+  char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
+  valueT value = *valP;
+  unsigned insn = 0;
+  symbolS *fx_addsy, *fx_subsy;
+  offsetT fx_offset;
+  segT add_symbol_segment = absolute_section;
+  segT sub_symbol_segment = absolute_section;
+  const struct arc_operand *operand = NULL;
+  extended_bfd_reloc_code_real_type reloc;
+
+  pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
+           fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
+           ((int) fixP->fx_r_type < 0) ? "Internal":
+           bfd_get_reloc_code_name (fixP->fx_r_type), value,
+           fixP->fx_offset);
+
+  fx_addsy = fixP->fx_addsy;
+  fx_subsy = fixP->fx_subsy;
+  fx_offset = 0;
+
+  if (fx_addsy)
     {
-      /* Hack around bfd_install_relocation brain damage.  */
-      if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
-       value += md_pcrel_from (fixP);
+      add_symbol_segment = S_GET_SEGMENT (fx_addsy);
     }
 
-  /* We can't actually support subtracting a symbol.  */
-  if (fixP->fx_subsy != NULL)
-    as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
-
-  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+  if (fx_subsy
+      && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
+      && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
+      && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
     {
-      int opindex;
-      const struct arc_operand *operand;
-      char *where;
-      arc_insn insn;
-
-      opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
-
-      operand = &arc_operands[opindex];
-
-      /* Fetch the instruction, insert the fully resolved operand
-        value, and stuff the instruction back again.  */
-      where = fixP->fx_frag->fr_literal + fixP->fx_where;
-      if (target_big_endian)
-       insn = bfd_getb32 ((unsigned char *) where);
-      else
-       insn = bfd_getl32 ((unsigned char *) where);
-      insn = arc_insert_operand (insn, operand, -1, NULL, (offsetT) value,
-                                fixP->fx_file, fixP->fx_line);
-      if (target_big_endian)
-       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
-      else
-       bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
-
-      if (fixP->fx_done)
-       /* Nothing else to do here.  */
-       return;
+      resolve_symbol_value (fx_subsy);
+      sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
 
-      /* Determine a BFD reloc value based on the operand information.
-        We are only prepared to turn a few of the operands into relocs.
-        !!! Note that we can't handle limm values here.  Since we're using
-        implicit addends the addend must be inserted into the instruction,
-        however, the opcode insertion routines currently do nothing with
-        limm values.  */
-      if (operand->fmt == 'B')
+      if (sub_symbol_segment == absolute_section)
        {
-         gas_assert ((operand->flags & ARC_OPERAND_RELATIVE_BRANCH) != 0
-                 && operand->bits == 20
-                 && operand->shift == 7);
-         fixP->fx_r_type = BFD_RELOC_ARC_B22_PCREL;
+         /* The symbol is really a constant.  */
+         fx_offset -= S_GET_VALUE (fx_subsy);
+         fx_subsy = NULL;
        }
-      else if (operand->fmt == 'J')
+      else
        {
-         gas_assert ((operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) != 0
-                 && operand->bits == 24
-                 && operand->shift == 32);
-         fixP->fx_r_type = BFD_RELOC_ARC_B26;
+         as_bad_where (fixP->fx_file, fixP->fx_line,
+                       _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+                       fx_addsy ? S_GET_NAME (fx_addsy) : "0",
+                       segment_name (add_symbol_segment),
+                       S_GET_NAME (fx_subsy),
+                       segment_name (sub_symbol_segment));
+         return;
        }
-      else if (operand->fmt == 'L')
+    }
+
+  if (fx_addsy
+      && !S_IS_WEAK (fx_addsy))
+    {
+      if (add_symbol_segment == seg
+         && fixP->fx_pcrel)
        {
-         gas_assert ((operand->flags & ARC_OPERAND_LIMM) != 0
-                 && operand->bits == 32
-                 && operand->shift == 32);
-         fixP->fx_r_type = BFD_RELOC_32;
+         value += S_GET_VALUE (fx_addsy);
+         value -= md_pcrel_from_section (fixP, seg);
+         fx_addsy = NULL;
+         fixP->fx_pcrel = FALSE;
        }
-      else
+      else if (add_symbol_segment == absolute_section)
        {
-         as_bad_where (fixP->fx_file, fixP->fx_line,
-                       _("unresolved expression that must be resolved"));
-         fixP->fx_done = 1;
-         return;
+         value = fixP->fx_offset;
+         fx_offset += S_GET_VALUE (fixP->fx_addsy);
+         fx_addsy = NULL;
+         fixP->fx_pcrel = FALSE;
        }
     }
-  else
+
+  if (!fx_addsy)
+    fixP->fx_done = TRUE;
+
+  if (fixP->fx_pcrel)
     {
+      if (fx_addsy
+         && ((S_IS_DEFINED (fx_addsy)
+              && S_GET_SEGMENT (fx_addsy) != seg)
+             || S_IS_WEAK (fx_addsy)))
+       value += md_pcrel_from_section (fixP, seg);
+
       switch (fixP->fx_r_type)
        {
-       case BFD_RELOC_8:
-         md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
-                             value, 1);
-         break;
-       case BFD_RELOC_16:
-         md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
-                             value, 2);
-         break;
+       case BFD_RELOC_ARC_32_ME:
+         /* This is a pc-relative value in a LIMM.  Adjust it to the
+            address of the instruction not to the address of the
+            LIMM.  Note: it is not anylonger valid this afirmation as
+            the linker consider ARC_PC32 a fixup to entire 64 bit
+            insn.  */
+         fixP->fx_offset += fixP->fx_frag->fr_address;
+         /* Fall through.  */
        case BFD_RELOC_32:
-         md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
-                             value, 4);
-         break;
-       case BFD_RELOC_ARC_B26:
-         /* If !fixP->fx_done then `value' is an implicit addend.
-            We must shift it right by 2 in this case as well because the
-            linker performs the relocation and then adds this in (as opposed
-            to adding this in and then shifting right by 2).  */
-         value >>= 2;
-         md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
-                             value, 4);
+         fixP->fx_r_type = BFD_RELOC_ARC_PC32;
+         /* Fall through.  */
+       case BFD_RELOC_ARC_PC32:
          break;
        default:
-         abort ();
+         if ((int) fixP->fx_r_type < 0)
+           as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
+                     fixP->fx_r_type);
+         break;
        }
     }
-}
 
-/* Translate internal representation of relocation info to BFD target
-   format.  */
+  pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
+           fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
+           ((int) fixP->fx_r_type < 0) ? "Internal":
+           bfd_get_reloc_code_name (fixP->fx_r_type), value,
+           fixP->fx_offset);
 
-arelent *
-tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
-             fixS *fixP)
-{
-  arelent *reloc;
+  if (!fixP->fx_done)
+    return;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  /* Addjust the value if we have a constant.  */
+  value += fx_offset;
 
-  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
-  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
-  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
-  if (reloc->howto == (reloc_howto_type *) NULL)
+  /* For hosts with longs bigger than 32-bits make sure that the top
+     bits of a 32-bit negative value read in by the parser are set,
+     so that the correct comparisons are made.  */
+  if (value & 0x80000000)
+    value |= (-1L << 31);
+
+  reloc = fixP->fx_r_type;
+  switch (reloc)
     {
-      as_bad_where (fixP->fx_file, fixP->fx_line,
-                   _("internal error: can't export reloc type %d (`%s')"),
-                   fixP->fx_r_type,
+    case BFD_RELOC_8:
+    case BFD_RELOC_16:
+    case BFD_RELOC_24:
+    case BFD_RELOC_32:
+    case BFD_RELOC_64:
+      md_number_to_chars (fixpos, value, fixP->fx_size);
+      return;
+
+    case BFD_RELOC_ARC_GOTPC32:
+      /* I cannot fix an GOTPC relocation because I need to relax it
+        from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc.  */
+      as_bad (_("Unsupported operation on reloc"));
+      return;
+    case BFD_RELOC_ARC_GOTOFF:
+    case BFD_RELOC_ARC_32_ME:
+    case BFD_RELOC_ARC_PC32:
+      md_number_to_chars_midend (fixpos, value, fixP->fx_size);
+      return;
+
+    case BFD_RELOC_ARC_PLT32:
+      md_number_to_chars_midend (fixpos, value, fixP->fx_size);
+      return;
+
+    case BFD_RELOC_ARC_S25H_PCREL_PLT:
+      reloc = BFD_RELOC_ARC_S25W_PCREL;
+      goto solve_plt;
+
+    case BFD_RELOC_ARC_S21H_PCREL_PLT:
+      reloc = BFD_RELOC_ARC_S21H_PCREL;
+      goto solve_plt;
+
+    case BFD_RELOC_ARC_S25W_PCREL_PLT:
+      reloc = BFD_RELOC_ARC_S25W_PCREL;
+      goto solve_plt;
+
+    case BFD_RELOC_ARC_S21W_PCREL_PLT:
+      reloc = BFD_RELOC_ARC_S21W_PCREL;
+
+    case BFD_RELOC_ARC_S25W_PCREL:
+    case BFD_RELOC_ARC_S21W_PCREL:
+    case BFD_RELOC_ARC_S21H_PCREL:
+    case BFD_RELOC_ARC_S25H_PCREL:
+    case BFD_RELOC_ARC_S13_PCREL:
+    solve_plt:
+      operand = find_operand_for_reloc (reloc);
+      gas_assert (operand);
+      break;
+
+    case BFD_RELOC_ARC_TLS_DTPOFF:
+    case BFD_RELOC_ARC_TLS_LE_32:
+      if (fixP->fx_done)
+       {
+         gas_assert (!fixP->fx_addsy);
+         gas_assert (!fixP->fx_subsy);
+         md_number_to_chars_midend (fixpos, value, fixP->fx_size);
+         return;
+       }
+      else
+       {
+         value = fixP->fx_offset;
+         fixP->fx_offset = 0;
+       }
+      /* Fall through.  */
+    case BFD_RELOC_ARC_TLS_GD_GOT:
+    case BFD_RELOC_ARC_TLS_IE_GOT:
+      S_SET_THREAD_LOCAL (fixP->fx_addsy);
+      md_number_to_chars_midend (fixpos, value, fixP->fx_size);
+      return;
+
+    case BFD_RELOC_ARC_TLS_GD_LD:
+      gas_assert (!fixP->fx_offset);
+      if (fixP->fx_subsy)
+       fixP->fx_offset
+         = (S_GET_VALUE (fixP->fx_subsy)
+            - fixP->fx_frag->fr_address- fixP->fx_where);
+      fixP->fx_subsy = NULL;
+      /* Fall through.  */
+    case BFD_RELOC_ARC_TLS_GD_CALL:
+      /* These two relocs are there just to allow ld to change the tls
+        model for this symbol, by patching the code.  */
+      /* Fall through.  */
+      /* The offset - and scale, if any - will be installed by the
+        linker.  */
+      gas_assert (!fixP->fx_done);
+      S_SET_THREAD_LOCAL (fixP->fx_addsy);
+      return;
+
+    case BFD_RELOC_ARC_TLS_LE_S9:
+    case BFD_RELOC_ARC_TLS_DTPOFF_S9:
+      as_bad (_("TLS_*_S9 relocs are not supported yet"));
+      break;
+
+    default:
+      {
+       if ((int) fixP->fx_r_type >= 0)
+         as_fatal (_("unhandled relocation type %s"),
                    bfd_get_reloc_code_name (fixP->fx_r_type));
+
+       /* The rest of these fixups needs to be completely resolved as
+          constants.  */
+       if (fixP->fx_addsy != 0
+           && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
+         as_bad_where (fixP->fx_file, fixP->fx_line,
+                       _("non-absolute expression in constant field"));
+
+       gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
+       operand = &arc_operands[-(int) fixP->fx_r_type];
+       break;
+      }
+    }
+
+  if (target_big_endian)
+    {
+      switch (fixP->fx_size)
+       {
+       case 4:
+         insn = bfd_getb32 (fixpos);
+         break;
+       case 2:
+         insn = bfd_getb16 (fixpos);
+         break;
+       default:
+         as_bad_where (fixP->fx_file, fixP->fx_line,
+                       _("unknown fixup size"));
+       }
+    }
+  else
+    {
+      insn = 0;
+      switch (fixP->fx_size)
+       {
+       case 4:
+         insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
+         break;
+       case 2:
+         insn = bfd_getl16 (fixpos);
+         break;
+       default:
+         as_bad_where (fixP->fx_file, fixP->fx_line,
+                       _("unknown fixup size"));
+       }
+    }
+
+  insn = insert_operand (insn, operand, (offsetT) value,
+                        fixP->fx_file, fixP->fx_line);
+
+  md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
+}
+
+/* Prepare machine-dependent frags for relaxation.
+
+   Called just before relaxation starts.  Any symbol that is now undefined
+   will not become defined.
+
+   Return the correct fr_subtype in the frag.
+
+   Return the initial "guess for fr_var" to caller.  The guess for fr_var
+   is *actually* the growth beyond fr_fix.  Whatever we do to grow fr_fix
+   or fr_var contributes to our returned value.
+
+   Although it may not be explicit in the frag, pretend
+   fr_var starts with a value.  */
+
+int
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+                              segT segment ATTRIBUTE_UNUSED)
+{
+  int growth = 4;
+
+  fragP->fr_var = 4;
+  pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
+          fragP->fr_file, fragP->fr_line, growth);
+
+  as_fatal (_("md_estimate_size_before_relax\n"));
+  return growth;
+}
+
+/* Translate internal representation of relocation info to BFD target
+   format.  */
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
+             fixS *fixP)
+{
+  arelent *reloc;
+  bfd_reloc_code_real_type code;
+
+  reloc = (arelent *) xmalloc (sizeof (* reloc));
+  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+
+  /* Make sure none of our internal relocations make it this far.
+     They'd better have been fully resolved by this point.  */
+  gas_assert ((int) fixP->fx_r_type > 0);
+
+  code = fixP->fx_r_type;
+
+  /* if we have something like add gp, pcl,
+     _GLOBAL_OFFSET_TABLE_@gotpc.  */
+  if (code == BFD_RELOC_ARC_GOTPC32
+      && GOT_symbol
+      && fixP->fx_addsy == GOT_symbol)
+    code = BFD_RELOC_ARC_GOTPC;
+
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+                   _("cannot represent `%s' relocation in object file"),
+                   bfd_get_reloc_code_name (code));
       return NULL;
     }
 
-  gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+  if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
+    as_fatal (_("internal error? cannot generate `%s' relocation"),
+             bfd_get_reloc_code_name (code));
 
-  /* Set addend to account for PC being advanced one insn before the
-     target address is computed.  */
+  gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
 
-  reloc->addend = (fixP->fx_pcrel ? -4 : 0);
+  if (code == BFD_RELOC_ARC_TLS_DTPOFF
+      || code ==  BFD_RELOC_ARC_TLS_DTPOFF_S9)
+    {
+      asymbol *sym
+       = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
+      /* We just want to store a 24 bit index, but we have to wait
+        till after write_contents has been called via
+        bfd_map_over_sections before we can get the index from
+        _bfd_elf_symbol_from_bfd_symbol.  Thus, the write_relocs
+        function is elf32-arc.c has to pick up the slack.
+        Unfortunately, this leads to problems with hosts that have
+        pointers wider than long (bfd_vma).  There would be various
+        ways to handle this, all error-prone :-(  */
+      reloc->addend = (bfd_vma) sym;
+      if ((asymbol *) reloc->addend != sym)
+       {
+         as_bad ("Can't store pointer\n");
+         return NULL;
+       }
+    }
+  else
+    reloc->addend = fixP->fx_offset;
 
   return reloc;
 }
 
-const pseudo_typeS md_pseudo_table[] =
-{
-  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
-  { "comm", arc_common, 0 },
-  { "common", arc_common, 0 },
-  { "lcomm", arc_common, 1 },
-  { "lcommon", arc_common, 1 },
-  { "2byte", cons, 2 },
-  { "half", cons, 2 },
-  { "short", cons, 2 },
-  { "3byte", cons, 3 },
-  { "4byte", cons, 4 },
-  { "word", cons, 4 },
-  { "option", arc_option, 0 },
-  { "cpu", arc_option, 0 },
-  { "block", s_space, 0 },
-  { "extcondcode", arc_extoper, 0 },
-  { "extcoreregister", arc_extoper, 1 },
-  { "extauxregister", arc_extoper, 2 },
-  { "extinstruction", arc_extinst, 0 },
-  { NULL, 0, 0 },
-};
+/* Perform post-processing of machine-dependent frags after relaxation.
+   Called after relaxation is finished.
+   In: Address of frag.
+   fr_type == rs_machine_dependent.
+   fr_subtype is what the address relaxed to.
 
-/* This routine is called for each instruction to be assembled.  */
+   Out: Any fixS:s and constants are set up.  */
 
 void
-md_assemble (char *str)
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+                segT segment ATTRIBUTE_UNUSED,
+                fragS *fragP ATTRIBUTE_UNUSED)
 {
-  const struct arc_opcode *opcode;
-  const struct arc_opcode *std_opcode;
-  struct arc_opcode *ext_opcode;
-  char *start;
-  const char *last_errmsg = 0;
-  arc_insn insn;
-  static int init_tables_p = 0;
-
-  /* Opcode table initialization is deferred until here because we have to
-     wait for a possible .option command.  */
-  if (!init_tables_p)
+  pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
+           fragP->fr_file, fragP->fr_line,
+           fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
+  abort ();
+}
+
+/* We have no need to default values of symbols.  We could catch
+   register names here, but that is handled by inserting them all in
+   the symbol table to begin with.  */
+
+symbolS *
+md_undefined_symbol (char *name)
+{
+  /* The arc abi demands that a GOT[0] should be referencible as
+     [pc+_DYNAMIC@gotpc].  Hence we convert a _DYNAMIC@gotpc to a
+     GOTPC reference to _GLOBAL_OFFSET_TABLE_.  */
+  if (((*name == '_')
+       && (*(name+1) == 'G')
+       && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
+      || ((*name == '_')
+         && (*(name+1) == 'D')
+         && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
     {
-      init_opcode_tables (arc_mach_type);
-      init_tables_p = 1;
+      if (!GOT_symbol)
+       {
+         if (symbol_find (name))
+           as_bad ("GOT already in symbol table");
+
+         GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
+                                  (valueT) 0, &zero_address_frag);
+       };
+      return GOT_symbol;
     }
+  return NULL;
+}
 
-  /* Skip leading white space.  */
-  while (ISSPACE (*str))
-    str++;
+/* Turn a string in input_line_pointer into a floating point constant
+   of type type, and store the appropriate bytes in *litP.  The number
+   of LITTLENUMS emitted is stored in *sizeP.  An error message is
+   returned, or NULL on OK.  */
 
-  /* The instructions are stored in lists hashed by the first letter (though
-     we needn't care how they're hashed).  Get the first in the list.  */
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  return ieee_md_atof (type, litP, sizeP, target_big_endian);
+}
 
-  ext_opcode = arc_ext_opcodes;
-  std_opcode = arc_opcode_lookup_asm (str);
+/* Called for any expression that can not be recognized.  When the
+   function is called, `input_line_pointer' will point to the start of
+   the expression.  */
 
-  /* Keep looking until we find a match.  */
-  start = str;
-  for (opcode = (ext_opcode ? ext_opcode : std_opcode);
-       opcode != NULL;
-       opcode = (ARC_OPCODE_NEXT_ASM (opcode)
-                ? ARC_OPCODE_NEXT_ASM (opcode)
-                : (ext_opcode ? ext_opcode = NULL, std_opcode : NULL)))
+void
+md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
+{
+  char *p = input_line_pointer;
+  if (*p == '@')
     {
-      int past_opcode_p, fc, num_suffixes;
-      int fix_up_at = 0;
-      char *syn;
-      struct arc_fixup fixups[MAX_FIXUPS];
-      /* Used as a sanity check.  If we need a limm reloc, make sure we ask
-        for an extra 4 bytes from frag_more.  */
-      int limm_reloc_p;
-      int ext_suffix_p;
-      const struct arc_operand_value *insn_suffixes[MAX_SUFFIXES];
-
-      /* Is this opcode supported by the selected cpu?  */
-      if (! arc_opcode_supported (opcode))
-       continue;
+      input_line_pointer++;
+      expressionP->X_op = O_symbol;
+      expression (expressionP);
+    }
+}
 
-      /* Scan the syntax string.  If it doesn't match, try the next one.  */
-      arc_opcode_init_insert ();
-      insn = opcode->value;
-      fc = 0;
-      past_opcode_p = 0;
-      num_suffixes = 0;
-      limm_reloc_p = 0;
-      ext_suffix_p = 0;
-
-      /* We don't check for (*str != '\0') here because we want to parse
-        any trailing fake arguments in the syntax string.  */
-      for (str = start, syn = opcode->syntax; *syn != '\0';)
-       {
-         int mods;
-         const struct arc_operand *operand;
+/* This function is called from the function 'expression', it attempts
+   to parse special names (in our case register names).  It fills in
+   the expression with the identified register.  It returns TRUE if
+   it is a register and FALSE otherwise.  */
 
-         /* Non operand chars must match exactly.  */
-         if (*syn != '%' || *++syn == '%')
-           {
-            if (*str == *syn)
-               {
-                 if (*syn == ' ')
-                   past_opcode_p = 1;
-                 ++syn;
-                 ++str;
-               }
-             else
-               break;
-             continue;
-           }
+bfd_boolean
+arc_parse_name (const char *name,
+               struct expressionS *e)
+{
+  struct symbol *sym;
 
-         /* We have an operand.  Pick out any modifiers.  */
-         mods = 0;
-         while (ARC_MOD_P (arc_operands[arc_operand_map[(int) *syn]].flags))
-           {
-             mods |= arc_operands[arc_operand_map[(int) *syn]].flags & ARC_MOD_BITS;
-             ++syn;
-           }
-         operand = arc_operands + arc_operand_map[(int) *syn];
-         if (operand->fmt == 0)
-           as_fatal (_("unknown syntax format character `%c'"), *syn);
+  if (!assembling_insn)
+    return FALSE;
 
-         if (operand->flags & ARC_OPERAND_FAKE)
-           {
-             const char *errmsg = NULL;
-             if (operand->insert)
-               {
-                 insn = (*operand->insert) (insn, operand, mods, NULL, 0, &errmsg);
-                 if (errmsg != (const char *) NULL)
-                   {
-                     last_errmsg = errmsg;
-                     if (operand->flags & ARC_OPERAND_ERROR)
-                       {
-                         as_bad ("%s", errmsg);
-                         return;
-                       }
-                     else if (operand->flags & ARC_OPERAND_WARN)
-                       as_warn ("%s", errmsg);
-                     break;
-                   }
-                 if (limm_reloc_p
-                     && (operand->flags && operand->flags & ARC_OPERAND_LIMM)
-                     && (operand->flags &
-                         (ARC_OPERAND_ABSOLUTE_BRANCH | ARC_OPERAND_ADDRESS)))
-                   {
-                     fixups[fix_up_at].opindex = arc_operand_map[operand->fmt];
-                   }
-               }
-             ++syn;
-           }
-         /* Are we finished with suffixes?  */
-         else if (!past_opcode_p)
-           {
-             int found;
-             char c;
-             char *s, *t;
-             const struct arc_operand_value *suf, *suffix_end;
-             const struct arc_operand_value *suffix = NULL;
-
-             if (!(operand->flags & ARC_OPERAND_SUFFIX))
-               abort ();
-
-             /* If we're at a space in the input string, we want to skip the
-                remaining suffixes.  There may be some fake ones though, so
-                just go on to try the next one.  */
-             if (*str == ' ')
-               {
-                 ++syn;
-                 continue;
-               }
+  /* Handle only registers.  */
+  if (e->X_op != O_absent)
+    return FALSE;
 
-             s = str;
-             if (mods & ARC_MOD_DOT)
-               {
-                 if (*s != '.')
-                   break;
-                 ++s;
-               }
-             else
-               {
-                 /* This can happen in "b.nd foo" and we're currently looking
-                    for "%q" (ie: a condition code suffix).  */
-                 if (*s == '.')
-                   {
-                     ++syn;
-                     continue;
-                   }
-               }
+  sym = hash_find (arc_reg_hash, name);
+  if (sym)
+    {
+      e->X_op = O_register;
+      e->X_add_number = S_GET_VALUE (sym);
+      return TRUE;
+    }
+  return FALSE;
+}
 
-             /* Pick the suffix out and look it up via the hash table.  */
-             for (t = s; *t && ISALNUM (*t); ++t)
-               continue;
-             c = *t;
-             *t = '\0';
-             if ((suf = get_ext_suffix (s)))
-               ext_suffix_p = 1;
-             else
-               suf = (const struct arc_operand_value *)
-                    hash_find (arc_suffix_hash, s);
-             if (!suf)
-               {
-                 /* This can happen in "blle foo" and we're currently using
-                    the template "b%q%.n %j".  The "bl" insn occurs later in
-                    the table so "lle" isn't an illegal suffix.  */
-                 *t = c;
-                 break;
-               }
+/* md_parse_option
+   Invocation line includes a switch not recognized by the base assembler.
+   See if it's a processor-specific option.
 
-             /* Is it the right type?  Note that the same character is used
-                several times, so we have to examine all of them.  This is
-                relatively efficient as equivalent entries are kept
-                together.  If it's not the right type, don't increment `str'
-                so we try the next one in the series.  */
-             found = 0;
-             if (ext_suffix_p && arc_operands[suf->type].fmt == *syn)
-               {
-                 /* Insert the suffix's value into the insn.  */
-                 *t = c;
-                 if (operand->insert)
-                   insn = (*operand->insert) (insn, operand,
-                                              mods, NULL, suf->value,
-                                              NULL);
-                 else
-                   insn |= suf->value << operand->shift;
-                 suffix = suf;
-                 str = t;
-                 found = 1;
-               }
-             else
-               {
-                 *t = c;
-                 suffix_end = arc_suffixes + arc_suffixes_count;
-                 for (suffix = suf;
-                      suffix < suffix_end && strcmp (suffix->name, suf->name) == 0;
-                      ++suffix)
-                   {
-                     if (arc_operands[suffix->type].fmt == *syn)
-                       {
-                         /* Insert the suffix's value into the insn.  */
-                         if (operand->insert)
-                           insn = (*operand->insert) (insn, operand,
-                                                      mods, NULL, suffix->value,
-                                                      NULL);
-                         else
-                           insn |= suffix->value << operand->shift;
-
-                         str = t;
-                         found = 1;
-                         break;
-                       }
-                   }
-               }
-             ++syn;
-             if (!found)
-               /* Wrong type.  Just go on to try next insn entry.  */
-               ;
-             else
-               {
-                 if (num_suffixes == MAX_SUFFIXES)
-                   as_bad (_("too many suffixes"));
-                 else
-                   insn_suffixes[num_suffixes++] = suffix;
-               }
-           }
-         else
-           /* This is either a register or an expression of some kind.  */
-           {
-             char *hold;
-             const struct arc_operand_value *reg = NULL;
-             long value = 0;
-             expressionS exp;
-
-             if (operand->flags & ARC_OPERAND_SUFFIX)
-               abort ();
-
-             /* Is there anything left to parse?
-                We don't check for this at the top because we want to parse
-                any trailing fake arguments in the syntax string.  */
-             if (is_end_of_line[(unsigned char) *str])
-               break;
+   New options (supported) are:
 
-             /* Parse the operand.  */
-             hold = input_line_pointer;
-             input_line_pointer = str;
-             expression (&exp);
-             str = input_line_pointer;
-             input_line_pointer = hold;
-
-             if (exp.X_op == O_illegal)
-               as_bad (_("illegal operand"));
-             else if (exp.X_op == O_absent)
-               as_bad (_("missing operand"));
-             else if (exp.X_op == O_constant)
-               value = exp.X_add_number;
-             else if (exp.X_op == O_register)
-               reg = (struct arc_operand_value *) exp.X_add_number;
-#define IS_REG_DEST_OPERAND(o) ((o) == 'a')
-             else if (IS_REG_DEST_OPERAND (*syn))
-               as_bad (_("symbol as destination register"));
-             else
-               {
-                 if (!strncmp (str, "@h30", 4))
-                   {
-                     arc_code_symbol (&exp);
-                     str += 4;
-                   }
-                 /* We need to generate a fixup for this expression.  */
-                 if (fc >= MAX_FIXUPS)
-                   as_fatal (_("too many fixups"));
-                 fixups[fc].exp = exp;
-                 /* We don't support shimm relocs. break here to force
-                    the assembler to output a limm.  */
-#define IS_REG_SHIMM_OFFSET(o) ((o) == 'd')
-                 if (IS_REG_SHIMM_OFFSET (*syn))
-                   break;
-                 /* If this is a register constant (IE: one whose
-                    register value gets stored as 61-63) then this
-                    must be a limm.  */
-                 /* ??? This bit could use some cleaning up.
-                    Referencing the format chars like this goes
-                    against style.  */
-                 if (IS_SYMBOL_OPERAND (*syn))
-                   {
-                     const char *junk;
-                     limm_reloc_p = 1;
-                     /* Save this, we don't yet know what reloc to use.  */
-                     fix_up_at = fc;
-                     /* Tell insert_reg we need a limm.  This is
-                        needed because the value at this point is
-                        zero, a shimm.  */
-                     /* ??? We need a cleaner interface than this.  */
-                     (*arc_operands[arc_operand_map['Q']].insert)
-                       (insn, operand, mods, reg, 0L, &junk);
-                   }
-                 else
-                   fixups[fc].opindex = arc_operand_map[(int) *syn];
-                 ++fc;
-                 value = 0;
-               }
+   -mcpu=<cpu name>             Assemble for selected processor
+   -EB/-mbig-endian             Big-endian
+   -EL/-mlittle-endian          Little-endian
 
-             /* Insert the register or expression into the instruction.  */
-             if (operand->insert)
-               {
-                 const char *errmsg = NULL;
-                 insn = (*operand->insert) (insn, operand, mods,
-                                            reg, (long) value, &errmsg);
-                 if (errmsg != (const char *) NULL)
-                   {
-                     last_errmsg = errmsg;
-                     if (operand->flags & ARC_OPERAND_ERROR)
-                       {
-                         as_bad ("%s", errmsg);
-                         return;
-                       }
-                     else if (operand->flags & ARC_OPERAND_WARN)
-                       as_warn ("%s", errmsg);
-                     break;
-                   }
-               }
-             else
-               insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+   The following CPU names are recognized:
+   arc700, av2em, av2hs.  */
 
-             ++syn;
-           }
-       }
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  int cpu_flags = EF_ARC_CPU_GENERIC;
 
-      /* If we're at the end of the syntax string, we're done.  */
-      /* FIXME: try to move this to a separate function.  */
-      if (*syn == '\0')
-       {
-         int i;
-         char *f;
-         long limm, limm_p;
+  switch (c)
+    {
+    case OPTION_ARC600:
+    case OPTION_ARC601:
+      return md_parse_option (OPTION_MCPU, "arc600");
+
+    case OPTION_ARC700:
+      return md_parse_option (OPTION_MCPU, "arc700");
 
-         /* For the moment we assume a valid `str' can only contain blanks
-            now.  IE: We needn't try again with a longer version of the
-            insn and it is assumed that longer versions of insns appear
-            before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+    case OPTION_ARCEM:
+      return md_parse_option (OPTION_MCPU, "arcem");
 
-         while (ISSPACE (*str))
-           ++str;
+    case OPTION_ARCHS:
+      return md_parse_option (OPTION_MCPU, "archs");
 
-         if (!is_end_of_line[(unsigned char) *str])
-           as_bad (_("junk at end of line: `%s'"), str);
+    case OPTION_MCPU:
+      {
+       int i;
+       char *s = alloca (strlen (arg) + 1);
 
-         /* Is there a limm value?  */
-         limm_p = arc_opcode_limm_p (&limm);
+       {
+         char *t = s;
+         char *arg1 = arg;
 
-         /* Perform various error and warning tests.  */
+         do
+           *t = TOLOWER (*arg1++);
+         while (*t++);
+       }
 
+       for (i = 0; cpu_types[i].name; ++i)
          {
-           static int in_delay_slot_p = 0;
-           static int prev_insn_needs_cc_nop_p = 0;
-           /* delay slot type seen */
-           int delay_slot_type = ARC_DELAY_NONE;
-           /* conditional execution flag seen */
-           int conditional = 0;
-           /* 1 if condition codes are being set */
-           int cc_set_p = 0;
-           /* 1 if conditional branch, including `b' "branch always" */
-           int cond_branch_p = opcode->flags & ARC_OPCODE_COND_BRANCH;
-
-           for (i = 0; i < num_suffixes; ++i)
+           if (!strcmp (cpu_types[i].name, s))
              {
-               switch (arc_operands[insn_suffixes[i]->type].fmt)
-                 {
-                 case 'n':
-                   delay_slot_type = insn_suffixes[i]->value;
-                   break;
-                 case 'q':
-                   conditional = insn_suffixes[i]->value;
-                   break;
-                 case 'f':
-                   cc_set_p = 1;
-                   break;
-                 }
+               arc_target      = cpu_types[i].flags;
+               arc_target_name = cpu_types[i].name;
+               arc_features    = cpu_types[i].features;
+               arc_mach_type   = cpu_types[i].mach;
+               cpu_flags       = cpu_types[i].eflags;
+
+               mach_type_specified_p = 1;
+               break;
              }
+         }
 
-           /* Putting an insn with a limm value in a delay slot is supposed to
-              be legal, but let's warn the user anyway.  Ditto for 8 byte
-              jumps with delay slots.  */
-           if (in_delay_slot_p && limm_p)
-             as_warn (_("8 byte instruction in delay slot"));
-           if (delay_slot_type != ARC_DELAY_NONE
-               && limm_p && arc_insn_not_jl (insn)) /* except for jl  addr */
-             as_warn (_("8 byte jump instruction with delay slot"));
-           in_delay_slot_p = (delay_slot_type != ARC_DELAY_NONE) && !limm_p;
-
-           /* Warn when a conditional branch immediately follows a set of
-              the condition codes.  Note that this needn't be done if the
-              insn that sets the condition codes uses a limm.  */
-           if (cond_branch_p && conditional != 0 /* 0 = "always" */
-               && prev_insn_needs_cc_nop_p && arc_mach_type == bfd_mach_arc_5)
-             as_warn (_("conditional branch follows set of flags"));
-           prev_insn_needs_cc_nop_p =
-             /* FIXME: ??? not required:
-                (delay_slot_type != ARC_DELAY_NONE) &&  */
-             cc_set_p && !limm_p;
+       if (!cpu_types[i].name)
+         {
+           as_fatal (_("unknown architecture: %s\n"), arg);
          }
+       break;
+      }
 
-         /* Write out the instruction.
-            It is important to fetch enough space in one call to `frag_more'.
-            We use (f - frag_now->fr_literal) to compute where we are and we
-            don't want frag_now to change between calls.  */
-         if (limm_p)
-           {
-             f = frag_more (8);
-             md_number_to_chars (f, insn, 4);
-             md_number_to_chars (f + 4, limm, 4);
-             dwarf2_emit_insn (8);
-           }
-         else if (limm_reloc_p)
-           /* We need a limm reloc, but the tables think we don't.  */
-           abort ();
-         else
-           {
-             f = frag_more (4);
-             md_number_to_chars (f, insn, 4);
-             dwarf2_emit_insn (4);
-           }
+    case OPTION_EB:
+      arc_target_format = "elf32-bigarc";
+      byte_order = BIG_ENDIAN;
+      break;
 
-         /* Create any fixups.  */
-         for (i = 0; i < fc; ++i)
-           {
-             int op_type, reloc_type;
-             expressionS exptmp;
-             const struct arc_operand *operand;
-
-             /* Create a fixup for this operand.
-                At this point we do not use a bfd_reloc_code_real_type for
-                operands residing in the insn, but instead just use the
-                operand index.  This lets us easily handle fixups for any
-                operand type, although that is admittedly not a very exciting
-                feature.  We pick a BFD reloc type in md_apply_fix.
-
-                Limm values (4 byte immediate "constants") must be treated
-                normally because they're not part of the actual insn word
-                and thus the insertion routines don't handle them.  */
-
-             if (arc_operands[fixups[i].opindex].flags & ARC_OPERAND_LIMM)
-               {
-                 /* Modify the fixup addend as required by the cpu.  */
-                 fixups[i].exp.X_add_number += arc_limm_fixup_adjust (insn);
-                 op_type = fixups[i].opindex;
-                 /* FIXME: can we add this data to the operand table?  */
-                 if (op_type == arc_operand_map['L']
-                     || op_type == arc_operand_map['s']
-                     || op_type == arc_operand_map['o']
-                     || op_type == arc_operand_map['O'])
-                   reloc_type = BFD_RELOC_32;
-                 else if (op_type == arc_operand_map['J'])
-                   reloc_type = BFD_RELOC_ARC_B26;
-                 else
-                   abort ();
-                 reloc_type = get_arc_exp_reloc_type (1, reloc_type,
-                                                      &fixups[i].exp,
-                                                      &exptmp);
-               }
-             else
-               {
-                 op_type = get_arc_exp_reloc_type (0, fixups[i].opindex,
-                                                   &fixups[i].exp, &exptmp);
-                 reloc_type = op_type + (int) BFD_RELOC_UNUSED;
-               }
-             operand = &arc_operands[op_type];
-             fix_new_exp (frag_now,
-                          ((f - frag_now->fr_literal)
-                           + (operand->flags & ARC_OPERAND_LIMM ? 4 : 0)), 4,
-                          &exptmp,
-                          (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) != 0,
-                          (bfd_reloc_code_real_type) reloc_type);
-           }
-         return;
+    case OPTION_EL:
+      arc_target_format = "elf32-littlearc";
+      byte_order = LITTLE_ENDIAN;
+      break;
+
+    case OPTION_CD:
+      /* This option has an effect only on ARC EM.  */
+      if (arc_target & ARC_OPCODE_ARCv2EM)
+       arc_features |= ARC_CD;
+      break;
+
+    case OPTION_USER_MODE:
+    case OPTION_LD_EXT_MASK:
+    case OPTION_SWAP:
+    case OPTION_NORM:
+    case OPTION_BARREL_SHIFT:
+    case OPTION_MIN_MAX:
+    case OPTION_NO_MPY:
+    case OPTION_EA:
+    case OPTION_MUL64:
+    case OPTION_SIMD:
+    case OPTION_SPFP:
+    case OPTION_DPFP:
+    case OPTION_XMAC_D16:
+    case OPTION_XMAC_24:
+    case OPTION_DSP_PACKA:
+    case OPTION_CRC:
+    case OPTION_DVBF:
+    case OPTION_TELEPHONY:
+    case OPTION_XYMEMORY:
+    case OPTION_LOCK:
+    case OPTION_SWAPE:
+    case OPTION_RTSC:
+    case OPTION_FPUDA:
+      /* Dummy options.  */
+
+    default:
+      return 0;
+    }
+
+  if (cpu_flags != EF_ARC_CPU_GENERIC)
+    arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  fprintf (stream, _("ARC-specific assembler options:\n"));
+
+  fprintf (stream, "  -mcpu=<cpu name>\t  assemble for CPU <cpu name>\n");
+  fprintf (stream,
+          "  -mcode-density\t  enable code density option for ARC EM\n");
+
+  fprintf (stream, _("\
+  -EB                     assemble code for a big-endian cpu\n"));
+  fprintf (stream, _("\
+  -EL                     assemble code for a little-endian cpu\n"));
+}
+
+static void
+preprocess_operands (const struct arc_opcode *opcode,
+                    expressionS *tok,
+                    int ntok)
+{
+  int i;
+  size_t len;
+  const char *p;
+  unsigned j;
+  const struct arc_aux_reg *auxr;
+
+  for (i = 0; i < ntok; i++)
+    {
+      switch (tok[i].X_op)
+       {
+       case O_illegal:
+       case O_absent:
+         break; /* Throw and error.  */
+
+       case O_symbol:
+         if (opcode->class != AUXREG)
+           break;
+         /* Convert the symbol to a constant if possible.  */
+         p = S_GET_NAME (tok[i].X_add_symbol);
+         len = strlen (p);
+
+         auxr = &arc_aux_regs[0];
+         for (j = 0; j < arc_num_aux_regs; j++, auxr++)
+           if (len == auxr->length
+               && strcasecmp (auxr->name, p) == 0)
+             {
+               tok[i].X_op = O_constant;
+               tok[i].X_add_number = auxr->address;
+               break;
+             }
+         break;
+       default:
+         break;
        }
     }
+}
 
-  if (NULL == last_errmsg)
-    as_bad (_("bad instruction `%s'"), start);
-  else
-    as_bad ("%s", last_errmsg);
+/* Given an opcode name, pre-tockenized set of argumenst and the
+   opcode flags, take it all the way through emission.  */
+
+static void
+assemble_tokens (const char *opname,
+                expressionS *tok,
+                int ntok,
+                struct arc_flags *pflags,
+                int nflgs)
+{
+  bfd_boolean found_something = FALSE;
+  const struct arc_opcode *opcode;
+  int cpumatch = 1;
+
+  /* Search opcodes.  */
+  opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname);
+
+  /* Couldn't find opcode conventional way, try special cases.  */
+  if (!opcode)
+    opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok);
+
+  if (opcode)
+    {
+      pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
+               frag_now->fr_file, frag_now->fr_line, opcode->name,
+               opcode->opcode);
+
+      preprocess_operands (opcode, tok, ntok);
+
+      found_something = TRUE;
+      opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch);
+      if (opcode)
+       {
+         struct arc_insn insn;
+         assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
+         emit_insn (&insn);
+         return;
+       }
+    }
+
+  if (found_something)
+    {
+      if (cpumatch)
+       as_bad (_("inappropriate arguments for opcode '%s'"), opname);
+      else
+       as_bad (_("opcode '%s' not supported for target %s"), opname,
+               arc_target_name);
+    }
+  else
+    as_bad (_("unknown opcode '%s'"), opname);
+}
+
+/* Used to find special case opcode.  */
+
+static const struct arc_opcode *
+find_special_case (const char *opname,
+                  int *nflgs,
+                  struct arc_flags *pflags,
+                  expressionS *tok,
+                  int *ntok)
+{
+  const struct arc_opcode *opcode;
+
+  opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
+
+  if (opcode == NULL)
+    opcode = find_special_case_flag (opname, nflgs, pflags);
+
+  return opcode;
+}
+
+/* Swap operand tokens.  */
+
+static void
+swap_operand (expressionS *operand_array,
+             unsigned source,
+             unsigned destination)
+{
+  expressionS cpy_operand;
+  expressionS *src_operand;
+  expressionS *dst_operand;
+  size_t size;
+
+  if (source == destination)
+    return;
+
+  src_operand = &operand_array[source];
+  dst_operand = &operand_array[destination];
+  size = sizeof (expressionS);
+
+  /* Make copy of operand to swap with and swap.  */
+  memcpy (&cpy_operand, dst_operand, size);
+  memcpy (dst_operand, src_operand, size);
+  memcpy (src_operand, &cpy_operand, size);
+}
+
+/* Check if *op matches *tok type.
+   Returns FALSE if they don't match, TRUE if they match.  */
+
+static bfd_boolean
+pseudo_operand_match (const expressionS *tok,
+                     const struct arc_operand_operation *op)
+{
+  offsetT min, max, val;
+  bfd_boolean ret;
+  const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
+
+  ret = FALSE;
+  switch (tok->X_op)
+    {
+    case O_constant:
+      if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
+       ret = 1;
+      else if (!(operand_real->flags & ARC_OPERAND_IR))
+       {
+         val = tok->X_add_number;
+         if (operand_real->flags & ARC_OPERAND_SIGNED)
+           {
+             max = (1 << (operand_real->bits - 1)) - 1;
+             min = -(1 << (operand_real->bits - 1));
+           }
+         else
+           {
+             max = (1 << operand_real->bits) - 1;
+             min = 0;
+           }
+         if (min <= val && val <= max)
+           ret = TRUE;
+       }
+      break;
+
+    case O_symbol:
+      /* Handle all symbols as long immediates or signed 9.  */
+      if (operand_real->flags & ARC_OPERAND_LIMM ||
+         ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
+       ret = TRUE;
+      break;
+
+    case O_register:
+      if (operand_real->flags & ARC_OPERAND_IR)
+       ret = TRUE;
+      break;
+
+    case O_bracket:
+      if (operand_real->flags & ARC_OPERAND_BRAKET)
+       ret = TRUE;
+      break;
+
+    default:
+      /* Unknown.  */
+      break;
+    }
+  return ret;
+}
+
+/* Find pseudo instruction in array.  */
+
+static const struct arc_pseudo_insn *
+find_pseudo_insn (const char *opname,
+                 int ntok,
+                 const expressionS *tok)
+{
+  const struct arc_pseudo_insn *pseudo_insn = NULL;
+  const struct arc_operand_operation *op;
+  unsigned int i;
+  int j;
+
+  for (i = 0; i < arc_num_pseudo_insn; ++i)
+    {
+      pseudo_insn = &arc_pseudo_insns[i];
+      if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
+       {
+         op = pseudo_insn->operand;
+         for (j = 0; j < ntok; ++j)
+           if (!pseudo_operand_match (&tok[j], &op[j]))
+             break;
+
+         /* Found the right instruction.  */
+         if (j == ntok)
+           return pseudo_insn;
+       }
+    }
+  return NULL;
+}
+
+/* Assumes the expressionS *tok is of sufficient size.  */
+
+static const struct arc_opcode *
+find_special_case_pseudo (const char *opname,
+                         int *ntok,
+                         expressionS *tok,
+                         int *nflgs,
+                         struct arc_flags *pflags)
+{
+  const struct arc_pseudo_insn *pseudo_insn = NULL;
+  const struct arc_operand_operation *operand_pseudo;
+  const struct arc_operand *operand_real;
+  unsigned i;
+  char construct_operand[MAX_CONSTR_STR];
+
+  /* Find whether opname is in pseudo instruction array.  */
+  pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
+
+  if (pseudo_insn == NULL)
+    return NULL;
+
+  /* Handle flag, Limited to one flag at the moment.  */
+  if (pseudo_insn->flag_r != NULL)
+    *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
+                             MAX_INSN_FLGS - *nflgs);
+
+  /* Handle operand operations.  */
+  for (i = 0; i < pseudo_insn->operand_cnt; ++i)
+    {
+      operand_pseudo = &pseudo_insn->operand[i];
+      operand_real = &arc_operands[operand_pseudo->operand_idx];
+
+      if (operand_real->flags & ARC_OPERAND_BRAKET &&
+         !operand_pseudo->needs_insert)
+       continue;
+
+      /* Has to be inserted (i.e. this token does not exist yet).  */
+      if (operand_pseudo->needs_insert)
+       {
+         if (operand_real->flags & ARC_OPERAND_BRAKET)
+           {
+             tok[i].X_op = O_bracket;
+             ++(*ntok);
+             continue;
+           }
+
+         /* Check if operand is a register or constant and handle it
+            by type.  */
+         if (operand_real->flags & ARC_OPERAND_IR)
+           snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
+                     operand_pseudo->count);
+         else
+           snprintf (construct_operand, MAX_CONSTR_STR, "%d",
+                     operand_pseudo->count);
+
+         tokenize_arguments (construct_operand, &tok[i], 1);
+         ++(*ntok);
+       }
+
+      else if (operand_pseudo->count)
+       {
+         /* Operand number has to be adjusted accordingly (by operand
+            type).  */
+         switch (tok[i].X_op)
+           {
+           case O_constant:
+             tok[i].X_add_number += operand_pseudo->count;
+             break;
+
+           case O_symbol:
+             break;
+
+           default:
+             /* Ignored.  */
+             break;
+           }
+       }
+    }
+
+  /* Swap operands if necessary.  Only supports one swap at the
+     moment.  */
+  for (i = 0; i < pseudo_insn->operand_cnt; ++i)
+    {
+      operand_pseudo = &pseudo_insn->operand[i];
+
+      if (operand_pseudo->swap_operand_idx == i)
+       continue;
+
+      swap_operand (tok, i, operand_pseudo->swap_operand_idx);
+
+      /* Prevent a swap back later by breaking out.  */
+      break;
+    }
+
+  return (const struct arc_opcode *)
+    hash_find (arc_opcode_hash,        pseudo_insn->mnemonic_r);
+}
+
+static const struct arc_opcode *
+find_special_case_flag (const char *opname,
+                       int *nflgs,
+                       struct arc_flags *pflags)
+{
+  unsigned int i;
+  const char *flagnm;
+  unsigned flag_idx, flag_arr_idx;
+  size_t flaglen, oplen;
+  const struct arc_flag_special *arc_flag_special_opcode;
+  const struct arc_opcode *opcode;
+
+  /* Search for special case instruction.  */
+  for (i = 0; i < arc_num_flag_special; i++)
+    {
+      arc_flag_special_opcode = &arc_flag_special_cases[i];
+      oplen = strlen (arc_flag_special_opcode->name);
+
+      if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
+       continue;
+
+      /* Found a potential special case instruction, now test for
+        flags.  */
+      for (flag_arr_idx = 0;; ++flag_arr_idx)
+       {
+         flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
+         if (flag_idx == 0)
+           break;  /* End of array, nothing found.  */
+
+         flagnm = arc_flag_operands[flag_idx].name;
+         flaglen = strlen (flagnm);
+         if (strcmp (opname + oplen, flagnm) == 0)
+           {
+             opcode = (const struct arc_opcode *)
+               hash_find (arc_opcode_hash,
+                          arc_flag_special_opcode->name);
+
+             if (*nflgs + 1 > MAX_INSN_FLGS)
+               break;
+             memcpy (pflags[*nflgs].name, flagnm, flaglen);
+             pflags[*nflgs].name[flaglen] = '\0';
+             (*nflgs)++;
+             return opcode;
+           }
+       }
+    }
+  return NULL;
+}
+
+/* Check whether a symbol involves a register.  */
+
+static int
+contains_register (symbolS *sym)
+{
+  if (sym)
+  {
+    expressionS *ex = symbol_get_value_expression (sym);
+    return ((O_register == ex->X_op)
+           && !contains_register (ex->X_add_symbol)
+           && !contains_register (ex->X_op_symbol));
+  }
+  else
+    return 0;
+}
+
+/* Returns the register number within a symbol.  */
+
+static int
+get_register (symbolS *sym)
+{
+  if (!contains_register (sym))
+    return -1;
+
+  expressionS *ex = symbol_get_value_expression (sym);
+  return regno (ex->X_add_number);
+}
+
+/* Allocates a tok entry.  */
+
+static int
+allocate_tok (expressionS *tok, int ntok, int cidx)
+{
+  if (ntok > MAX_INSN_ARGS - 2)
+    return 0; /* No space left.  */
+
+  if (cidx > ntok)
+    return 0; /* Incorect args.  */
+
+  memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
+
+  if (cidx == ntok)
+    return 1; /* Success.  */
+  return allocate_tok (tok, ntok - 1, cidx);
+}
+
+/* Return true if a RELOC is generic.  A generic reloc is PC-rel of a
+   simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32.  */
+
+static bfd_boolean
+generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
+{
+  if (!reloc)
+    return FALSE;
+
+  switch (reloc)
+    {
+    case BFD_RELOC_ARC_SDA_LDST:
+    case BFD_RELOC_ARC_SDA_LDST1:
+    case BFD_RELOC_ARC_SDA_LDST2:
+    case BFD_RELOC_ARC_SDA16_LD:
+    case BFD_RELOC_ARC_SDA16_LD1:
+    case BFD_RELOC_ARC_SDA16_LD2:
+    case BFD_RELOC_ARC_SDA16_ST2:
+    case BFD_RELOC_ARC_SDA32_ME:
+      return FALSE;
+    default:
+      break;
+    }
+  return TRUE;
+}
+
+/* Search forward through all variants of an opcode looking for a
+   syntax match.  */
+
+static const struct arc_opcode *
+find_opcode_match (const struct arc_opcode *first_opcode,
+                  expressionS *tok,
+                  int *pntok,
+                  struct arc_flags *first_pflag,
+                  int nflgs,
+                  int *pcpumatch)
+{
+  const struct arc_opcode *opcode = first_opcode;
+  int ntok = *pntok;
+  int got_cpu_match = 0;
+  expressionS bktok[MAX_INSN_ARGS];
+  int bkntok;
+  expressionS emptyE;
+
+  memset (&emptyE, 0, sizeof (emptyE));
+  memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
+  bkntok = ntok;
+
+  do
+    {
+      const unsigned char *opidx;
+      const unsigned char *flgidx;
+      int tokidx = 0;
+      const expressionS *t = &emptyE;
+
+      pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
+               frag_now->fr_file, frag_now->fr_line, opcode->opcode);
+
+      /* Don't match opcodes that don't exist on this
+        architecture.  */
+      if (!(opcode->cpu & arc_target))
+       goto match_failed;
+
+      if (is_code_density_p (opcode) && !(arc_features & ARC_CD))
+       goto match_failed;
+
+      got_cpu_match = 1;
+      pr_debug ("cpu ");
+
+      /* Check the operands.  */
+      for (opidx = opcode->operands; *opidx; ++opidx)
+       {
+         const struct arc_operand *operand = &arc_operands[*opidx];
+
+         /* Only take input from real operands.  */
+         if ((operand->flags & ARC_OPERAND_FAKE)
+             && !(operand->flags & ARC_OPERAND_BRAKET))
+           continue;
+
+         /* When we expect input, make sure we have it.  */
+         if (tokidx >= ntok)
+           goto match_failed;
+
+         /* Match operand type with expression type.  */
+         switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
+           {
+           case ARC_OPERAND_IR:
+             /* Check to be a register.  */
+             if ((tok[tokidx].X_op != O_register
+                  || !is_ir_num (tok[tokidx].X_add_number))
+                 && !(operand->flags & ARC_OPERAND_IGNORE))
+               goto match_failed;
+
+             /* If expect duplicate, make sure it is duplicate.  */
+             if (operand->flags & ARC_OPERAND_DUPLICATE)
+               {
+                 /* Check for duplicate.  */
+                 if (t->X_op != O_register
+                     || !is_ir_num (t->X_add_number)
+                     || (regno (t->X_add_number) !=
+                         regno (tok[tokidx].X_add_number)))
+                   goto match_failed;
+               }
+
+             /* Special handling?  */
+             if (operand->insert)
+               {
+                 const char *errmsg = NULL;
+                 (*operand->insert)(0,
+                                    regno (tok[tokidx].X_add_number),
+                                    &errmsg);
+                 if (errmsg)
+                   {
+                     if (operand->flags & ARC_OPERAND_IGNORE)
+                       {
+                         /* Missing argument, create one.  */
+                         if (!allocate_tok (tok, ntok - 1, tokidx))
+                           goto match_failed;
+
+                         tok[tokidx].X_op = O_absent;
+                         ++ntok;
+                       }
+                     else
+                       goto match_failed;
+                   }
+               }
+
+             t = &tok[tokidx];
+             break;
+
+           case ARC_OPERAND_BRAKET:
+             /* Check if bracket is also in opcode table as
+                operand.  */
+             if (tok[tokidx].X_op != O_bracket)
+               goto match_failed;
+             break;
+
+           case ARC_OPERAND_LIMM:
+           case ARC_OPERAND_SIGNED:
+           case ARC_OPERAND_UNSIGNED:
+             switch (tok[tokidx].X_op)
+               {
+               case O_illegal:
+               case O_absent:
+               case O_register:
+                 goto match_failed;
+
+               case O_bracket:
+                 /* Got an (too) early bracket, check if it is an
+                    ignored operand.  N.B. This procedure works only
+                    when bracket is the last operand!  */
+                 if (!(operand->flags & ARC_OPERAND_IGNORE))
+                   goto match_failed;
+                 /* Insert the missing operand.  */
+                 if (!allocate_tok (tok, ntok - 1, tokidx))
+                   goto match_failed;
+
+                 tok[tokidx].X_op = O_absent;
+                 ++ntok;
+                 break;
+
+               case O_constant:
+                 /* Check the range.  */
+                 if (operand->bits != 32
+                     && !(operand->flags & ARC_OPERAND_NCHK))
+                   {
+                     offsetT min, max, val;
+                     val = tok[tokidx].X_add_number;
+
+                     if (operand->flags & ARC_OPERAND_SIGNED)
+                       {
+                         max = (1 << (operand->bits - 1)) - 1;
+                         min = -(1 << (operand->bits - 1));
+                       }
+                     else
+                       {
+                         max = (1 << operand->bits) - 1;
+                         min = 0;
+                       }
+
+                     if (val < min || val > max)
+                       goto match_failed;
+
+                     /* Check alignmets.  */
+                     if ((operand->flags & ARC_OPERAND_ALIGNED32)
+                         && (val & 0x03))
+                       goto match_failed;
+
+                     if ((operand->flags & ARC_OPERAND_ALIGNED16)
+                         && (val & 0x01))
+                       goto match_failed;
+                   }
+                 else if (operand->flags & ARC_OPERAND_NCHK)
+                   {
+                     if (operand->insert)
+                       {
+                         const char *errmsg = NULL;
+                         (*operand->insert)(0,
+                                            tok[tokidx].X_add_number,
+                                            &errmsg);
+                         if (errmsg)
+                           goto match_failed;
+                       }
+                     else
+                       goto match_failed;
+                   }
+                 break;
+
+               case O_subtract:
+                 /* Check if it is register range.  */
+                 if ((tok[tokidx].X_add_number == 0)
+                     && contains_register (tok[tokidx].X_add_symbol)
+                     && contains_register (tok[tokidx].X_op_symbol))
+                   {
+                     int regs;
+
+                     regs = get_register (tok[tokidx].X_add_symbol);
+                     regs <<= 16;
+                     regs |= get_register (tok[tokidx].X_op_symbol);
+                     if (operand->insert)
+                       {
+                         const char *errmsg = NULL;
+                         (*operand->insert)(0,
+                                            regs,
+                                            &errmsg);
+                         if (errmsg)
+                           goto match_failed;
+                       }
+                     else
+                       goto match_failed;
+                     break;
+                   }
+               default:
+                 if (operand->default_reloc == 0)
+                   goto match_failed; /* The operand needs relocation.  */
+
+                 /* Relocs requiring long immediate.  FIXME! make it
+                    generic and move it to a function.  */
+                 switch (tok[tokidx].X_md)
+                   {
+                   case O_gotoff:
+                   case O_gotpc:
+                   case O_pcl:
+                   case O_tpoff:
+                   case O_dtpoff:
+                   case O_tlsgd:
+                   case O_tlsie:
+                     if (!(operand->flags & ARC_OPERAND_LIMM))
+                       goto match_failed;
+                   case O_absent:
+                     if (!generic_reloc_p (operand->default_reloc))
+                       goto match_failed;
+                   default:
+                     break;
+                   }
+                 break;
+               }
+             /* If expect duplicate, make sure it is duplicate.  */
+             if (operand->flags & ARC_OPERAND_DUPLICATE)
+               {
+                 if (t->X_op == O_illegal
+                     || t->X_op == O_absent
+                     || t->X_op == O_register
+                     || (t->X_add_number != tok[tokidx].X_add_number))
+                   goto match_failed;
+               }
+             t = &tok[tokidx];
+             break;
+
+           default:
+             /* Everything else should have been fake.  */
+             abort ();
+           }
+
+         ++tokidx;
+       }
+      pr_debug ("opr ");
+
+      /* Check the flags.  Iterate over the valid flag classes.  */
+      int lnflg = nflgs;
+
+      for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx)
+       {
+         /* Get a valid flag class.  */
+         const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+         const unsigned *flgopridx;
+
+         for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+           {
+             const struct arc_flag_operand *flg_operand;
+             struct arc_flags *pflag = first_pflag;
+             int i;
+
+             flg_operand = &arc_flag_operands[*flgopridx];
+             for (i = 0; i < nflgs; i++, pflag++)
+               {
+                 /* Match against the parsed flags.  */
+                 if (!strcmp (flg_operand->name, pflag->name))
+                   {
+                     /*TODO: Check if it is duplicated.  */
+                     pflag->code = *flgopridx;
+                     lnflg--;
+                     break; /* goto next flag class and parsed flag.  */
+                   }
+               }
+           }
+       }
+      /* Did I check all the parsed flags?  */
+      if (lnflg)
+       goto match_failed;
+
+      pr_debug ("flg");
+      /* Possible match -- did we use all of our input?  */
+      if (tokidx == ntok)
+       {
+         *pntok = ntok;
+         pr_debug ("\n");
+         return opcode;
+       }
+
+    match_failed:;
+      pr_debug ("\n");
+      /* Restore the original parameters.  */
+      memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
+      ntok = bkntok;
+    }
+  while (++opcode - arc_opcodes < (int) arc_num_opcodes
+        && !strcmp (opcode->name, first_opcode->name));
+
+  if (*pcpumatch)
+    *pcpumatch = got_cpu_match;
+
+  return NULL;
+}
+
+/* Find the proper relocation for the given opcode.  */
+
+static extended_bfd_reloc_code_real_type
+find_reloc (const char *name,
+           const char *opcodename,
+           const struct arc_flags *pflags,
+           int nflg,
+           extended_bfd_reloc_code_real_type reloc)
+{
+  unsigned int i;
+  int j;
+  bfd_boolean found_flag;
+  extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
+
+  for (i = 0; i < arc_num_equiv_tab; i++)
+    {
+      const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
+
+      /* Find the entry.  */
+      if (strcmp (name, r->name))
+       continue;
+      if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
+       continue;
+      if (r->flagcode)
+       {
+         if (!nflg)
+           continue;
+         found_flag = FALSE;
+         for (j = 0; j < nflg; j++)
+           if (pflags[i].code == r->flagcode)
+             {
+               found_flag = TRUE;
+               break;
+             }
+         if (!found_flag)
+           continue;
+       }
+
+      if (reloc != r->oldreloc)
+       continue;
+      /* Found it.  */
+      ret = r->newreloc;
+      break;
+    }
+
+  if (ret == BFD_RELOC_UNUSED)
+    as_bad (_("Unable to find %s relocation for instruction %s"),
+           name, opcodename);
+  return ret;
+}
+
+/* Turn an opcode description and a set of arguments into
+   an instruction and a fixup.  */
+
+static void
+assemble_insn (const struct arc_opcode *opcode,
+              const expressionS *tok,
+              int ntok,
+              const struct arc_flags *pflags,
+              int nflg,
+              struct arc_insn *insn)
+{
+  const expressionS *reloc_exp = NULL;
+  unsigned image;
+  const unsigned char *argidx;
+  int i;
+  int tokidx = 0;
+  unsigned char pcrel = 0;
+  bfd_boolean needGOTSymbol;
+  bfd_boolean has_delay_slot = FALSE;
+  extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
+
+  memset (insn, 0, sizeof (*insn));
+  image = opcode->opcode;
+
+  pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
+           frag_now->fr_file, frag_now->fr_line, opcode->name,
+           opcode->opcode);
+
+  /* Handle operands.  */
+  for (argidx = opcode->operands; *argidx; ++argidx)
+    {
+      const struct arc_operand *operand = &arc_operands[*argidx];
+      const expressionS *t = (const expressionS *) 0;
+
+      if ((operand->flags & ARC_OPERAND_FAKE)
+         && !(operand->flags & ARC_OPERAND_BRAKET))
+       continue;
+
+      if (operand->flags & ARC_OPERAND_DUPLICATE)
+       {
+         /* Duplicate operand, already inserted.  */
+         tokidx ++;
+         continue;
+       }
+
+      if (tokidx >= ntok)
+       {
+         abort ();
+       }
+      else
+       t = &tok[tokidx++];
+
+      /* Regardless if we have a reloc or not mark the instruction
+        limm if it is the case.  */
+      if (operand->flags & ARC_OPERAND_LIMM)
+       insn->has_limm = TRUE;
+
+      switch (t->X_op)
+       {
+       case O_register:
+         image = insert_operand (image, operand, regno (t->X_add_number),
+                                 NULL, 0);
+         break;
+
+       case O_constant:
+         image = insert_operand (image, operand, t->X_add_number, NULL, 0);
+         reloc_exp = t;
+         if (operand->flags & ARC_OPERAND_LIMM)
+           insn->limm = t->X_add_number;
+         break;
+
+       case O_bracket:
+         /* Ignore brackets.  */
+         break;
+
+       case O_absent:
+         gas_assert (operand->flags & ARC_OPERAND_IGNORE);
+         break;
+
+       case O_subtract:
+         /* Maybe register range.  */
+         if ((t->X_add_number == 0)
+             && contains_register (t->X_add_symbol)
+             && contains_register (t->X_op_symbol))
+           {
+             int regs;
+
+             regs = get_register (t->X_add_symbol);
+             regs <<= 16;
+             regs |= get_register (t->X_op_symbol);
+             image = insert_operand (image, operand, regs, NULL, 0);
+             break;
+           }
+
+       default:
+         /* This operand needs a relocation.  */
+         needGOTSymbol = FALSE;
+
+         switch (t->X_md)
+           {
+           case O_plt:
+             needGOTSymbol = TRUE;
+             reloc = find_reloc ("plt", opcode->name,
+                                 pflags, nflg,
+                                 operand->default_reloc);
+             break;
+
+           case O_gotoff:
+           case O_gotpc:
+             needGOTSymbol = TRUE;
+             reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
+             break;
+           case O_pcl:
+             reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
+             if (ARC_SHORT (opcode->mask))
+               as_bad_where (frag_now->fr_file, frag_now->fr_line,
+                             _("Unable to use @pcl relocation for insn %s"),
+                             opcode->name);
+             break;
+           case O_sda:
+             reloc = find_reloc ("sda", opcode->name,
+                                 pflags, nflg,
+                                 operand->default_reloc);
+             break;
+           case O_tlsgd:
+           case O_tlsie:
+             needGOTSymbol = TRUE;
+             /* Fall-through.  */
+
+           case O_tpoff:
+           case O_dtpoff:
+             reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
+             break;
+
+           case O_tpoff9: /*FIXME! Check for the conditionality of
+                            the insn.  */
+           case O_dtpoff9: /*FIXME! Check for the conditionality of
+                             the insn.  */
+             as_bad (_("TLS_*_S9 relocs are not supported yet"));
+             break;
+
+           default:
+             /* Just consider the default relocation.  */
+             reloc = operand->default_reloc;
+             break;
+           }
+
+         if (needGOTSymbol && (GOT_symbol == NULL))
+           GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
+
+         reloc_exp = t;
+
+#if 0
+         if (reloc > 0)
+           {
+             /* sanity checks.  */
+             reloc_howto_type *reloc_howto
+               = bfd_reloc_type_lookup (stdoutput,
+                                        (bfd_reloc_code_real_type) reloc);
+             unsigned reloc_bitsize = reloc_howto->bitsize;
+             if (reloc_howto->rightshift)
+               reloc_bitsize -= reloc_howto->rightshift;
+             if (reloc_bitsize != operand->bits)
+               {
+                 as_bad (_("invalid relocation %s for field"),
+                         bfd_get_reloc_code_name (reloc));
+                 return;
+               }
+           }
+#endif
+         if (insn->nfixups >= MAX_INSN_FIXUPS)
+           as_fatal (_("too many fixups"));
+
+         struct arc_fixup *fixup;
+         fixup = &insn->fixups[insn->nfixups++];
+         fixup->exp = *t;
+         fixup->reloc = reloc;
+         pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
+         fixup->pcrel = pcrel;
+         fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
+           TRUE : FALSE;
+         break;
+       }
+    }
+
+  /* Handle flags.  */
+  for (i = 0; i < nflg; i++)
+    {
+      const struct arc_flag_operand *flg_operand =
+       &arc_flag_operands[pflags[i].code];
+
+      /* Check if the instruction has a delay slot.  */
+      if (!strcmp (flg_operand->name, "d"))
+       has_delay_slot = TRUE;
+
+      /* There is an exceptional case when we cannot insert a flag
+        just as it is.  The .T flag must be handled in relation with
+        the relative address.  */
+      if (!strcmp (flg_operand->name, "t")
+         || !strcmp (flg_operand->name, "nt"))
+       {
+         unsigned bitYoperand = 0;
+         /* FIXME! move selection bbit/brcc in arc-opc.c.  */
+         if (!strcmp (flg_operand->name, "t"))
+           if (!strcmp (opcode->name, "bbit0")
+               || !strcmp (opcode->name, "bbit1"))
+             bitYoperand = arc_NToperand;
+           else
+             bitYoperand = arc_Toperand;
+         else
+           if (!strcmp (opcode->name, "bbit0")
+               || !strcmp (opcode->name, "bbit1"))
+             bitYoperand = arc_Toperand;
+           else
+             bitYoperand = arc_NToperand;
+
+         gas_assert (reloc_exp != NULL);
+         if (reloc_exp->X_op == O_constant)
+           {
+             /* Check if we have a constant and solved it
+                immediately.  */
+             offsetT val = reloc_exp->X_add_number;
+             image |= insert_operand (image, &arc_operands[bitYoperand],
+                                      val, NULL, 0);
+           }
+         else
+           {
+             struct arc_fixup *fixup;
+
+             if (insn->nfixups >= MAX_INSN_FIXUPS)
+               as_fatal (_("too many fixups"));
+
+             fixup = &insn->fixups[insn->nfixups++];
+             fixup->exp = *reloc_exp;
+             fixup->reloc = -bitYoperand;
+             fixup->pcrel = pcrel;
+             fixup->islong = FALSE;
+           }
+       }
+      else
+       image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
+         << flg_operand->shift;
+    }
+
+  /* Short instruction?  */
+  insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
+
+  insn->insn = image;
+
+  /* Update last insn status.  */
+  arc_last_insns[1]               = arc_last_insns[0];
+  arc_last_insns[0].opcode        = opcode;
+  arc_last_insns[0].has_limm      = insn->has_limm;
+  arc_last_insns[0].has_delay_slot = has_delay_slot;
+
+  /* Check if the current instruction is legally used.  */
+  if (arc_last_insns[1].has_delay_slot
+      && is_br_jmp_insn_p (arc_last_insns[0].opcode))
+    as_bad_where (frag_now->fr_file, frag_now->fr_line,
+                 _("A jump/branch instruction in delay slot."));
+}
+
+/* Actually output an instruction with its fixup.  */
+
+static void
+emit_insn (struct arc_insn *insn)
+{
+  char *f;
+  int i;
+
+  pr_debug ("Emit insn : 0x%x\n", insn->insn);
+  pr_debug ("\tShort   : 0x%d\n", insn->short_insn);
+  pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
+
+  /* Write out the instruction.  */
+  if (insn->short_insn)
+    {
+      if (insn->has_limm)
+       {
+         f = frag_more (6);
+         md_number_to_chars (f, insn->insn, 2);
+         md_number_to_chars_midend (f + 2, insn->limm, 4);
+         dwarf2_emit_insn (6);
+       }
+      else
+       {
+         f = frag_more (2);
+         md_number_to_chars (f, insn->insn, 2);
+         dwarf2_emit_insn (2);
+       }
+    }
+  else
+    {
+      if (insn->has_limm)
+       {
+         f = frag_more (8);
+         md_number_to_chars_midend (f, insn->insn, 4);
+         md_number_to_chars_midend (f + 4, insn->limm, 4);
+         dwarf2_emit_insn (8);
+       }
+      else
+       {
+         f = frag_more (4);
+         md_number_to_chars_midend (f, insn->insn, 4);
+         dwarf2_emit_insn (4);
+       }
+    }
+
+  /* Apply the fixups in order.  */
+  for (i = 0; i < insn->nfixups; i++)
+    {
+      struct arc_fixup *fixup = &insn->fixups[i];
+      int size, pcrel, offset = 0;
+
+      /*FIXME! the reloc size is wrong in the BFD file.  When it will
+       be fixed please delete me.  */
+      size = (insn->short_insn && !fixup->islong) ? 2 : 4;
+
+      if (fixup->islong)
+       offset = (insn->short_insn) ? 2 : 4;
+
+      /* Some fixups are only used internally, thus no howto.  */
+      if ((int) fixup->reloc < 0)
+       {
+         /*FIXME! the reloc size is wrong in the BFD file.  When it
+           will be fixed please enable me.
+           size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
+         pcrel = fixup->pcrel;
+       }
+      else
+       {
+         reloc_howto_type *reloc_howto =
+           bfd_reloc_type_lookup (stdoutput,
+                                  (bfd_reloc_code_real_type) fixup->reloc);
+         gas_assert (reloc_howto);
+         /*FIXME! the reloc size is wrong in the BFD file.  When it
+           will be fixed please enable me.
+           size = bfd_get_reloc_size (reloc_howto); */
+         pcrel = reloc_howto->pc_relative;
+       }
+
+      pr_debug ("%s:%d: emit_insn: new %s fixup (PCrel:%s) of size %d @ offset %d\n",
+               frag_now->fr_file, frag_now->fr_line,
+               (fixup->reloc < 0) ? "Internal" :
+               bfd_get_reloc_code_name (fixup->reloc),
+               pcrel ? "Y" : "N",
+               size, offset);
+      fix_new_exp (frag_now, f - frag_now->fr_literal + offset,
+                  size, &fixup->exp, pcrel, fixup->reloc);
+
+      /* Check for ZOLs, and update symbol info if any.  */
+      if (LP_INSN (insn->insn))
+       {
+         gas_assert (fixup->exp.X_add_symbol);
+         ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
+       }
+    }
+}
+
+/* Insert an operand value into an instruction.  */
+
+static unsigned
+insert_operand (unsigned insn,
+               const struct arc_operand *operand,
+               offsetT val,
+               char *file,
+               unsigned line)
+{
+  offsetT min = 0, max = 0;
+
+  if (operand->bits != 32
+      && !(operand->flags & ARC_OPERAND_NCHK)
+      && !(operand->flags & ARC_OPERAND_FAKE))
+    {
+      if (operand->flags & ARC_OPERAND_SIGNED)
+       {
+         max = (1 << (operand->bits - 1)) - 1;
+         min = -(1 << (operand->bits - 1));
+       }
+      else
+       {
+         max = (1 << operand->bits) - 1;
+         min = 0;
+       }
+
+      if (val < min || val > max)
+       as_bad_value_out_of_range (_("operand"),
+                                  val, min, max, file, line);
+    }
+
+  pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
+           min, val, max, insn);
+
+  if ((operand->flags & ARC_OPERAND_ALIGNED32)
+      && (val & 0x03))
+    as_bad_where (file, line,
+                 _("Unaligned operand. Needs to be 32bit aligned"));
+
+  if ((operand->flags & ARC_OPERAND_ALIGNED16)
+      && (val & 0x01))
+    as_bad_where (file, line,
+                 _("Unaligned operand. Needs to be 16bit aligned"));
+
+  if (operand->insert)
+    {
+      const char *errmsg = NULL;
+
+      insn = (*operand->insert) (insn, val, &errmsg);
+      if (errmsg)
+       as_warn_where (file, line, "%s", errmsg);
+    }
+  else
+    {
+      if (operand->flags & ARC_OPERAND_TRUNCATE)
+       {
+         if (operand->flags & ARC_OPERAND_ALIGNED32)
+           val >>= 2;
+         if (operand->flags & ARC_OPERAND_ALIGNED16)
+           val >>= 1;
+       }
+      insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
+    }
+  return insn;
+}
+
+void
+arc_handle_align (fragS* fragP)
+{
+  if ((fragP)->fr_type == rs_align_code)
+    {
+      char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
+      valueT count = ((fragP)->fr_next->fr_address
+                     - (fragP)->fr_address - (fragP)->fr_fix);
+
+      (fragP)->fr_var = 2;
+
+      if (count & 1)/* Padding in the gap till the next 2-byte
+                      boundary with 0s.  */
+       {
+         (fragP)->fr_fix++;
+         *dest++ = 0;
+       }
+      /* Writing nop_s.  */
+      md_number_to_chars (dest, NOP_OPCODE_S, 2);
+    }
+}
+
+/* Here we decide which fixups can be adjusted to make them relative
+   to the beginning of the section instead of the symbol.  Basically
+   we need to make sure that the dynamic relocations are done
+   correctly, so in some cases we force the original symbol to be
+   used.  */
+
+int
+tc_arc_fix_adjustable (fixS *fixP)
+{
+
+  /* Prevent all adjustments to global symbols.  */
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
+    return 0;
+  if (S_IS_WEAK (fixP->fx_addsy))
+    return 0;
+
+  /* Adjust_reloc_syms doesn't know about the GOT.  */
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_ARC_GOTPC32:
+    case BFD_RELOC_ARC_PLT32:
+    case BFD_RELOC_ARC_S25H_PCREL_PLT:
+    case BFD_RELOC_ARC_S21H_PCREL_PLT:
+    case BFD_RELOC_ARC_S25W_PCREL_PLT:
+    case BFD_RELOC_ARC_S21W_PCREL_PLT:
+      return 0;
+
+    default:
+      break;
+    }
+
+  return 0; /* FIXME! return 1, fix it in the linker.  */
+}
+
+/* Compute the reloc type of an expression EXP.  */
+
+static void
+arc_check_reloc (expressionS *exp,
+                bfd_reloc_code_real_type *r_type_p)
+{
+  if (*r_type_p == BFD_RELOC_32
+      && exp->X_op == O_subtract
+      && exp->X_op_symbol != NULL
+      && exp->X_op_symbol->bsym->section == now_seg)
+    *r_type_p = BFD_RELOC_ARC_PC32;
+}
+
+
+/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG.  */
+
+void
+arc_cons_fix_new (fragS *frag,
+                 int off,
+                 int size,
+                 expressionS *exp,
+                 bfd_reloc_code_real_type r_type)
+{
+  r_type = BFD_RELOC_UNUSED;
+
+  switch (size)
+    {
+    case 1:
+      r_type = BFD_RELOC_8;
+      break;
+
+    case 2:
+      r_type = BFD_RELOC_16;
+      break;
+
+    case 3:
+      r_type = BFD_RELOC_24;
+      break;
+
+    case 4:
+      r_type = BFD_RELOC_32;
+      arc_check_reloc (exp, &r_type);
+      break;
+
+    case 8:
+      r_type = BFD_RELOC_64;
+      break;
+
+    default:
+      as_bad (_("unsupported BFD relocation size %u"), size);
+      r_type = BFD_RELOC_UNUSED;
+    }
+
+  fix_new_exp (frag, off, size, exp, 0, r_type);
+}
+
+/* The actual routine that checks the ZOL conditions.  */
+
+static void
+check_zol (symbolS *s)
+{
+  switch (arc_mach_type)
+    {
+    case bfd_mach_arc_arcv2:
+      if (arc_target & ARC_OPCODE_ARCv2EM)
+       return;
+
+      if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
+         || arc_last_insns[1].has_delay_slot)
+       as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
+               S_GET_NAME (s));
+
+      break;
+    case bfd_mach_arc_arc600:
+
+      if (is_kernel_insn_p (arc_last_insns[0].opcode))
+       as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
+               S_GET_NAME (s));
+
+      if (arc_last_insns[0].has_limm
+         && is_br_jmp_insn_p (arc_last_insns[0].opcode))
+       as_bad (_("A jump instruction with long immediate detected at the \
+end of the ZOL label @%s"), S_GET_NAME (s));
+
+      /* Fall through.  */
+    case bfd_mach_arc_arc700:
+      if (arc_last_insns[0].has_delay_slot)
+       as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
+               S_GET_NAME (s));
+
+      break;
+    default:
+      break;
+    }
+}
+
+/* If ZOL end check the last two instruction for illegals.  */
+void
+arc_frob_label (symbolS * sym)
+{
+  if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
+    check_zol (sym);
+
+  dwarf2_emit_label (sym);
 }

diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h
index 8eda165..8fff767 100644 (file)
--- a/gas/config/tc-arc.h
+++ b/gas/config/tc-arc.h
@@ -1,6 +1,7 @@
 /* tc-arc.h - Macros and type defines for the ARC.
-   Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+   Copyright 2014 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,56 +20,170 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#define TC_ARC 1
 
-#define TARGET_BYTES_BIG_ENDIAN 0
+/* By convention, you should define this macro in the `.h' file.  For
+   example, `tc-m68k.h' defines `TC_M68K'.  You might have to use this
+   if it is necessary to add CPU specific code to the object format
+   file.  */
+#define TC_ARC
 
+/* We want local label support.  */
 #define LOCAL_LABELS_FB 1
 
+/* This macro is the BFD architecture to pass to
+   `bfd_set_arch_mach'.  */
 #define TARGET_ARCH bfd_arch_arc
 
+/* The `extsym - .' expressions can be emitted using PC-relative
+   relocs.  */
 #define DIFF_EXPR_OK
-#define REGISTER_PREFIX '%'
-
-#ifdef LITTLE_ENDIAN
-#undef LITTLE_ENDIAN
-#endif
 
-#ifdef BIG_ENDIAN
-#undef BIG_ENDIAN
-#endif
+#define REGISTER_PREFIX '%'
 
+#undef  LITTLE_ENDIAN
 #define LITTLE_ENDIAN   1234
 
+#undef  BIG_ENDIAN
 #define BIG_ENDIAN      4321
 
+#ifdef TARGET_BYTES_BIG_ENDIAN
+
+# define DEFAULT_TARGET_FORMAT  "elf32-bigarc"
+# define DEFAULT_BYTE_ORDER     BIG_ENDIAN
+
+#else
+/* You should define this macro to be non-zero if the target is big
+   endian, and zero if the target is little endian.  */
+# define TARGET_BYTES_BIG_ENDIAN 0
+
+# define DEFAULT_TARGET_FORMAT  "elf32-littlearc"
+# define DEFAULT_BYTE_ORDER     LITTLE_ENDIAN
+
+#endif /* TARGET_BYTES_BIG_ENDIAN.  */
+
 /* The endianness of the target format may change based on command
    line arguments.  */
-extern const char * arc_target_format;
-
-#define DEFAULT_TARGET_FORMAT  "elf32-littlearc"
-#define TARGET_FORMAT          arc_target_format
-#define DEFAULT_BYTE_ORDER     LITTLE_ENDIAN
+extern const char *arc_target_format;
+
+/* This macro is the BFD target name to use when creating the output
+   file.  This will normally depend upon the `OBJ_FMT' macro.  */
+#define TARGET_FORMAT arc_target_format
+
+/* `md_short_jump_size'
+   `md_long_jump_size'
+   `md_create_short_jump'
+   `md_create_long_jump'
+
+   If `WORKING_DOT_WORD' is defined, GAS will not do broken word
+   processing (*note Broken words::.).  Otherwise, you should set
+   `md_short_jump_size' to the size of a short jump (a jump that is
+   just long enough to jump around a long jmp) and `md_long_jump_size'
+   to the size of a long jump (a jump that can go anywhere in the
+   function).  You should define `md_create_short_jump' to create a
+   short jump around a long jump, and define `md_create_long_jump' to
+   create a long jump.  */
 #define WORKING_DOT_WORD
-#define LISTING_HEADER         "ARC GAS "
 
-/* The ARC needs to parse reloc specifiers in .word.  */
+#define LISTING_HEADER "ARC GAS "
 
-extern bfd_reloc_code_real_type arc_parse_cons_expression (struct expressionS *,
-                                                          unsigned);
-#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \
-  arc_parse_cons_expression (EXP, NBYTES)
+/* The number of bytes to put into a word in a listing.  This affects
+   the way the bytes are clumped together in the listing.  For
+   example, a value of 2 might print `1234 5678' where a value of 1
+   would print `12 34 56 78'.  The default value is 4.  */
+#define LISTING_WORD_SIZE 2
 
-extern void arc_cons_fix_new (struct frag *, int, int, struct expressionS *,
-                             bfd_reloc_code_real_type);
-#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC)       \
-  arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC)
+/* If you define this macro, it should return the position from which
+   the PC relative adjustment for a PC relative fixup should be made.
+   On many processors, the base of a PC relative instruction is the
+   next instruction, so this macro would return the length of an
+   instruction, plus the address of the PC relative fixup.  The latter
+   can be calculated as fixp->fx_where +
+   fixp->fx_frag->fr_address.  */
+extern long md_pcrel_from_section (struct fix *, segT);
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
+
+/* [ ] is index operator.  */
+#define NEED_INDEX_OPERATOR
 
-#define DWARF2_LINE_MIN_INSN_LENGTH 4
+#define MAX_MEM_FOR_RS_ALIGN_CODE (1+2)
 
-/* Values passed to md_apply_fix don't include the symbol value.  */
+/* HANDLE_ALIGN called after all the assembly has been done,
+   so we can fill in all the rs_align_code type frags with
+   nop instructions.  */
+#define HANDLE_ALIGN(FRAGP)     arc_handle_align (FRAGP)
+
+/* Values passed to md_apply_fix3 don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* No shared lib support, so we don't need to ensure externally
    visible symbols can be overridden.  */
 #define EXTERN_FORCE_RELOC 0
+
+/* You may define this macro to generate a fixup for a data allocation
+   pseudo-op.  */
+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC)    \
+  arc_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC))
+
+/* We don't want gas to fixup the following program memory related
+   relocations.  */
+#define TC_VALIDATE_FIX(FIXP,SEG,SKIP)                      \
+  if ((FIXP->fx_r_type == BFD_RELOC_ARC_GOTPC32)            \
+      && FIXP->fx_addsy != NULL                                     \
+      && FIXP->fx_subsy == NULL)                            \
+    {                                                       \
+      symbol_mark_used_in_reloc (FIXP->fx_addsy);           \
+      goto SKIP;                                            \
+    }
+
+/* BFD_RELOC_ARC_TLS_GD_LD may use fx_subsy to store a label that is
+   later turned into fx_offset.  */
+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \
+  ((FIX)->fx_r_type == BFD_RELOC_ARC_TLS_GD_LD)
+
+#define TC_VALIDATE_FIX_SUB(FIX, SEG) \
+  ((md_register_arithmetic || (SEG) != reg_section) \
+   && ((FIX)->fx_r_type == BFD_RELOC_GPREL32 \
+       || (FIX)->fx_r_type == BFD_RELOC_GPREL16 \
+       || (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF \
+       || (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF_S9 \
+       || TC_FORCE_RELOCATION_SUB_LOCAL (FIX, SEG)))
+
+/* We use this to mark the end-loop label.  We use this mark for ZOL
+   validity checks.  */
+#define TC_SYMFIELD_TYPE   unsigned int
+#define ARC_GET_FLAG(s)   (*symbol_get_tc (s))
+#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
+
+/* The symbol is a ZOL's end loop label.  */
+#define ARC_FLAG_ZOL      (1 << 0)
+
+/* We use this hook to check the validity of the last to instructions
+   of a ZOL.  */
+#define tc_frob_label(S)  arc_frob_label (S)
+
+#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
+#define DYNAMIC_STRUCT_NAME "_DYNAMIC"
+
+/* We need to take care of not having section relative fixups for the
+   fixups with respect to Position Independent Code.  */
+#define tc_fix_adjustable(FIX)  tc_arc_fix_adjustable(FIX)
+
+/* This hook is required to parse register names as operands.  */
+#define md_parse_name(name, exp, m, c) arc_parse_name (name, exp)
+
+extern bfd_boolean arc_parse_name (const char *, struct expressionS *);
+extern int tc_arc_fix_adjustable (struct fix *);
+extern void arc_handle_align (fragS *);
+extern void arc_cons_fix_new (fragS *, int, int, expressionS *,
+                             bfd_reloc_code_real_type);
+extern void arc_frob_label (symbolS *);
+
+/* The blink register is r31.  */
+#define DWARF2_DEFAULT_RETURN_COLUMN   31
+/* Registers are generally saved at negative offsets to the CFA.  */
+#define DWARF2_CIE_DATA_ALIGNMENT      (-4)
+
+/* Define the NOPs.  */
+#define NOP_OPCODE_S   0x000078E0
+#define NOP_OPCODE_L   0x264A7000 /* mov 0,0.  */
+

diff --git a/gas/configure.tgt b/gas/configure.tgt
index 00fa104..0b490d4 100644 (file)
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -6,12 +6,12 @@
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
-#
+# 
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-#
+# 
 # You should have received a copy of the GNU General Public License
 # along with this program; see the file COPYING3.  If not see
 # <http://www.gnu.org/licenses/>.
@@ -50,6 +50,7 @@ case ${cpu} in
   aarch64_be)          cpu_type=aarch64 endian=big ;;
   alpha*)              cpu_type=alpha ;;
   am33_2.0)            cpu_type=mn10300 endian=little ;;
+  arc*eb)              cpu_type=arc endian=big ;;
   arm*be|arm*b)                cpu_type=arm endian=big ;;
   arm*)                        cpu_type=arm endian=little ;;
   bfin*)               cpu_type=bfin endian=little ;;
@@ -130,6 +131,7 @@ case ${generic_target} in
   alpha-*-openbsd*)                    fmt=elf em=obsd ;;
 
   arc-*-elf*)                          fmt=elf ;;
+  arc*-*-linux-uclibc*)                        fmt=elf bfd_gas=yes ;;
 
   arm-*-aout)                          fmt=aout ;;
   arm-*-coff)                          fmt=coff ;;
@@ -352,7 +354,7 @@ case ${generic_target} in
   moxie-*-uclinux)                     fmt=elf em=linux ;;
   moxie-*-moxiebox*)                    fmt=elf endian=little ;;
   moxie-*-*)                           fmt=elf ;;
-
+    
   mt-*-elf)                            fmt=elf bfd_gas=yes ;;
 
   msp430-*-*)                          fmt=elf ;;
@@ -461,7 +463,7 @@ case ${generic_target} in
   visium-*-elf)                                fmt=elf ;;
 
   xstormy16-*-*)                       fmt=elf ;;
-
+  
   xgate-*-*)                           fmt=elf ;;
 
   xtensa*-*-*)                         fmt=elf ;;

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index fa3221e..4ed29d1 100644 (file)
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -265,7 +265,9 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @ifset ARC
 
 @emph{Target ARC options:}
-   [@b{-marc[5|6|7|8]}]
+   [@b{-mcpu=@var{cpu}}]
+   [@b{-mA6}|@b{-mARC600}|@b{-mARC601}|@b{-mA7}|@b{-mARC700}|@b{-mEM}|@b{-mHS}]
+   [@b{-mcode-density}]
    [@b{-EB}|@b{-EL}]
 @end ifset
 @ifset ARM
@@ -860,14 +862,16 @@ processor.
 
 @c man begin OPTIONS
 @ifset ARC
-The following options are available when @value{AS} is configured for
-an ARC processor.
+The following options are available when @value{AS} is configured for an ARC
+processor.
 
 @table @gcctabopt
-@item -marc[5|6|7|8]
+@item -mcpu=@var{cpu}
 This option selects the core processor variant.
 @item -EB | -EL
 Select either big-endian (-EB) or little-endian (-EL) output.
+@item -mcode-density
+Enable Code Density extenssion instructions.
 @end table
 @end ifset
 

diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index 9fa28e5..f72ecae 100644 (file)
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -19,52 +19,54 @@
 @menu
 * ARC Options::              Options
 * ARC Syntax::               Syntax
-* ARC Floating Point::       Floating Point
 * ARC Directives::           ARC Machine Directives
+* ARC Modifiers::            ARC Assembler Modifiers
+* ARC Symbols::              ARC Pre-defined Symbols
 * ARC Opcodes::              Opcodes
 @end menu
 
-
 @node ARC Options
 @section Options
-@cindex ARC options (none)
-@cindex options for ARC (none)
+@cindex ARC options
+@cindex options for ARC
+
+The following options control the type of CPU for which code is
+assembled, and generic constraints on the code generated:
 
 @table @code
 
-@cindex @code{-marc[5|6|7|8]} command line option, ARC
-@item -marc[5|6|7|8]
-This option selects the core processor variant.  Using
-@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which
-is also the default.
+@item -mcpu=@var{cpu}
+@cindex @code{-mcpu=@var{cpu}} command line option, ARC
+Set architecture type and register usage for @var{cpu}.  There are
+also shortcut alias options available for backward compatibility and
+convenience.  Supported values for @var{cpu} are
 
 @table @code
+@cindex @code{mA6} command line option, ARC
+@cindex @code{marc600} command line option, ARC
+@item arc600
+Assemble for ARC 600.  Aliases: @code{-mA6}, @code{-mARC600}.
 
-@cindex @code{arc5} arc5, ARC
-@item arc5
-Base instruction set.
+@item arc601
+@cindex @code{mARC601} command line option, ARC
+Assemble for ARC 601.  Alias: @code{-mARC601}.
 
-@cindex @code{arc6} arc6, ARC
-@item arc6
-Jump-and-link (jl) instruction.  No requirement of an instruction between
-setting flags and conditional jump.  For example:
+@item arc700
+@cindex @code{mA7} command line option, ARC
+@cindex @code{mARC700} command line option, ARC
+Assemble for ARC 700.  Aliases: @code{-mA7}, @code{-mARC700}.
 
-@smallexample
-  mov.f r0,r1
-  beq   foo
-@end smallexample
+@item arcem
+@cindex @code{mEM} command line option, ARC
+Assemble for ARC EM.  Aliases: @code{-mEM}
 
-@cindex @code{arc7} arc7, ARC
-@item arc7
-Break (brk) and sleep (sleep) instructions.
-
-@cindex @code{arc8} arc8, ARC
-@item arc8
-Software interrupt (swi) instruction.
+@item archs
+@cindex @code{mHS} command line option, ARC
+Assemble for ARC HS.  Aliases: @code{-mHS}, @code{-mav2hs}.
 
 @end table
 
-Note: the @code{.option} directive can to be used to select a core
+Note: the @code{.cpu} directive can to be used to select a core
 variant from within assembly code.
 
 @cindex @code{-EB} command line option, ARC
@@ -78,6 +80,11 @@ This option specifies that the output generated by the assembler should
 be marked as being encoded for a little-endian processor - this is the
 default.
 
+@cindex @code{-mcode-density} command line option, ARC
+@item -mcode-density
+This option turns on Code Density instructions.  Only valid for ARC EM
+processors.
+
 @end table
 
 @node ARC Syntax
@@ -90,36 +97,211 @@ default.
 @node ARC-Chars
 @subsection Special Characters
 
+@table @code
+@item %
+@cindex register name prefix character, ARC
+@cindex ARC register name prefix character
+A register name can optionally be prefixed by a @samp{%} character.  So
+register @code{%r0} is equivalent to @code{r0} in the assembly code.
+
+@item #
 @cindex line comment character, ARC
 @cindex ARC line comment character
-The presence of a @samp{#} on a line indicates the start of a comment
-that extends to the end of the current line.  Note that if a line
-starts with a @samp{#} character then it can also be a logical line
-number directive (@pxref{Comments}) or a preprocessor
-control command (@pxref{Preprocessing}).
-
+The presence of a @samp{#} character within a line (but not at the
+start of a line) indicates the start of a comment that extends to the
+end of the current line.
+
+@emph{Note:} if a line starts with a @samp{#} character then it can
+also be a logical line number directive (@pxref{Comments}) or a
+preprocessor control command (@pxref{Preprocessing}).
+
+@item @@
+@cindex symbol prefix character, ARC
+@cindex ARC symbol prefix character
+Prefixing an operand with an @samp{@@} specifies that the operand is a
+symbol and not a register.  This is how the assembler disambiguates
+the use of an ARC register name as a symbol.  So the instruction
+@example
+mov r0, @@r0
+@end example
+moves the address of symbol @code{r0} into register @code{r0}.
+
+@item `
 @cindex line separator, ARC
 @cindex statement separator, ARC
 @cindex ARC line separator
-The ARC assembler does not support a line separator character.
+The @samp{`} (backtick) character is used to separate statements on a
+single line.
+
+@cindex line
+@item -
+@cindex C preprocessor macro separator, ARC
+@cindex ARC C preprocessor macro separator
+Used as a separator to obtain a sequence of commands from a C
+preprocessor macro.
+
+@end table
 
 @node ARC-Regs
 @subsection Register Names
 
 @cindex ARC register names
 @cindex register names, ARC
-*TODO*
+The ARC assembler uses the following register names for its core
+registers:
+
+@table @code
+@item r0-r31
+@cindex core general registers, ARC
+@cindex ARC core general registers
+The core general registers.  Registers @code{r26} through @code{r31}
+have special functions, and are usually referred to by those synonyms.
+
+@item gp
+@cindex global pointer, ARC
+@cindex ARC global pointer
+The global pointer and a synonym for @code{r26}.
+
+@item fp
+@cindex frame pointer, ARC
+@cindex ARC frame pointer
+The frame pointer and a synonym for @code{r27}.
+
+@item sp
+@cindex stack pointer, ARC
+@cindex ARC stack pointer
+The stack pointer and a synonym for @code{r28}.
+
+@item ilink1
+@cindex level 1 interrupt link register, ARC
+@cindex ARC level 1 interrupt link register
+For ARC 600 and ARC 700, the level 1 interrupt link register and a
+synonym for @code{r29}.  Not supported for ARCv2.
+
+@item ilink
+@cindex interrupt link register, ARC
+@cindex ARC interrupt link register
+For ARCv2, the interrupt link register and a synonym for @code{r29}.
+Not supported for ARC 600 and ARC 700.
+
+@item ilink2
+@cindex level 2 interrupt link register, ARC
+@cindex ARC level 2 interrupt link register
+For ARC 600 and ARC 700, the level 2 interrupt link register and a
+synonym for @code{r30}.  Not supported for ARC v2.
+
+@item blink
+@cindex link register, ARC
+@cindex ARC link register
+The link register and a synonym for @code{r31}.
+
+@item r32-r59
+@cindex extension core registers, ARC
+@cindex ARC extension core registers
+The extension core registers.
+
+@item lp_count
+@cindex loop counter, ARC
+@cindex ARC loop counter
+The loop count register.
+
+@item pcl
+@cindex word aligned program counter, ARC
+@cindex ARC word aligned program counter
+The word aligned program counter.
+
+@end table
 
+In addition the ARC processor has a large number of @emph{auxiliary
+registers}.  The precise set depends on the extensions being
+supported, but the following baseline set are always defined:
 
-@node ARC Floating Point
-@section Floating Point
+@table @code
+@item identity
+@cindex Processor Identification register, ARC
+@cindex ARC Processor Identification register
+Processor Identification register.  Auxiliary register address 0x4.
+
+@item pc
+@cindex Program Counter, ARC
+@cindex ARC Program Counter
+Program Counter.  Auxiliary register address 0x6.
+
+@item status32
+@cindex Status register, ARC
+@cindex ARC Status register
+Status register.  Auxiliary register address 0x0a.
+
+@item bta
+@cindex Branch Target Address, ARC
+@cindex ARC Branch Target Address
+Branch Target Address.  Auxiliary register address 0x412.
+
+@item ecr
+@cindex Exception Cause Register, ARC
+@cindex ARC Exception Cause Register
+Exception Cause Register.  Auxiliary register address 0x403.
+
+@item int_vector_base
+@cindex Interrupt Vector Base address, ARC
+@cindex ARC Interrupt Vector Base address
+Interrupt Vector Base address.  Auxiliary register address 0x25.
+
+@item status32_p0
+@cindex Stored STATUS32 register on entry to level P0 interrupts, ARC
+@cindex ARC Stored STATUS32 register on entry to level P0 interrupts
+Stored STATUS32 register on entry to level P0 interrupts.  Auxiliary
+register address 0xb.
+
+@item aux_user_sp
+@cindex Saved User Stack Pointer, ARC
+@cindex ARC Saved User Stack Pointer
+Saved User Stack Pointer.  Auxiliary register address 0xd.
+
+@item eret
+@cindex Exception Return Address, ARC
+@cindex ARC Exception Return Address
+Exception Return Address.  Auxiliary register address 0x400.
+
+@item erbta
+@cindex BTA saved on exception entry, ARC
+@cindex ARC BTA saved on exception entry
+BTA saved on exception entry.  Auxiliary register address 0x401.
+
+@item erstatus
+@cindex STATUS32 saved on exception, ARC
+@cindex ARC STATUS32 saved on exception
+STATUS32 saved on exception.  Auxiliary register address 0x402.
+
+@item bcr_ver
+@cindex Build Configuration Registers Version, ARC
+@cindex ARC Build Configuration Registers Version
+Build Configuration Registers Version.  Auxiliary register address 0x60.
+
+@item bta_link_build
+@cindex Build configuration for: BTA Registers, ARC
+@cindex ARC Build configuration for: BTA Registers
+Build configuration for: BTA Registers.  Auxiliary register address 0x63.
+
+@item vecbase_ac_build
+@cindex Build configuration for: Interrupts, ARC
+@cindex ARC Build configuration for: Interrupts
+Build configuration for: Interrupts.  Auxiliary register address 0x68.
+
+@item rf_build
+@cindex Build configuration for: Core Registers, ARC
+@cindex ARC Build configuration for: Core Registers
+Build configuration for: Core Registers.  Auxiliary register address 0x6e.
+
+@item dccm_build
+@cindex DCCM RAM Configuration Register, ARC
+@cindex ARC DCCM RAM Configuration Register
+DCCM RAM Configuration Register.  Auxiliary register address 0xc1.
 
-@cindex floating point, ARC (@sc{ieee})
-@cindex ARC floating point (@sc{ieee})
-The ARC core does not currently have hardware floating point
-support. Software floating point support is provided by @code{GCC}
-and uses @sc{ieee} floating-point numbers.
+@end table
 
+Additional auxiliary register names are defined according to the
+processor architecture version and extensions selected by the options.
 
 @node ARC Directives
 @section ARC Machine Directives
@@ -131,205 +313,106 @@ machine directives:
 
 @table @code
 
-@cindex @code{2byte} directive, ARC
-@item .2byte @var{expressions}
-*TODO*
-
-@cindex @code{3byte} directive, ARC
-@item .3byte @var{expressions}
-*TODO*
-
-@cindex @code{4byte} directive, ARC
-@item .4byte @var{expressions}
-*TODO*
-
-@cindex @code{extAuxRegister} directive, ARC
-@item .extAuxRegister @var{name},@var{address},@var{mode}
-The ARCtangent A4 has extensible auxiliary register space.  The
-auxiliary registers can be defined in the assembler source code by
-using this directive.  The first parameter is the @var{name} of the
-new auxiallry register.  The second parameter is the @var{address} of
-the register in the auxiliary register memory map for the variant of
-the ARC.  The third parameter specifies the @var{mode} in which the
-register can be operated is and it can be one of:
-
+@cindex @code{lcomm} directive
+@item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
+Reserve @var{length} (an absolute expression) bytes for a local common
+denoted by @var{symbol}.  The section and value of @var{symbol} are
+those of the new local common.  The addresses are allocated in the bss
+section, so that at run-time the bytes start off zeroed.  Since
+@var{symbol} is not declared global, it is normally not visible to
+@code{@value{LD}}.  The optional third parameter, @var{alignment},
+specifies the desired alignment of the symbol in the bss section,
+specified as a byte boundary (for example, an alignment of 16 means
+that the least significant 4 bits of the address should be zero).  The
+alignment must be an absolute expression, and it must be a power of
+two.  If no alignment is specified, as will set the alignment to the
+largest power of two less than or equal to the size of the symbol, up
+to a maximum of 16.
+
+@cindex @code{lcommon} directive
+@item .lcommon @var{symbol} , @var{length}[, @var{alignment}]
+The same as @code{lcomm} directive.
+
+@cindex @code{cpu} directive, ARC
+@cindex @code{cpu} directive, ARC
+The @code{.cpu} directive must be followed by the desired core
+version.  Permitted values for CPU are:
 @table @code
-@item r          (readonly)
-@item w          (write only)
-@item r|w        (read or write)
-@end table
-
-For example:
-
-@smallexample
-  .extAuxRegister mulhi,0x12,w
-@end smallexample
+@item ARC600
+Assemble for the ARC600 instruction set.
 
-This specifies an extension auxiliary register called @emph{mulhi}
-which is at address 0x12 in the memory space and which is only
-writable.
+@item ARC700
+Assemble for the ARC700 instruction set.
 
-@cindex @code{extCondCode} directive, ARC
-@item .extCondCode @var{suffix},@var{value}
-The condition codes on the ARCtangent A4 are extensible and can be
-specified by means of this assembler directive.  They are specified
-by the suffix and the value for the condition code.  They can be used to
-specify extra condition codes with any values.  For example:
+@item EM
+Assemble for the ARC EM instruction set.
 
-@smallexample
-  .extCondCode is_busy,0x14
+@item HS
+Assemble for the ARC HS instruction set.
 
-   add.is_busy  r1,r2,r3
-   bis_busy     _main
-@end smallexample
-
-@cindex @code{extCoreRegister} directive, ARC
-@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
-Specifies an extension core register @var{name} for the application.
-This allows a register @var{name} with a valid @var{regnum} between 0
-and 60, with the following as valid values for @var{mode}
-
-@table @samp
-@item @emph{r}   (readonly)
-@item @emph{w}   (write only)
-@item @emph{r|w} (read or write)
 @end table
 
-
-The other parameter gives a description of the register having a
-@var{shortcut} in the pipeline.  The valid values are:
-
-@table @code
-@item can_shortcut
-@item cannot_shortcut
+Note: the @code{.cpu} directive overrides the command line option
+@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
+consistent between the two.
 @end table
 
-For example:
-
-@smallexample
-  .extCoreRegister mlo,57,r,can_shortcut
-@end smallexample
-
-This defines an extension core register mlo with the value 57 which
-can shortcut the pipeline.
-
-@cindex @code{extInstruction} directive, ARC
-@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass}
-The ARCtangent A4 allows the user to specify extension instructions.
-The extension instructions are not macros.  The assembler creates
-encodings for use of these instructions according to the specification
-by the user.  The parameters are:
-
-@itemize @bullet
-@item @var{name}
-Name of the extension instruction
-
-@item @var{opcode}
-Opcode to be used. (Bits 27:31 in the encoding).  Valid values
-0x10-0x1f or 0x03
+@node ARC Modifiers
+@section ARC Assembler Modifiers
 
-@item @var{subopcode}
-Subopcode to be used.  Valid values are from 0x09-0x3f.  However the
-correct value also depends on @var{syntaxclass}
-
-@item @var{suffixclass}
-Determines the kinds of suffixes to be allowed.  Valid values are
-@code{SUFFIX_NONE}, @code{SUFFIX_COND},
-@code{SUFFIX_FLAG} which indicates the absence or presence of
-conditional suffixes and flag setting by the extension instruction.
-It is also possible to specify that an instruction sets the flags and
-is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
-
-@item @var{syntaxclass}
-Determines the syntax class for the instruction.  It can have the
-following values:
+The following additional assembler modifiers have been added for
+position-independent code.  These modifiers are available only with
+the ARC 700 and above processors and generate relocation entries,
+which are interpreted by the linker as follows:
 
 @table @code
-@item @code{SYNTAX_2OP}:
-2 Operand Instruction
-@item @code{SYNTAX_3OP}:
-3 Operand Instruction
-@end table
-
-In addition there could be modifiers for the syntax class as described
-below:
-
-@itemize @minus
-Syntax Class Modifiers are:
-
-@item @code{OP1_MUST_BE_IMM}:
-Modifies syntax class SYNTAX_3OP,  specifying that the first operand
-of a three-operand instruction must be an immediate (i.e., the result
-is discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it with
-SYNTAX_3OP as given in the example below.  This could usually be used
-to set the flags using specific instructions and not retain results.
+@item @@pcl(@var{symbol})
+@cindex @@pcl(@var{symbol}), ARC modifier
+Relative distance of @var{symbol}'s from the current program counter
+location.
+
+@item @@gotpc(@var{symbol})
+@cindex @@gotpc(@var{symbol}), ARC modifier
+Relative distance of @var{symbol}'s Global Offset Table entry from the
+current program counter location.
+
+@item @@gotoff(@var{symbol})
+@cindex @@gotoff(@var{symbol}), ARC modifier
+Distance of @var{symbol} from the base of the Global Offset Table.
+
+@item @@plt(@var{symbol})
+@cindex @@plt(@var{symbol}), ARC modifier
+Distance of @var{symbol}'s Procedure Linkage Table entry from the
+current program counter.  This is valid only with branch and link
+instructions and PC-relative calls.
+
+@item @@sda(@var{symbol})
+@cindex @@sda(@var{symbol}), ARC modifier
+Relative distance of @var{symbol} from the base of the Small Data
+Pointer.
 
-@item @code{OP1_IMM_IMPLIED}:
-Modifies syntax class SYNTAX_20P, it specifies that there is an
-implied immediate destination operand which does not appear in the
-syntax.  For example, if the source code contains an instruction like:
-
-@smallexample
-inst r1,r2
-@end smallexample
-
-it really means that the first argument is an implied immediate (that
-is, the result is discarded).  This is the same as though the source
-code were: inst 0,r1,r2.  You use OP1_IMM_IMPLIED by bitwise ORing it
-with SYNTAX_20P.
-
-@end itemize
-@end itemize
-
-For example, defining 64-bit multiplier with immediate operands:
-
-@smallexample
-.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
-                SYNTAX_3OP|OP1_MUST_BE_IMM
-@end smallexample
-
-The above specifies an extension instruction called mp64 which has 3 operands,
-sets the flags, can be used with a condition code, for which the
-first operand is an immediate.  (Equivalent to discarding the result
-of the operation).
-
-@smallexample
- .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
-@end smallexample
-
-This describes a 2 operand instruction with an implicit first
-immediate operand.  The result of this operation would be discarded.
-
-@cindex @code{half} directive, ARC
-@item .half @var{expressions}
-*TODO*
-
-@cindex @code{long} directive, ARC
-@item .long @var{expressions}
-*TODO*
+@end table
 
-@cindex @code{option} directive, ARC
-@item .option @var{arc|arc5|arc6|arc7|arc8}
-The @code{.option} directive must be followed by the desired core
-version. Again @code{arc} is an alias for
-@code{arc@value{ARC_CORE_DEFAULT}}.
+@node ARC Symbols
+@section ARC Pre-defined Symbols
 
-Note: the @code{.option} directive overrides the command line option
-@code{-marc}; a warning is emitted when the version is not consistent
-between the two - even for the implicit default core version
-(arc@value{ARC_CORE_DEFAULT}).
+The following assembler symbols will prove useful when developing
+position-independent code.  These symbols are available only with the
+ARC 700 and above processors.
 
-@cindex @code{short} directive, ARC
-@item .short @var{expressions}
-*TODO*
+@table @code
+@item __GLOBAL_OFFSET_TABLE__
+@cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol
+Symbol referring to the base of the Global Offset Table.
 
-@cindex @code{word} directive, ARC
-@item .word @var{expressions}
-*TODO*
+@item __DYNAMIC__
+@cindex __DYNAMIC__, ARC pre-defined symbol
+An alias for the Global Offset Table
+@code{Base__GLOBAL_OFFSET_TABLE__}.  It can be used only with
+@code{@@gotpc} modifiers.
 
 @end table
 
-
 @node ARC Opcodes
 @section Opcodes
 
@@ -337,4 +420,4 @@ between the two - even for the implicit default core version
 @cindex opcodes for ARC
 
 For information on the ARC instruction set, see @cite{ARC Programmers
-Reference Manual}, ARC International (www.arc.com)
+Reference Manual}, available where you download the processor IP library.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index ba63994..814d0a6 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,80 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * gas/arc/adc.s: Update test for ARCv1/ARCv2.
+       * gas/arc/adc.d: Expected output.
+       * gas/arc/add.s: Update test for ARCv1/ARCv2.
+       * gas/arc/add.d: Expected output.
+       * gas/arc/and.s: Update test for ARCv1/ARCv2.
+       * gas/arc/and.d: Expected output.
+       * gas/arc/arc.exp: Cleanup.
+       * gas/arc/asl.s: Update test for ARCv1/ARCv2.
+       * gas/arc/asl.d: Expected output.
+       * gas/arc/asr.s: Update test for ARCv1/ARCv2.
+       * gas/arc/asr.d: Expected output.
+       * gas/arc/b.s: Update test for ARCv1/ARCv2.
+       * gas/arc/b.d: Expected output.
+       * gas/arc/bic.s: Update test for ARCv1/ARCv2.
+       * gas/arc/bic.d: Expected output.
+       * gas/arc/bl.s: Update test for ARCv1/ARCv2.
+       * gas/arc/bl.d: Expected output.
+       * gas/arc/brk.s: Update test for ARCv1/ARCv2.
+       * gas/arc/brk.d: Expected output.
+       * gas/arc/extb.s: Update test for ARCv1/ARCv2.
+       * gas/arc/extb.d: Expected output.
+       * gas/arc/extw.s: Update test for ARCv1/ARCv2.
+       * gas/arc/extw.d: Expected output.
+       * gas/arc/flag.d: Update output for ARCv1/ARCv2.
+       * gas/arc/j.s: Update test for ARCv1/ARCv2.
+       * gas/arc/j.d: Expected output.
+       * gas/arc/jl.s: Update test for ARCv1/ARCv2.
+       * gas/arc/jl.d: Expected output.
+       * gas/arc/ld.s: Update test for ARCv1/ARCv2.
+       * gas/arc/ld.d: Expected output.
+       * gas/arc/ld2.s: Update test for ARCv1/ARCv2.
+       * gas/arc/ld2.d: Expected output.
+       * gas/arc/lp.s: Update test for ARCv1/ARCv2.
+       * gas/arc/lp.d: Expected output.
+       * gas/arc/lsr.s: Update test for ARCv1/ARCv2.
+       * gas/arc/lsr.d: Expected output.
+       * gas/arc/mov.s: Update test for ARCv1/ARCv2.
+       * gas/arc/mov.d: Expected output.
+       * gas/arc/nop.s: Update test for ARCv1/ARCv2.
+       * gas/arc/nop.d: Expected output.
+       * gas/arc/or.s: Update test for ARCv1/ARCv2.
+       * gas/arc/or.d: Expected output.
+       * gas/arc/rlc.s: Update test for ARCv1/ARCv2.
+       * gas/arc/rlc.d: Expected output.
+       * gas/arc/ror.s: Update test for ARCv1/ARCv2.
+       * gas/arc/ror.d: Expected output.
+       * gas/arc/rrc.s: Update test for ARCv1/ARCv2.
+       * gas/arc/rrc.d: Expected output.
+       * gas/arc/sbc.s: Update test for ARCv1/ARCv2.
+       * gas/arc/sbc.d: Expected output.
+       * gas/arc/sexb.s: Update test for ARCv1/ARCv2.
+       * gas/arc/sexb.d: Expected output.
+       * gas/arc/sexw.s: Update test for ARCv1/ARCv2.
+       * gas/arc/sexw.d: Expected output.
+       * gas/arc/sleep.s: Update test for ARCv1/ARCv2.
+       * gas/arc/sleep.d: Expected output.
+       * gas/arc/st.s: Update test for ARCv1/ARCv2.
+       * gas/arc/st.d: Expected output.
+       * gas/arc/sub.s: Update test for ARCv1/ARCv2.
+       * gas/arc/sub.d: Expected output.
+       * gas/arc/swi.d: Update expected output for ARCv1/ARCv2.
+       * gas/arc/warn.exp: Cleanup
+       * gas/arc/xor.s: Update test for ARCv1/ARCv2.
+       * gas/arc/xor.d: Expected output.
+       * gas/arc/alias.d: Removed.
+       * gas/arc/alias.s: Likewise.
+       * gas/arc/branch.d: Likewise.
+       * gas/arc/branch.s: Likewise.
+       * gas/arc/insn3.d: Likewise.
+       * gas/arc/insn3.s: Likewise.
+       * gas/arc/math.d: Likewise.
+       * gas/arc/math.s: Likewise.
+       * gas/arc/sshift.d: Likewise.
+       * gas/arc/sshift.s: Likewise.
+
 2015-10-02  Renlin Li <renlin.li@arm.com>
 
        * gas/aarch64/reloc-tlsdesc_off_g0_nc.d: New.

diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index 0af9bd0..6aaf4b8 100644 (file)
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -152,7 +152,7 @@ case $target_triplet in {
        run_dump_test redef
        # These targets fail redef2 because they disallow redefined
        # symbols on relocs.
-       setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*"
+       setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "arc-*-*"
        setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*"
        run_dump_test redef2
        setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*"

diff --git a/gas/testsuite/gas/arc/adc.d b/gas/testsuite/gas/arc/adc.d
index 7cb8523..b6cf253 100644 (file)
--- a/gas/testsuite/gas/arc/adc.d
+++ b/gas/testsuite/gas/arc/adc.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 48     48008400     adc        r0,r1,r2
-   4:  00 b8 4d 4b     4b4db800     adc        gp,fp,sp
-   8:  00 3e af 4b     4baf3e00     adc        ilink1,ilink2,blink
-   c:  00 f8 1d 4f     4f1df800     adc        r56,r59,lp_count
-  10:  00 fe 00 48     4800fe00     adc        r0,r1,0
-  14:  00 84 1f 48     481f8400     adc        r0,0,r2
-  18:  00 84 e0 4f     4fe08400     adc        0,r1,r2
-  1c:  ff ff 00 48     4800ffff     adc        r0,r1,-1
-  20:  ff 85 1f 48     481f85ff     adc        r0,-1,r2
-  24:  00 84 e0 4f     4fe08400     adc        0,r1,r2
-  28:  ff fe 00 48     4800feff     adc        r0,r1,255
-  2c:  ff 84 1f 48     481f84ff     adc        r0,255,r2
-  30:  00 84 e0 4f     4fe08400     adc        0,r1,r2
-  34:  00 ff 00 48     4800ff00     adc        r0,r1,-256
-  38:  00 85 1f 48     481f8500     adc        r0,-256,r2
-  3c:  00 84 e0 4f     4fe08400     adc        0,r1,r2
-  40:  00 fc 00 48     4800fc00     adc        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 48     481f0400     adc        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 48     481ffcff     adc        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 48     481f7eff     adc        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 48     4800fc00     adc        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 48     48008400     adc        r0,r1,r2
-  6c:  00 0a 62 48     48620a00     adc        r3,r4,r5
-  70:  01 90 c3 48     48c39001     adc.z      r6,r7,r8
-  74:  01 16 25 49     49251601     adc.z      r9,r10,r11
-  78:  02 9c 86 49     49869c02     adc.nz     r12,r13,r14
-  7c:  02 22 e8 49     49e82202     adc.nz     r15,r16,r17
-  80:  03 a8 49 4a     4a49a803     adc.p      r18,r19,r20
-  84:  03 2e ab 4a     4aab2e03     adc.p      r21,r22,r23
-  88:  04 b4 0c 4b     4b0cb404     adc.n      r24,r25,gp
-  8c:  04 3a 6e 4b     4b6e3a04     adc.n      fp,sp,ilink1
-  90:  05 c0 cf 4b     4bcfc005     adc.c      ilink2,blink,r32
-  94:  05 46 31 4c     4c314605     adc.c      r33,r34,r35
-  98:  05 cc 92 4c     4c92cc05     adc.c      r36,r37,r38
-  9c:  06 52 f4 4c     4cf45206     adc.nc     r39,r40,r41
-  a0:  06 d8 55 4d     4d55d806     adc.nc     r42,r43,r44
-  a4:  06 5e b7 4d     4db75e06     adc.nc     r45,r46,r47
-  a8:  07 e4 18 4e     4e18e407     adc.v      r48,r49,r50
-  ac:  07 6a 1a 4f     4f1a6a07     adc.v      r56,r52,r53
-  b0:  08 f0 1b 4f     4f1bf008     adc.nv     r56,r55,r56
-  b4:  08 76 1d 4f     4f1d7608     adc.nv     r56,r58,r59
-  b8:  09 00 9e 4f     4f9e0009     adc.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 48     48007c0a     adc.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 48     483f020b     adc.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 48     487f060d     adc.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 4f     4fdf080e     adc.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 4f     4fc2fc0f     adc.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 48     48008500     adc.f      r0,r1,r2
-  e8:  01 fa 00 48     4800fa01     adc.f      r0,r1,1
-  ec:  01 84 1e 48     481e8401     adc.f      r0,1,r2
-  f0:  00 85 e0 4f     4fe08500     adc.f      0,r1,r2
-  f4:  00 fd 00 48     4800fd00     adc.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 48     481f0500     adc.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 48     48008501     adc.z.f    r0,r1,r2
- 108:  02 fd 00 48     4800fd02     adc.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 48     481f050b     adc.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 4f     4fc08509     adc.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 48     4800fd0c     adc.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 48     481f050a     adc.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2101 0080                  adc     r0,r1,r2
+0x[0-9a-f]+ 2301 371a                  adc     gp,fp,sp
+0x[0-9a-f]+ 2601 37dd                  adc     ilink,r30,blink
+0x[0-9a-f]+ 2141 0000                  adc     r0,r1,0
+0x[0-9a-f]+ 2601 7080 0000 0000        adc     r0,0,r2
+0x[0-9a-f]+ 2101 00be                  adc     0,r1,r2
+0x[0-9a-f]+ 2101 0f80 ffff ffff        adc     r0,r1,0xffffffff
+0x[0-9a-f]+ 2601 7080 ffff ffff        adc     r0,0xffffffff,r2
+0x[0-9a-f]+ 2101 0f80 0000 00ff        adc     r0,r1,0xff
+0x[0-9a-f]+ 2601 7080 0000 00ff        adc     r0,0xff,r2
+0x[0-9a-f]+ 2101 0f80 ffff ff00        adc     r0,r1,0xffffff00
+0x[0-9a-f]+ 2601 7080 ffff ff00        adc     r0,0xffffff00,r2
+0x[0-9a-f]+ 2101 0f80 0000 0100        adc     r0,r1,0x100
+0x[0-9a-f]+ 2601 7080 ffff feff        adc     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2601 7f80 0000 0100        adc     r0,0x100,0x100
+0x[0-9a-f]+ 2101 0f80 0000 0000        adc     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c1 0080                  adc     r0,r0,r2
+0x[0-9a-f]+ 23c1 0140                  adc     r3,r3,r5
+0x[0-9a-f]+ 26c1 0201                  adc.eq  r6,r6,r8
+0x[0-9a-f]+ 21c1 12c1                  adc.eq  r9,r9,r11
+0x[0-9a-f]+ 24c1 1382                  adc.ne  r12,r12,r14
+0x[0-9a-f]+ 27c1 1442                  adc.ne  r15,r15,r17
+0x[0-9a-f]+ 22c1 2503                  adc.p   r18,r18,r20
+0x[0-9a-f]+ 25c1 25c3                  adc.p   r21,r21,r23
+0x[0-9a-f]+ 20c1 3684                  adc.n   r24,r24,gp
+0x[0-9a-f]+ 23c1 3744                  adc.n   fp,fp,ilink
+0x[0-9a-f]+ 26c1 37c5                  adc.c   r30,r30,blink
+0x[0-9a-f]+ 23c1 00c5                  adc.c   r3,r3,r3
+0x[0-9a-f]+ 23c1 0205                  adc.c   r3,r3,r8
+0x[0-9a-f]+ 23c1 0106                  adc.nc  r3,r3,r4
+0x[0-9a-f]+ 24c1 0106                  adc.nc  r4,r4,r4
+0x[0-9a-f]+ 24c1 01c6                  adc.nc  r4,r4,r7
+0x[0-9a-f]+ 24c1 0147                  adc.v   r4,r4,r5
+0x[0-9a-f]+ 25c1 0147                  adc.v   r5,r5,r5
+0x[0-9a-f]+ 25c1 0148                  adc.nv  r5,r5,r5
+0x[0-9a-f]+ 25c1 0148                  adc.nv  r5,r5,r5
+0x[0-9a-f]+ 26c1 0009                  adc.gt  r6,r6,r0
+0x[0-9a-f]+ 20c1 002a                  adc.ge  r0,r0,0
+0x[0-9a-f]+ 21c1 006b                  adc.lt  r1,r1,0x1
+0x[0-9a-f]+ 23c1 00ed                  adc.hi  r3,r3,0x3
+0x[0-9a-f]+ 24c1 012e                  adc.ls  r4,r4,0x4
+0x[0-9a-f]+ 25c1 016f                  adc.pnz r5,r5,0x5
+0x[0-9a-f]+ 2101 8080                  adc.f   r0,r1,r2
+0x[0-9a-f]+ 2141 8040                  adc.f   r0,r1,0x1
+0x[0-9a-f]+ 2601 f080 0000 0001        adc.f   r0,0x1,r2
+0x[0-9a-f]+ 2101 80be                  adc.f   0,r1,r2
+0x[0-9a-f]+ 2101 8f80 0000 0200        adc.f   r0,r1,0x200
+0x[0-9a-f]+ 2601 f080 0000 0200        adc.f   r0,0x200,r2
+0x[0-9a-f]+ 21c1 8081                  adc.f.eq        r1,r1,r2
+0x[0-9a-f]+ 20c1 8022                  adc.f.ne        r0,r0,0
+0x[0-9a-f]+ 22c1 808b                  adc.f.lt        r2,r2,r2
+0x[0-9a-f]+ 26c1 f0a9 0000 0001        adc.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 26c1 ff8c 0000 0200        adc.f.le        0,0x200,0x200
+0x[0-9a-f]+ 26c1 f0aa 0000 0200        adc.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/adc.s b/gas/testsuite/gas/arc/adc.s
index 162f6b8..213f000 100644 (file)
--- a/gas/testsuite/gas/arc/adc.s
+++ b/gas/testsuite/gas/arc/adc.s
@@ -3,55 +3,50 @@
        adc r0,r1,r2
        adc r26,fp,sp
        adc ilink1,ilink2,blink
-       adc r56,r59,lp_count
 
        adc r0,r1,0
        adc r0,0,r2
        adc 0,r1,r2
        adc r0,r1,-1
        adc r0,-1,r2
-       adc -1,r1,r2
        adc r0,r1,255
        adc r0,255,r2
-       adc 255,r1,r2
        adc r0,r1,-256
        adc r0,-256,r2
-       adc -256,r1,r2
 
        adc r0,r1,256
        adc r0,-257,r2
 
-       adc r0,255,256
-       adc r0,256,255
+       adc r0,256,256
 
        adc r0,r1,foo
 
-       adc.al r0,r1,r2
-       adc.ra r3,r4,r5
-       adc.eq r6,r7,r8
-       adc.z r9,r10,r11
-       adc.ne r12,r13,r14
-       adc.nz r15,r16,r17
-       adc.pl r18,r19,r20
-       adc.p r21,r22,r23
-       adc.mi r24,r25,r26
-       adc.n r27,r28,r29
-       adc.cs r30,r31,r32
-       adc.c r33,r34,r35
-       adc.lo r36,r37,r38
-       adc.cc r39,r40,r41
-       adc.nc r42,r43,r44
-       adc.hs r45,r46,r47
-       adc.vs r48,r49,r50
-       adc.v r56,r52,r53
-       adc.vc r56,r55,r56
-       adc.nv r56,r58,r59
-       adc.gt r60,r60,r0
+       adc.al r0,r0,r2
+       adc.ra r3,r3,r5
+       adc.eq r6,r6,r8
+       adc.z  r9,r9,r11
+       adc.ne r12,r12,r14
+       adc.nz r15,r15,r17
+       adc.pl r18,r18,r20
+       adc.p  r21,r21,r23
+       adc.mi r24,r24,r26
+       adc.n  r27,r27,r29
+       adc.cs r30,r30,r31
+       adc.c  r3,r3,r3
+       adc.lo r3,r3,r8
+       adc.cc r3,r3,r4
+       adc.nc r4,r4,r4
+       adc.hs r4,r4,r7
+       adc.vs r4,r4,r5
+       adc.v  r5,r5,r5
+       adc.vc r5,r5,r5
+       adc.nv r5,r5,r5
+       adc.gt r6,r6,r0
        adc.ge r0,r0,0
-       adc.lt r1,1,r1
-       adc.hi r3,3,r3
-       adc.ls 4,4,r4
-       adc.pnz 5,r5,5
+       adc.lt r1,r1,1
+       adc.hi r3,r3,3
+       adc.ls r4,r4,4
+       adc.pnz r5,r5,5
 
        adc.f r0,r1,r2
        adc.f r0,r1,1
@@ -60,9 +55,9 @@
        adc.f r0,r1,512
        adc.f r0,512,r2
 
-       adc.eq.f r0,r1,r2
-       adc.ne.f r0,r1,0
-       adc.lt.f r0,0,r2
-       adc.gt.f 0,r1,r2
-       adc.le.f r0,r1,512
-       adc.ge.f r0,512,r2
+       adc.eq.f r1,r1,r2
+       adc.ne.f r0,r0,0
+       adc.lt.f r2,r2,r2
+       adc.gt.f 0,1,2
+       adc.le.f 0,512,512
+       adc.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/add.d b/gas/testsuite/gas/arc/add.d
index 864bc4d..e1cdc5c 100644 (file)
--- a/gas/testsuite/gas/arc/add.d
+++ b/gas/testsuite/gas/arc/add.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 40     40008400     add        r0,r1,r2
-   4:  00 b8 4d 43     434db800     add        gp,fp,sp
-   8:  00 3e af 43     43af3e00     add        ilink1,ilink2,blink
-   c:  00 f8 1d 47     471df800     add        r56,r59,lp_count
-  10:  00 fe 00 40     4000fe00     add        r0,r1,0
-  14:  00 84 1f 40     401f8400     add        r0,0,r2
-  18:  00 84 e0 47     47e08400     add        0,r1,r2
-  1c:  ff ff 00 40     4000ffff     add        r0,r1,-1
-  20:  ff 85 1f 40     401f85ff     add        r0,-1,r2
-  24:  00 84 e0 47     47e08400     add        0,r1,r2
-  28:  ff fe 00 40     4000feff     add        r0,r1,255
-  2c:  ff 84 1f 40     401f84ff     add        r0,255,r2
-  30:  00 84 e0 47     47e08400     add        0,r1,r2
-  34:  00 ff 00 40     4000ff00     add        r0,r1,-256
-  38:  00 85 1f 40     401f8500     add        r0,-256,r2
-  3c:  00 84 e0 47     47e08400     add        0,r1,r2
-  40:  00 fc 00 40     4000fc00     add        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 40     401f0400     add        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 40     401ffcff     add        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 40     401f7eff     add        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 40     4000fc00     add        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 40     40008400     add        r0,r1,r2
-  6c:  00 0a 62 40     40620a00     add        r3,r4,r5
-  70:  01 90 c3 40     40c39001     add.z      r6,r7,r8
-  74:  01 16 25 41     41251601     add.z      r9,r10,r11
-  78:  02 9c 86 41     41869c02     add.nz     r12,r13,r14
-  7c:  02 22 e8 41     41e82202     add.nz     r15,r16,r17
-  80:  03 a8 49 42     4249a803     add.p      r18,r19,r20
-  84:  03 2e ab 42     42ab2e03     add.p      r21,r22,r23
-  88:  04 b4 0c 43     430cb404     add.n      r24,r25,gp
-  8c:  04 3a 6e 43     436e3a04     add.n      fp,sp,ilink1
-  90:  05 c0 cf 43     43cfc005     add.c      ilink2,blink,r32
-  94:  05 46 31 44     44314605     add.c      r33,r34,r35
-  98:  05 cc 92 44     4492cc05     add.c      r36,r37,r38
-  9c:  06 52 f4 44     44f45206     add.nc     r39,r40,r41
-  a0:  06 d8 55 45     4555d806     add.nc     r42,r43,r44
-  a4:  06 5e b7 45     45b75e06     add.nc     r45,r46,r47
-  a8:  07 e4 18 46     4618e407     add.v      r48,r49,r50
-  ac:  07 6a 1a 47     471a6a07     add.v      r56,r52,r53
-  b0:  08 f0 1b 47     471bf008     add.nv     r56,r55,r56
-  b4:  08 76 1d 47     471d7608     add.nv     r56,r58,r59
-  b8:  09 00 9e 47     479e0009     add.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 40     40007c0a     add.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 40     403f020b     add.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 40     407f060d     add.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 47     47df080e     add.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 47     47c2fc0f     add.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 40     40008500     add.f      r0,r1,r2
-  e8:  01 fa 00 40     4000fa01     add.f      r0,r1,1
-  ec:  01 84 1e 40     401e8401     add.f      r0,1,r2
-  f0:  00 85 e0 47     47e08500     add.f      0,r1,r2
-  f4:  00 fd 00 40     4000fd00     add.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 40     401f0500     add.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 40     40008501     add.z.f    r0,r1,r2
- 108:  02 fd 00 40     4000fd02     add.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 40     401f050b     add.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 47     47c08509     add.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 40     4000fd0c     add.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 40     401f050a     add.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2100 0080                  add     r0,r1,r2
+0x[0-9a-f]+ 2300 371a                  add     gp,fp,sp
+0x[0-9a-f]+ 2600 37dd                  add     ilink,r30,blink
+0x[0-9a-f]+ 2140 0000                  add     r0,r1,0
+0x[0-9a-f]+ 2600 7080 0000 0000        add     r0,0,r2
+0x[0-9a-f]+ 2100 00be                  add     0,r1,r2
+0x[0-9a-f]+ 2100 0f80 ffff ffff        add     r0,r1,0xffffffff
+0x[0-9a-f]+ 2600 7080 ffff ffff        add     r0,0xffffffff,r2
+0x[0-9a-f]+ 2100 0f80 0000 00ff        add     r0,r1,0xff
+0x[0-9a-f]+ 2600 7080 0000 00ff        add     r0,0xff,r2
+0x[0-9a-f]+ 2100 0f80 ffff ff00        add     r0,r1,0xffffff00
+0x[0-9a-f]+ 2600 7080 ffff ff00        add     r0,0xffffff00,r2
+0x[0-9a-f]+ 2100 0f80 0000 0100        add     r0,r1,0x100
+0x[0-9a-f]+ 2600 7080 ffff feff        add     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2600 7f80 0000 0100        add     r0,0x100,0x100
+0x[0-9a-f]+ 2100 0f80 0000 0000        add     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c0 0080                  add     r0,r0,r2
+0x[0-9a-f]+ 23c0 0140                  add     r3,r3,r5
+0x[0-9a-f]+ 26c0 0201                  add.eq  r6,r6,r8
+0x[0-9a-f]+ 21c0 12c1                  add.eq  r9,r9,r11
+0x[0-9a-f]+ 24c0 1382                  add.ne  r12,r12,r14
+0x[0-9a-f]+ 27c0 1442                  add.ne  r15,r15,r17
+0x[0-9a-f]+ 22c0 2503                  add.p   r18,r18,r20
+0x[0-9a-f]+ 25c0 25c3                  add.p   r21,r21,r23
+0x[0-9a-f]+ 20c0 3684                  add.n   r24,r24,gp
+0x[0-9a-f]+ 23c0 3744                  add.n   fp,fp,ilink
+0x[0-9a-f]+ 26c0 37c5                  add.c   r30,r30,blink
+0x[0-9a-f]+ 23c0 00c5                  add.c   r3,r3,r3
+0x[0-9a-f]+ 23c0 0205                  add.c   r3,r3,r8
+0x[0-9a-f]+ 23c0 0106                  add.nc  r3,r3,r4
+0x[0-9a-f]+ 24c0 0106                  add.nc  r4,r4,r4
+0x[0-9a-f]+ 24c0 01c6                  add.nc  r4,r4,r7
+0x[0-9a-f]+ 24c0 0147                  add.v   r4,r4,r5
+0x[0-9a-f]+ 25c0 0147                  add.v   r5,r5,r5
+0x[0-9a-f]+ 25c0 0148                  add.nv  r5,r5,r5
+0x[0-9a-f]+ 25c0 0148                  add.nv  r5,r5,r5
+0x[0-9a-f]+ 26c0 0009                  add.gt  r6,r6,r0
+0x[0-9a-f]+ 20c0 002a                  add.ge  r0,r0,0
+0x[0-9a-f]+ 21c0 006b                  add.lt  r1,r1,0x1
+0x[0-9a-f]+ 23c0 00ed                  add.hi  r3,r3,0x3
+0x[0-9a-f]+ 24c0 012e                  add.ls  r4,r4,0x4
+0x[0-9a-f]+ 25c0 016f                  add.pnz r5,r5,0x5
+0x[0-9a-f]+ 2100 8080                  add.f   r0,r1,r2
+0x[0-9a-f]+ 2140 8040                  add.f   r0,r1,0x1
+0x[0-9a-f]+ 2600 f080 0000 0001        add.f   r0,0x1,r2
+0x[0-9a-f]+ 2100 80be                  add.f   0,r1,r2
+0x[0-9a-f]+ 2100 8f80 0000 0200        add.f   r0,r1,0x200
+0x[0-9a-f]+ 2600 f080 0000 0200        add.f   r0,0x200,r2
+0x[0-9a-f]+ 21c0 8081                  add.f.eq        r1,r1,r2
+0x[0-9a-f]+ 20c0 8022                  add.f.ne        r0,r0,0
+0x[0-9a-f]+ 22c0 808b                  add.f.lt        r2,r2,r2
+0x[0-9a-f]+ 26c0 f0a9 0000 0001        add.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 26c0 ff8c 0000 0200        add.f.le        0,0x200,0x200
+0x[0-9a-f]+ 26c0 f0aa 0000 0200        add.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/add.s b/gas/testsuite/gas/arc/add.s
index 8e74971..ffa747e 100644 (file)
--- a/gas/testsuite/gas/arc/add.s
+++ b/gas/testsuite/gas/arc/add.s
@@ -3,55 +3,50 @@
        add r0,r1,r2
        add r26,fp,sp
        add ilink1,ilink2,blink
-       add r56,r59,lp_count
 
        add r0,r1,0
        add r0,0,r2
        add 0,r1,r2
        add r0,r1,-1
        add r0,-1,r2
-       add -1,r1,r2
        add r0,r1,255
        add r0,255,r2
-       add 255,r1,r2
        add r0,r1,-256
        add r0,-256,r2
-       add -256,r1,r2
 
        add r0,r1,256
        add r0,-257,r2
 
-       add r0,255,256
-       add r0,256,255
+       add r0,256,256
 
        add r0,r1,foo
 
-       add.al r0,r1,r2
-       add.ra r3,r4,r5
-       add.eq r6,r7,r8
-       add.z r9,r10,r11
-       add.ne r12,r13,r14
-       add.nz r15,r16,r17
-       add.pl r18,r19,r20
-       add.p r21,r22,r23
-       add.mi r24,r25,r26
-       add.n r27,r28,r29
-       add.cs r30,r31,r32
-       add.c r33,r34,r35
-       add.lo r36,r37,r38
-       add.cc r39,r40,r41
-       add.nc r42,r43,r44
-       add.hs r45,r46,r47
-       add.vs r48,r49,r50
-       add.v r56,r52,r53
-       add.vc r56,r55,r56
-       add.nv r56,r58,r59
-       add.gt r60,r60,r0
+       add.al r0,r0,r2
+       add.ra r3,r3,r5
+       add.eq r6,r6,r8
+       add.z  r9,r9,r11
+       add.ne r12,r12,r14
+       add.nz r15,r15,r17
+       add.pl r18,r18,r20
+       add.p  r21,r21,r23
+       add.mi r24,r24,r26
+       add.n  r27,r27,r29
+       add.cs r30,r30,r31
+       add.c  r3,r3,r3
+       add.lo r3,r3,r8
+       add.cc r3,r3,r4
+       add.nc r4,r4,r4
+       add.hs r4,r4,r7
+       add.vs r4,r4,r5
+       add.v  r5,r5,r5
+       add.vc r5,r5,r5
+       add.nv r5,r5,r5
+       add.gt r6,r6,r0
        add.ge r0,r0,0
-       add.lt r1,1,r1
-       add.hi r3,3,r3
-       add.ls 4,4,r4
-       add.pnz 5,r5,5
+       add.lt r1,r1,1
+       add.hi r3,r3,3
+       add.ls r4,r4,4
+       add.pnz r5,r5,5
 
        add.f r0,r1,r2
        add.f r0,r1,1
@@ -60,9 +55,9 @@
        add.f r0,r1,512
        add.f r0,512,r2
 
-       add.eq.f r0,r1,r2
-       add.ne.f r0,r1,0
-       add.lt.f r0,0,r2
-       add.gt.f 0,r1,r2
-       add.le.f r0,r1,512
-       add.ge.f r0,512,r2
+       add.eq.f r1,r1,r2
+       add.ne.f r0,r0,0
+       add.lt.f r2,r2,r2
+       add.gt.f 0,1,2
+       add.le.f 0,512,512
+       add.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/alias.d b/gas/testsuite/gas/arc/alias.d
deleted file mode 100644 (file)
index b51acf6..0000000
--- a/gas/testsuite/gas/arc/alias.d
+++ /dev/null
@@ -1,68 +0,0 @@
-#objdump: -dr
-#name: @OC@
-
-# Test the @OC@ insn.
-
-.*: +file format elf32-.*arc
-
-Disassembly of section .text:
-00000000 @IC+0@008200  @OC@ r0,r1
-00000004 @IC+3@6e3800  @OC@ fp,sp
-00000008 @IC+0@1ffe00  @OC@ r0,0
-0000000c @IC+0@3fffff  @OC@ r1,-1
-00000010 @IC+7@e10400  @OC@ 0,r2
-00000014 @IC+7@e187ff  @OC@ -1,r3
-00000018 @IC+0@9ffeff  @OC@ r4,255
-0000001c @IC+7@e28aff  @OC@ 255,r5
-00000020 @IC+0@dfff00  @OC@ r6,-256
-00000024 @IC+7@e38f00  @OC@ -256,r7
-00000028 @IC+1@1f7c00  @OC@ r8,256
-00000030 @IC+1@3f7c00  @OC@ r9,-257
-00000038 @IC+7@c51400  @OC@ 511,r10
-00000040 @IC+1@7f7c00  @OC@ r11,1111638594
-00000048 @IC+7@c61800  @OC@ 305419896,r12
-00000050 @IC+7@ff7cff  @OC@ 255,256
-00000058 @IC+7@dffeff  @OC@ 256,255
-00000060 @IC+0@1f7c00  @OC@ r0,0
-               RELOC: 00000064 R_ARC_32 foo
-00000068 @IC+0@008200  @OC@ r0,r1
-0000006c @IC+0@620800  @OC@ r3,r4
-00000070 @IC+0@c38e01  @OC@.eq r6,r7
-00000074 @IC+1@251401  @OC@.eq r9,r10
-00000078 @IC+1@869a02  @OC@.ne r12,r13
-0000007c @IC+1@e82002  @OC@.ne r15,r16
-00000080 @IC+2@49a603  @OC@.p r18,r19
-00000084 @IC+2@ab2c03  @OC@.p r21,r22
-00000088 @IC+3@0cb204  @OC@.n r24,r25
-0000008c @IC+3@6e3804  @OC@.n fp,sp
-00000090 @IC+3@cfbe05  @OC@.c ilink2,blink
-00000094 @IC+4@314405  @OC@.c r33,r34
-00000098 @IC+4@92ca05  @OC@.c r36,r37
-0000009c @IC+4@f45006  @OC@.nc r39,r40
-000000a0 @IC+5@55d606  @OC@.nc r42,r43
-000000a4 @IC+5@b75c06  @OC@.nc r45,r46
-000000a8 @IC+6@18e207  @OC@.v r48,r49
-000000ac @IC+6@7a6807  @OC@.v r51,r52
-000000b0 @IC+6@dbee08  @OC@.nv r54,r55
-000000b4 @IC+7@3d7408  @OC@.nv r57,r58
-000000b8 @IC+7@9e7809  @OC@.gt lp_count,lp_count
-000000bc @IC+0@1f7c0a  @OC@.ge r0,0
-000000c4 @IC+7@c0820b  @OC@.lt 1,r1
-000000cc @IC+7@df7c0c  @OC@.le 2,2
-000000d4 @IC+0@61860d  @OC@.hi r3,r3
-000000d8 @IC+0@82080e  @OC@.ls r4,r4
-000000dc @IC+0@a28a0f  @OC@.pnz r5,r5
-000000e0 @IC+0@008300  @OC@.f r0,r1
-000000e4 @IC+0@5efa01  @OC@.f r2,1
-000000e8 @IC+7@a18601  @OC@.f 1,r3
-000000ec @IC+7@a20800  @OC@.f 0,r4
-000000f0 @IC+0@bf7d00  @OC@.f r5,512
-000000f8 @IC+7@c30d00  @OC@.f 512,r6
-00000100 @IC+7@df7d00  @OC@.f 512,512
-00000108 @IC+0@008301  @OC@.eq.f r0,r1
-0000010c @IC+0@3f7d02  @OC@.ne.f r1,0
-00000114 @IC+7@c1050b  @OC@.lt.f 0,r2
-0000011c @IC+7@c10509  @OC@.gt.f 1,r2
-00000124 @IC+0@1f7d0c  @OC@.le.f r0,512
-0000012c @IC+7@c1050a  @OC@.ge.f 512,r2
-00000134 @IC+7@df7d04  @OC@.n.f 512,512

diff --git a/gas/testsuite/gas/arc/alias.s b/gas/testsuite/gas/arc/alias.s
deleted file mode 100644 (file)
index d524440..0000000
--- a/gas/testsuite/gas/arc/alias.s
+++ /dev/null
@@ -1,76 +0,0 @@
-# @OC@ test
-
-# reg,reg
-       @OC@ r0,r1
-       @OC@ fp,sp
-
-# shimm values
-       @OC@ r0,0
-       @OC@ r1,-1
-       @OC@ 0,r2
-       @OC@ -1,r3
-       @OC@ r4,255
-       @OC@ 255,r5
-       @OC@ r6,-256
-       @OC@ -256,r7
-
-# limm values
-       @OC@ r8,256
-       @OC@ r9,-257
-       @OC@ 511,r10
-       @OC@ r11,0x42424242
-       @OC@ 0x12345678,r12
-
-# shimm and limm
-       @OC@ 255,256
-       @OC@ 256,255
-
-# symbols
-       @OC@ r0,foo
-
-# conditional execution
-       @OC@.al r0,r1
-       @OC@.ra r3,r4
-       @OC@.eq r6,r7
-       @OC@.z r9,r10
-       @OC@.ne r12,r13
-       @OC@.nz r15,r16
-       @OC@.pl r18,r19
-       @OC@.p r21,r22
-       @OC@.mi r24,r25
-       @OC@.n r27,r28
-       @OC@.cs r30,r31
-       @OC@.c r33,r34
-       @OC@.lo r36,r37
-       @OC@.cc r39,r40
-       @OC@.nc r42,r43
-       @OC@.hs r45,r46
-       @OC@.vs r48,r49
-       @OC@.v r51,r52
-       @OC@.vc r54,r55
-       @OC@.nv r57,r58
-       @OC@.gt r60,r60
-       @OC@.ge r0,0
-       @OC@.lt 1,r1
-       @OC@.le 2,2
-       @OC@.hi r3,r3
-       @OC@.ls r4,r4
-       @OC@.pnz r5,r5
-
-# flag setting
-       @OC@.f r0,r1
-       @OC@.f r2,1
-       @OC@.f 1,r3
-       @OC@.f 0,r4
-       @OC@.f r5,512
-       @OC@.f 512,r6
-       @OC@.f 512,512
-
-# conditional execution + flag setting
-       @OC@.eq.f r0,r1
-       @OC@.ne.f r1,0
-       @OC@.lt.f 0,r2
-       @OC@.gt.f 1,r2
-       @OC@.le.f r0,512
-       @OC@.ge.f 512,r2
-       @OC@.n.f 512,512

diff --git a/gas/testsuite/gas/arc/and.d b/gas/testsuite/gas/arc/and.d
index 5fca082..94b3c4d 100644 (file)
--- a/gas/testsuite/gas/arc/and.d
+++ b/gas/testsuite/gas/arc/and.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 60     60008400     and        r0,r1,r2
-   4:  00 b8 4d 63     634db800     and        gp,fp,sp
-   8:  00 3e af 63     63af3e00     and        ilink1,ilink2,blink
-   c:  00 f8 1d 67     671df800     and        r56,r59,lp_count
-  10:  00 fe 00 60     6000fe00     and        r0,r1,0
-  14:  00 84 1f 60     601f8400     and        r0,0,r2
-  18:  00 84 e0 67     67e08400     and        0,r1,r2
-  1c:  ff ff 00 60     6000ffff     and        r0,r1,-1
-  20:  ff 85 1f 60     601f85ff     and        r0,-1,r2
-  24:  00 84 e0 67     67e08400     and        0,r1,r2
-  28:  ff fe 00 60     6000feff     and        r0,r1,255
-  2c:  ff 84 1f 60     601f84ff     and        r0,255,r2
-  30:  00 84 e0 67     67e08400     and        0,r1,r2
-  34:  00 ff 00 60     6000ff00     and        r0,r1,-256
-  38:  00 85 1f 60     601f8500     and        r0,-256,r2
-  3c:  00 84 e0 67     67e08400     and        0,r1,r2
-  40:  00 fc 00 60     6000fc00     and        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 60     601f0400     and        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 60     601ffcff     and        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 60     601f7eff     and        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 60     6000fc00     and        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 60     60008400     and        r0,r1,r2
-  6c:  00 0a 62 60     60620a00     and        r3,r4,r5
-  70:  01 90 c3 60     60c39001     and.z      r6,r7,r8
-  74:  01 16 25 61     61251601     and.z      r9,r10,r11
-  78:  02 9c 86 61     61869c02     and.nz     r12,r13,r14
-  7c:  02 22 e8 61     61e82202     and.nz     r15,r16,r17
-  80:  03 a8 49 62     6249a803     and.p      r18,r19,r20
-  84:  03 2e ab 62     62ab2e03     and.p      r21,r22,r23
-  88:  04 b4 0c 63     630cb404     and.n      r24,r25,gp
-  8c:  04 3a 6e 63     636e3a04     and.n      fp,sp,ilink1
-  90:  05 c0 cf 63     63cfc005     and.c      ilink2,blink,r32
-  94:  05 46 31 64     64314605     and.c      r33,r34,r35
-  98:  05 cc 92 64     6492cc05     and.c      r36,r37,r38
-  9c:  06 52 f4 64     64f45206     and.nc     r39,r40,r41
-  a0:  06 d8 55 65     6555d806     and.nc     r42,r43,r44
-  a4:  06 5e b7 65     65b75e06     and.nc     r45,r46,r47
-  a8:  07 e4 18 66     6618e407     and.v      r48,r49,r50
-  ac:  07 6a 1a 67     671a6a07     and.v      r56,r52,r53
-  b0:  08 f0 1b 67     671bf008     and.nv     r56,r55,r56
-  b4:  08 76 1d 67     671d7608     and.nv     r56,r58,r59
-  b8:  09 00 9e 67     679e0009     and.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 60     60007c0a     and.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 60     603f020b     and.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 60     607f060d     and.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 67     67df080e     and.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 67     67c2fc0f     and.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 60     60008500     and.f      r0,r1,r2
-  e8:  01 fa 00 60     6000fa01     and.f      r0,r1,1
-  ec:  01 84 1e 60     601e8401     and.f      r0,1,r2
-  f0:  00 85 e0 67     67e08500     and.f      0,r1,r2
-  f4:  00 fd 00 60     6000fd00     and.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 60     601f0500     and.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 60     60008501     and.z.f    r0,r1,r2
- 108:  02 fd 00 60     6000fd02     and.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 60     601f050b     and.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 67     67c08509     and.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 60     6000fd0c     and.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 60     601f050a     and.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2104 0080                  and     r0,r1,r2
+0x[0-9a-f]+ 2304 371a                  and     gp,fp,sp
+0x[0-9a-f]+ 2604 37dd                  and     ilink,r30,blink
+0x[0-9a-f]+ 2144 0000                  and     r0,r1,0
+0x[0-9a-f]+ 2604 7080 0000 0000        and     r0,0,r2
+0x[0-9a-f]+ 2104 00be                  and     0,r1,r2
+0x[0-9a-f]+ 2104 0f80 ffff ffff        and     r0,r1,0xffffffff
+0x[0-9a-f]+ 2604 7080 ffff ffff        and     r0,0xffffffff,r2
+0x[0-9a-f]+ 2104 0f80 0000 00ff        and     r0,r1,0xff
+0x[0-9a-f]+ 2604 7080 0000 00ff        and     r0,0xff,r2
+0x[0-9a-f]+ 2104 0f80 ffff ff00        and     r0,r1,0xffffff00
+0x[0-9a-f]+ 2604 7080 ffff ff00        and     r0,0xffffff00,r2
+0x[0-9a-f]+ 2104 0f80 0000 0100        and     r0,r1,0x100
+0x[0-9a-f]+ 2604 7080 ffff feff        and     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2604 7f80 0000 0100        and     r0,0x100,0x100
+0x[0-9a-f]+ 2104 0f80 0000 0000        and     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c4 0080                  and     r0,r0,r2
+0x[0-9a-f]+ 23c4 0140                  and     r3,r3,r5
+0x[0-9a-f]+ 26c4 0201                  and.eq  r6,r6,r8
+0x[0-9a-f]+ 21c4 12c1                  and.eq  r9,r9,r11
+0x[0-9a-f]+ 24c4 1382                  and.ne  r12,r12,r14
+0x[0-9a-f]+ 27c4 1442                  and.ne  r15,r15,r17
+0x[0-9a-f]+ 22c4 2503                  and.p   r18,r18,r20
+0x[0-9a-f]+ 25c4 25c3                  and.p   r21,r21,r23
+0x[0-9a-f]+ 20c4 3684                  and.n   r24,r24,gp
+0x[0-9a-f]+ 23c4 3744                  and.n   fp,fp,ilink
+0x[0-9a-f]+ 26c4 37c5                  and.c   r30,r30,blink
+0x[0-9a-f]+ 23c4 00c5                  and.c   r3,r3,r3
+0x[0-9a-f]+ 23c4 0205                  and.c   r3,r3,r8
+0x[0-9a-f]+ 23c4 0106                  and.nc  r3,r3,r4
+0x[0-9a-f]+ 24c4 0106                  and.nc  r4,r4,r4
+0x[0-9a-f]+ 24c4 01c6                  and.nc  r4,r4,r7
+0x[0-9a-f]+ 24c4 0147                  and.v   r4,r4,r5
+0x[0-9a-f]+ 25c4 0147                  and.v   r5,r5,r5
+0x[0-9a-f]+ 25c4 0148                  and.nv  r5,r5,r5
+0x[0-9a-f]+ 25c4 0148                  and.nv  r5,r5,r5
+0x[0-9a-f]+ 26c4 0009                  and.gt  r6,r6,r0
+0x[0-9a-f]+ 20c4 002a                  and.ge  r0,r0,0
+0x[0-9a-f]+ 21c4 006b                  and.lt  r1,r1,0x1
+0x[0-9a-f]+ 23c4 00ed                  and.hi  r3,r3,0x3
+0x[0-9a-f]+ 24c4 012e                  and.ls  r4,r4,0x4
+0x[0-9a-f]+ 25c4 016f                  and.pnz r5,r5,0x5
+0x[0-9a-f]+ 2104 8080                  and.f   r0,r1,r2
+0x[0-9a-f]+ 2144 8040                  and.f   r0,r1,0x1
+0x[0-9a-f]+ 2604 f080 0000 0001        and.f   r0,0x1,r2
+0x[0-9a-f]+ 2104 80be                  and.f   0,r1,r2
+0x[0-9a-f]+ 2104 8f80 0000 0200        and.f   r0,r1,0x200
+0x[0-9a-f]+ 2604 f080 0000 0200        and.f   r0,0x200,r2
+0x[0-9a-f]+ 21c4 8081                  and.f.eq        r1,r1,r2
+0x[0-9a-f]+ 20c4 8022                  and.f.ne        r0,r0,0
+0x[0-9a-f]+ 22c4 808b                  and.f.lt        r2,r2,r2
+0x[0-9a-f]+ 26c4 f0a9 0000 0001        and.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 26c4 ff8c 0000 0200        and.f.le        0,0x200,0x200
+0x[0-9a-f]+ 26c4 f0aa 0000 0200        and.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/and.s b/gas/testsuite/gas/arc/and.s
index ddd7865..ecd11d5 100644 (file)
--- a/gas/testsuite/gas/arc/and.s
+++ b/gas/testsuite/gas/arc/and.s
@@ -3,55 +3,50 @@
        and r0,r1,r2
        and r26,fp,sp
        and ilink1,ilink2,blink
-       and r56,r59,lp_count
 
        and r0,r1,0
        and r0,0,r2
        and 0,r1,r2
        and r0,r1,-1
        and r0,-1,r2
-       and -1,r1,r2
        and r0,r1,255
        and r0,255,r2
-       and 255,r1,r2
        and r0,r1,-256
        and r0,-256,r2
-       and -256,r1,r2
 
        and r0,r1,256
        and r0,-257,r2
 
-       and r0,255,256
-       and r0,256,255
+       and r0,256,256
 
        and r0,r1,foo
 
-       and.al r0,r1,r2
-       and.ra r3,r4,r5
-       and.eq r6,r7,r8
-       and.z r9,r10,r11
-       and.ne r12,r13,r14
-       and.nz r15,r16,r17
-       and.pl r18,r19,r20
-       and.p r21,r22,r23
-       and.mi r24,r25,r26
-       and.n r27,r28,r29
-       and.cs r30,r31,r32
-       and.c r33,r34,r35
-       and.lo r36,r37,r38
-       and.cc r39,r40,r41
-       and.nc r42,r43,r44
-       and.hs r45,r46,r47
-       and.vs r48,r49,r50
-       and.v r56,r52,r53
-       and.vc r56,r55,r56
-       and.nv r56,r58,r59
-       and.gt r60,r60,r0
+       and.al r0,r0,r2
+       and.ra r3,r3,r5
+       and.eq r6,r6,r8
+       and.z  r9,r9,r11
+       and.ne r12,r12,r14
+       and.nz r15,r15,r17
+       and.pl r18,r18,r20
+       and.p  r21,r21,r23
+       and.mi r24,r24,r26
+       and.n  r27,r27,r29
+       and.cs r30,r30,r31
+       and.c  r3,r3,r3
+       and.lo r3,r3,r8
+       and.cc r3,r3,r4
+       and.nc r4,r4,r4
+       and.hs r4,r4,r7
+       and.vs r4,r4,r5
+       and.v  r5,r5,r5
+       and.vc r5,r5,r5
+       and.nv r5,r5,r5
+       and.gt r6,r6,r0
        and.ge r0,r0,0
-       and.lt r1,1,r1
-       and.hi r3,3,r3
-       and.ls 4,4,r4
-       and.pnz 5,r5,5
+       and.lt r1,r1,1
+       and.hi r3,r3,3
+       and.ls r4,r4,4
+       and.pnz r5,r5,5
 
        and.f r0,r1,r2
        and.f r0,r1,1
@@ -60,9 +55,9 @@
        and.f r0,r1,512
        and.f r0,512,r2
 
-       and.eq.f r0,r1,r2
-       and.ne.f r0,r1,0
-       and.lt.f r0,0,r2
-       and.gt.f 0,r1,r2
-       and.le.f r0,r1,512
-       and.ge.f r0,512,r2
+       and.eq.f r1,r1,r2
+       and.ne.f r0,r0,0
+       and.lt.f r2,r2,r2
+       and.gt.f 0,1,2
+       and.le.f 0,512,512
+       and.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/arc.exp b/gas/testsuite/gas/arc/arc.exp
index 44d82d4..7951744 100644 (file)
--- a/gas/testsuite/gas/arc/arc.exp
+++ b/gas/testsuite/gas/arc/arc.exp
@@ -4,59 +4,19 @@
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
-# 
+#
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
-# ARC base instruction set (to arc8)
-if [istarget arc*-*-*] then {
-    run_dump_test ld
-    run_dump_test ld2
-    run_dump_test st
-
-    # Specially encoded/single operand instructions
-    run_dump_test flag
-    run_dump_test brk
-    run_dump_test sleep
-    run_dump_test swi
-    run_dump_test asr
-    run_dump_test lsr
-    run_dump_test ror
-    run_dump_test rrc
-    run_dump_test sexb
-    run_dump_test sexw
-    run_dump_test extb
-    run_dump_test extw
-
-    run_dump_test b
-    run_dump_test bl
-    run_dump_test lp
-    run_dump_test j
-    run_dump_test jl
-    run_dump_test add
-    run_dump_test asl
-    # FIXME: ??? `lsl' gets dumped as `asl'
-    # run_dump_test lsl
-    run_dump_test adc
-    run_dump_test rlc
-    run_dump_test sub
-    run_dump_test sbc
-    run_dump_test and
-    run_dump_test mov
-    run_dump_test or
-    run_dump_test bic
-    run_dump_test xor
-    run_dump_test nop
-    run_dump_test extensions
-}
+# ARC base instruction set
 
 # ARC library extensions
 if [istarget arc*-*-*] then {
-    # *TODO*
+     run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
 }

diff --git a/gas/testsuite/gas/arc/asl.d b/gas/testsuite/gas/arc/asl.d
index 89aea0e..f27a671 100644 (file)
--- a/gas/testsuite/gas/arc/asl.d
+++ b/gas/testsuite/gas/arc/asl.d
@@ -1,68 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 82 00 40     40008200     asl        r0,r1
-   4:  00 38 6e 43     436e3800     asl        fp,sp
-   8:  00 fe 1f 40     401ffe00     asl        r0,0
-   c:  ff ff 3f 40     403fffff     asl        r1,-1
-  10:  00 04 e1 47     47e10400     asl        0,r2
-  14:  00 86 e1 47     47e18600     asl        0,r3
-  18:  ff fe 9f 40     409ffeff     asl        r4,255
-  1c:  00 8a e2 47     47e28a00     asl        0,r5
-  20:  00 ff df 40     40dfff00     asl        r6,-256
-  24:  00 8e e3 47     47e38e00     asl        0,r7
-  28:  00 7c 1f 41     411f7c00     asl        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 7c 3f 41     413f7c00     asl        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 7c 7f 41     417f7c00     asl        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 7c ff 47     47ff7c00     asl        0,0x100
-  44:  00 01 00 00 
-  48:  00 7c 1f 40     401f7c00     asl        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  00 82 00 40     40008200     asl        r0,r1
-  54:  00 08 62 40     40620800     asl        r3,r4
-  58:  01 8e c3 40     40c38e01     asl.z      r6,r7
-  5c:  01 14 25 41     41251401     asl.z      r9,r10
-  60:  02 9a 86 41     41869a02     asl.nz     r12,r13
-  64:  02 20 e8 41     41e82002     asl.nz     r15,r16
-  68:  03 a6 49 42     4249a603     asl.p      r18,r19
-  6c:  03 2c ab 42     42ab2c03     asl.p      r21,r22
-  70:  04 b2 0c 43     430cb204     asl.n      r24,r25
-  74:  04 38 6e 43     436e3804     asl.n      fp,sp
-  78:  05 be cf 43     43cfbe05     asl.c      ilink2,blink
-  7c:  05 44 31 44     44314405     asl.c      r33,r34
-  80:  05 ca 92 44     4492ca05     asl.c      r36,r37
-  84:  06 50 f4 44     44f45006     asl.nc     r39,r40
-  88:  06 d6 55 45     4555d606     asl.nc     r42,r43
-  8c:  06 5c b7 45     45b75c06     asl.nc     r45,r46
-  90:  07 e2 18 46     4618e207     asl.v      r48,r49
-  94:  07 64 39 46     46396407     asl.v      r49,r50
-  98:  08 ee 3b 46     463bee08     asl.nv     r49,r55
-  9c:  08 74 3d 46     463d7408     asl.nv     r49,r58
-  a0:  09 78 9e 47     479e7809     asl.gt     lp_count,lp_count
-  a4:  0a 7c 1f 40     401f7c0a     asl.ge     r0,0
-  a8:  00 00 00 00 
-  ac:  0c 7c df 47     47df7c0c     asl.le     0,2
-  b0:  02 00 00 00 
-  b4:  0d 86 61 40     4061860d     asl.hi     r3,r3
-  b8:  0e 08 82 40     4082080e     asl.ls     r4,r4
-  bc:  0f 8a a2 40     40a28a0f     asl.pnz    r5,r5
-  c0:  00 83 00 40     40008300     asl.f      r0,r1
-  c4:  01 fa 5e 40     405efa01     asl.f      r2,1
-  c8:  00 87 e1 47     47e18700     asl.f      0,r3
-  cc:  00 09 e2 47     47e20900     asl.f      0,r4
-  d0:  00 7d bf 40     40bf7d00     asl.f      r5,0x200
-  d4:  00 02 00 00 
-  d8:  00 7d df 47     47df7d00     asl.f      0,0x200
-  dc:  00 02 00 00 
-  e0:  01 83 00 40     40008301     asl.z.f    r0,r1
-  e4:  02 7d 3f 40     403f7d02     asl.nz.f   r1,0
-  e8:  00 00 00 00 
+0x[0-9a-f]+ 2900 0080                  asl     r0,r1,r2
+0x[0-9a-f]+ 2b00 371a                  asl     gp,fp,sp
+0x[0-9a-f]+ 2e00 37dd                  asl     ilink,r30,blink
+0x[0-9a-f]+ 2940 0000                  asl     r0,r1,0
+0x[0-9a-f]+ 2e00 7080 0000 0000        asl     r0,0,r2
+0x[0-9a-f]+ 2900 00be                  asl     0,r1,r2
+0x[0-9a-f]+ 2900 0f80 ffff ffff        asl     r0,r1,0xffffffff
+0x[0-9a-f]+ 2e00 7080 ffff ffff        asl     r0,0xffffffff,r2
+0x[0-9a-f]+ 2900 0f80 0000 00ff        asl     r0,r1,0xff
+0x[0-9a-f]+ 2e00 7080 0000 00ff        asl     r0,0xff,r2
+0x[0-9a-f]+ 2900 0f80 ffff ff00        asl     r0,r1,0xffffff00
+0x[0-9a-f]+ 2e00 7080 ffff ff00        asl     r0,0xffffff00,r2
+0x[0-9a-f]+ 2900 0f80 0000 0100        asl     r0,r1,0x100
+0x[0-9a-f]+ 2e00 7080 ffff feff        asl     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2e00 7f80 0000 0100        asl     r0,0x100,0x100
+0x[0-9a-f]+ 2900 0f80 0000 0000        asl     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 28c0 0080                  asl     r0,r0,r2
+0x[0-9a-f]+ 2bc0 0140                  asl     r3,r3,r5
+0x[0-9a-f]+ 2ec0 0201                  asl.eq  r6,r6,r8
+0x[0-9a-f]+ 29c0 12c1                  asl.eq  r9,r9,r11
+0x[0-9a-f]+ 2cc0 1382                  asl.ne  r12,r12,r14
+0x[0-9a-f]+ 2fc0 1442                  asl.ne  r15,r15,r17
+0x[0-9a-f]+ 2ac0 2503                  asl.p   r18,r18,r20
+0x[0-9a-f]+ 2dc0 25c3                  asl.p   r21,r21,r23
+0x[0-9a-f]+ 28c0 3684                  asl.n   r24,r24,gp
+0x[0-9a-f]+ 2bc0 3744                  asl.n   fp,fp,ilink
+0x[0-9a-f]+ 2ec0 37c5                  asl.c   r30,r30,blink
+0x[0-9a-f]+ 2bc0 00c5                  asl.c   r3,r3,r3
+0x[0-9a-f]+ 2bc0 0205                  asl.c   r3,r3,r8
+0x[0-9a-f]+ 2bc0 0106                  asl.nc  r3,r3,r4
+0x[0-9a-f]+ 2cc0 0106                  asl.nc  r4,r4,r4
+0x[0-9a-f]+ 2cc0 01c6                  asl.nc  r4,r4,r7
+0x[0-9a-f]+ 2cc0 0147                  asl.v   r4,r4,r5
+0x[0-9a-f]+ 2dc0 0147                  asl.v   r5,r5,r5
+0x[0-9a-f]+ 2dc0 0148                  asl.nv  r5,r5,r5
+0x[0-9a-f]+ 2dc0 0148                  asl.nv  r5,r5,r5
+0x[0-9a-f]+ 2ec0 0009                  asl.gt  r6,r6,r0
+0x[0-9a-f]+ 28c0 002a                  asl.ge  r0,r0,0
+0x[0-9a-f]+ 29c0 006b                  asl.lt  r1,r1,0x1
+0x[0-9a-f]+ 2bc0 00ed                  asl.hi  r3,r3,0x3
+0x[0-9a-f]+ 2cc0 012e                  asl.ls  r4,r4,0x4
+0x[0-9a-f]+ 2dc0 016f                  asl.pnz r5,r5,0x5
+0x[0-9a-f]+ 2900 8080                  asl.f   r0,r1,r2
+0x[0-9a-f]+ 2940 8040                  asl.f   r0,r1,0x1
+0x[0-9a-f]+ 2e00 f080 0000 0001        asl.f   r0,0x1,r2
+0x[0-9a-f]+ 2900 80be                  asl.f   0,r1,r2
+0x[0-9a-f]+ 2900 8f80 0000 0200        asl.f   r0,r1,0x200
+0x[0-9a-f]+ 2e00 f080 0000 0200        asl.f   r0,0x200,r2
+0x[0-9a-f]+ 29c0 8081                  asl.f.eq        r1,r1,r2
+0x[0-9a-f]+ 28c0 8022                  asl.f.ne        r0,r0,0
+0x[0-9a-f]+ 2ac0 808b                  asl.f.lt        r2,r2,r2
+0x[0-9a-f]+ 2ec0 f0a9 0000 0001        asl.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 2ec0 ff8c 0000 0200        asl.f.le        0,0x200,0x200
+0x[0-9a-f]+ 2ec0 f0aa 0000 0200        asl.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/asl.s b/gas/testsuite/gas/arc/asl.s
index f931458..39c7e12 100644 (file)
--- a/gas/testsuite/gas/arc/asl.s
+++ b/gas/testsuite/gas/arc/asl.s
@@ -1,58 +1,63 @@
 # asl test
 
-       asl r0,r1
-       asl fp,sp
-
-       asl r0,0
-       asl r1,-1
-       asl 0,r2
-       asl -1,r3
-       asl r4,255
-       asl 255,r5
-       asl r6,-256
-       asl -256,r7
-
-       asl r8,256
-       asl r9,-257
-       asl r11,0x42424242
-
-       asl 255,256
-
-       asl r0,foo
-
-       asl.al r0,r1
-       asl.ra r3,r4
-       asl.eq r6,r7
-       asl.z r9,r10
-       asl.ne r12,r13
-       asl.nz r15,r16
-       asl.pl r18,r19
-       asl.p r21,r22
-       asl.mi r24,r25
-       asl.n r27,r28
-       asl.cs r30,r31
-       asl.c r33,r34
-       asl.lo r36,r37
-       asl.cc r39,r40
-       asl.nc r42,r43
-       asl.hs r45,r46
-       asl.vs r48,r49
-       asl.v r49,r50
-       asl.vc r49,r55
-       asl.nv r49,r58
-       asl.gt r60,r60
-       asl.ge r0,0
-       asl.le 2,2
-       asl.hi r3,r3
-       asl.ls r4,r4
-       asl.pnz r5,r5
-
-       asl.f r0,r1
-       asl.f r2,1
-       asl.f 1,r3
-       asl.f 0,r4
-       asl.f r5,512
-       asl.f 512,512
-
-       asl.eq.f r0,r1
-       asl.ne.f r1,0
+       asl r0,r1,r2
+       asl r26,fp,sp
+       asl ilink1,ilink2,blink
+
+       asl r0,r1,0
+       asl r0,0,r2
+       asl 0,r1,r2
+       asl r0,r1,-1
+       asl r0,-1,r2
+       asl r0,r1,255
+       asl r0,255,r2
+       asl r0,r1,-256
+       asl r0,-256,r2
+
+       asl r0,r1,256
+       asl r0,-257,r2
+
+       asl r0,256,256
+
+       asl r0,r1,foo
+
+       asl.al r0,r0,r2
+       asl.ra r3,r3,r5
+       asl.eq r6,r6,r8
+       asl.z  r9,r9,r11
+       asl.ne r12,r12,r14
+       asl.nz r15,r15,r17
+       asl.pl r18,r18,r20
+       asl.p  r21,r21,r23
+       asl.mi r24,r24,r26
+       asl.n  r27,r27,r29
+       asl.cs r30,r30,r31
+       asl.c  r3,r3,r3
+       asl.lo r3,r3,r8
+       asl.cc r3,r3,r4
+       asl.nc r4,r4,r4
+       asl.hs r4,r4,r7
+       asl.vs r4,r4,r5
+       asl.v  r5,r5,r5
+       asl.vc r5,r5,r5
+       asl.nv r5,r5,r5
+       asl.gt r6,r6,r0
+       asl.ge r0,r0,0
+       asl.lt r1,r1,1
+       asl.hi r3,r3,3
+       asl.ls r4,r4,4
+       asl.pnz r5,r5,5
+
+       asl.f r0,r1,r2
+       asl.f r0,r1,1
+       asl.f r0,1,r2
+       asl.f 0,r1,r2
+       asl.f r0,r1,512
+       asl.f r0,512,r2
+
+       asl.eq.f r1,r1,r2
+       asl.ne.f r0,r0,0
+       asl.lt.f r2,r2,r2
+       asl.gt.f 0,1,2
+       asl.le.f 0,512,512
+       asl.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/asr.d b/gas/testsuite/gas/arc/asr.d
index bb4c96e..c94736e 100644 (file)
--- a/gas/testsuite/gas/arc/asr.d
+++ b/gas/testsuite/gas/arc/asr.d
@@ -1,51 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 82 00 18     18008200     asr        r0,r1
-   4:  00 02 6e 1b     1b6e0200     asr        fp,sp
-   8:  00 82 1f 18     181f8200     asr        r0,0
-   c:  ff 83 3f 18     183f83ff     asr        r1,-1
-  10:  00 02 e1 1f     1fe10200     asr        0,r2
-  14:  00 82 e1 1f     1fe18200     asr        0,r3
-  18:  ff 82 9f 18     189f82ff     asr        r4,255
-  1c:  00 82 e2 1f     1fe28200     asr        0,r5
-  20:  00 83 df 18     18df8300     asr        r6,-256
-  24:  00 82 e3 1f     1fe38200     asr        0,r7
-  28:  00 02 1f 19     191f0200     asr        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 02 3f 19     193f0200     asr        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 02 7f 19     197f0200     asr        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 02 ff 1f     1fff0200     asr        0,0x100
-  44:  00 01 00 00 
-  48:  00 02 1f 18     181f0200     asr        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 82 45 19     19458201     asr.z      r10,r11
-  54:  02 82 86 19     19868202     asr.nz     r12,r13
-  58:  0b 02 df 19     19df020b     asr.lt     r14,0
-  5c:  00 00 00 00 
-  60:  09 02 ff 19     19ff0209     asr.gt     r15,0x200
-  64:  00 02 00 00 
-  68:  00 83 00 18     18008300     asr.f      r0,r1
-  6c:  01 82 5e 18     185e8201     asr.f      r2,1
-  70:  00 03 e2 1f     1fe20300     asr.f      0,r4
-  74:  00 03 bf 18     18bf0300     asr.f      r5,0x200
-  78:  00 02 00 00 
-  7c:  00 03 df 1f     1fdf0300     asr.f      0,0x200
-  80:  00 02 00 00 
-  84:  01 83 00 18     18008301     asr.z.f    r0,r1
-  88:  02 03 3f 18     183f0302     asr.nz.f   r1,0
-  8c:  00 00 00 00 
-  90:  0b 03 c1 1f     1fc1030b     asr.lt.f   0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 03 1f 18     181f030c     asr.le.f   r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 03 df 1f     1fdf0304     asr.n.f    0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 2902 0080                  asr     r0,r1,r2
+0x[0-9a-f]+ 2b02 371a                  asr     gp,fp,sp
+0x[0-9a-f]+ 2e02 37dd                  asr     ilink,r30,blink
+0x[0-9a-f]+ 2942 0000                  asr     r0,r1,0
+0x[0-9a-f]+ 2e02 7080 0000 0000        asr     r0,0,r2
+0x[0-9a-f]+ 2902 00be                  asr     0,r1,r2
+0x[0-9a-f]+ 2902 0f80 ffff ffff        asr     r0,r1,0xffffffff
+0x[0-9a-f]+ 2e02 7080 ffff ffff        asr     r0,0xffffffff,r2
+0x[0-9a-f]+ 2902 0f80 0000 00ff        asr     r0,r1,0xff
+0x[0-9a-f]+ 2e02 7080 0000 00ff        asr     r0,0xff,r2
+0x[0-9a-f]+ 2902 0f80 ffff ff00        asr     r0,r1,0xffffff00
+0x[0-9a-f]+ 2e02 7080 ffff ff00        asr     r0,0xffffff00,r2
+0x[0-9a-f]+ 2902 0f80 0000 0100        asr     r0,r1,0x100
+0x[0-9a-f]+ 2e02 7080 ffff feff        asr     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2e02 7f80 0000 0100        asr     r0,0x100,0x100
+0x[0-9a-f]+ 2902 0f80 0000 0000        asr     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 28c2 0080                  asr     r0,r0,r2
+0x[0-9a-f]+ 2bc2 0140                  asr     r3,r3,r5
+0x[0-9a-f]+ 2ec2 0201                  asr.eq  r6,r6,r8
+0x[0-9a-f]+ 29c2 12c1                  asr.eq  r9,r9,r11
+0x[0-9a-f]+ 2cc2 1382                  asr.ne  r12,r12,r14
+0x[0-9a-f]+ 2fc2 1442                  asr.ne  r15,r15,r17
+0x[0-9a-f]+ 2ac2 2503                  asr.p   r18,r18,r20
+0x[0-9a-f]+ 2dc2 25c3                  asr.p   r21,r21,r23
+0x[0-9a-f]+ 28c2 3684                  asr.n   r24,r24,gp
+0x[0-9a-f]+ 2bc2 3744                  asr.n   fp,fp,ilink
+0x[0-9a-f]+ 2ec2 37c5                  asr.c   r30,r30,blink
+0x[0-9a-f]+ 2bc2 00c5                  asr.c   r3,r3,r3
+0x[0-9a-f]+ 2bc2 0205                  asr.c   r3,r3,r8
+0x[0-9a-f]+ 2bc2 0106                  asr.nc  r3,r3,r4
+0x[0-9a-f]+ 2cc2 0106                  asr.nc  r4,r4,r4
+0x[0-9a-f]+ 2cc2 01c6                  asr.nc  r4,r4,r7
+0x[0-9a-f]+ 2cc2 0147                  asr.v   r4,r4,r5
+0x[0-9a-f]+ 2dc2 0147                  asr.v   r5,r5,r5
+0x[0-9a-f]+ 2dc2 0148                  asr.nv  r5,r5,r5
+0x[0-9a-f]+ 2dc2 0148                  asr.nv  r5,r5,r5
+0x[0-9a-f]+ 2ec2 0009                  asr.gt  r6,r6,r0
+0x[0-9a-f]+ 28c2 002a                  asr.ge  r0,r0,0
+0x[0-9a-f]+ 29c2 006b                  asr.lt  r1,r1,0x1
+0x[0-9a-f]+ 2bc2 00ed                  asr.hi  r3,r3,0x3
+0x[0-9a-f]+ 2cc2 012e                  asr.ls  r4,r4,0x4
+0x[0-9a-f]+ 2dc2 016f                  asr.pnz r5,r5,0x5
+0x[0-9a-f]+ 2902 8080                  asr.f   r0,r1,r2
+0x[0-9a-f]+ 2942 8040                  asr.f   r0,r1,0x1
+0x[0-9a-f]+ 2e02 f080 0000 0001        asr.f   r0,0x1,r2
+0x[0-9a-f]+ 2902 80be                  asr.f   0,r1,r2
+0x[0-9a-f]+ 2902 8f80 0000 0200        asr.f   r0,r1,0x200
+0x[0-9a-f]+ 2e02 f080 0000 0200        asr.f   r0,0x200,r2
+0x[0-9a-f]+ 29c2 8081                  asr.f.eq        r1,r1,r2
+0x[0-9a-f]+ 28c2 8022                  asr.f.ne        r0,r0,0
+0x[0-9a-f]+ 2ac2 808b                  asr.f.lt        r2,r2,r2
+0x[0-9a-f]+ 2ec2 f0a9 0000 0001        asr.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 2ec2 ff8c 0000 0200        asr.f.le        0,0x200,0x200
+0x[0-9a-f]+ 2ec2 f0aa 0000 0200        asr.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/asr.s b/gas/testsuite/gas/arc/asr.s
index 9998b34..999706f 100644 (file)
--- a/gas/testsuite/gas/arc/asr.s
+++ b/gas/testsuite/gas/arc/asr.s
@@ -1,38 +1,63 @@
 # asr test
 
-       asr r0,r1
-       asr fp,sp
-
-       asr r0,0
-       asr r1,-1
-       asr 0,r2
-       asr -1,r3
-       asr r4,255
-       asr 255,r5
-       asr r6,-256
-       asr -256,r7
-
-       asr r8,256
-       asr r9,-257
-       asr r11,0x42424242
-
-       asr 255,256
-
-       asr r0,foo
-
-       asr.eq r10,r11
-       asr.ne r12,r13
-       asr.lt r14,0
-       asr.gt r15,512
-
-       asr.f r0,r1
-       asr.f r2,1
-       asr.f 0,r4
-       asr.f r5,512
-       asr.f 512,512
-
-       asr.eq.f r0,r1
-       asr.ne.f r1,0
-       asr.lt.f 0,r2
-       asr.le.f r0,512
-       asr.n.f 512,512
+       asr r0,r1,r2
+       asr r26,fp,sp
+       asr ilink1,ilink2,blink
+
+       asr r0,r1,0
+       asr r0,0,r2
+       asr 0,r1,r2
+       asr r0,r1,-1
+       asr r0,-1,r2
+       asr r0,r1,255
+       asr r0,255,r2
+       asr r0,r1,-256
+       asr r0,-256,r2
+
+       asr r0,r1,256
+       asr r0,-257,r2
+
+       asr r0,256,256
+
+       asr r0,r1,foo
+
+       asr.al r0,r0,r2
+       asr.ra r3,r3,r5
+       asr.eq r6,r6,r8
+       asr.z  r9,r9,r11
+       asr.ne r12,r12,r14
+       asr.nz r15,r15,r17
+       asr.pl r18,r18,r20
+       asr.p  r21,r21,r23
+       asr.mi r24,r24,r26
+       asr.n  r27,r27,r29
+       asr.cs r30,r30,r31
+       asr.c  r3,r3,r3
+       asr.lo r3,r3,r8
+       asr.cc r3,r3,r4
+       asr.nc r4,r4,r4
+       asr.hs r4,r4,r7
+       asr.vs r4,r4,r5
+       asr.v  r5,r5,r5
+       asr.vc r5,r5,r5
+       asr.nv r5,r5,r5
+       asr.gt r6,r6,r0
+       asr.ge r0,r0,0
+       asr.lt r1,r1,1
+       asr.hi r3,r3,3
+       asr.ls r4,r4,4
+       asr.pnz r5,r5,5
+
+       asr.f r0,r1,r2
+       asr.f r0,r1,1
+       asr.f r0,1,r2
+       asr.f 0,r1,r2
+       asr.f r0,r1,512
+       asr.f r0,512,r2
+
+       asr.eq.f r1,r1,r2
+       asr.ne.f r0,r0,0
+       asr.lt.f r2,r2,r2
+       asr.gt.f 0,1,2
+       asr.le.f 0,512,512
+       asr.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/b.d b/gas/testsuite/gas/arc/b.d
index 8c2eb01..87afdc0 100644 (file)
--- a/gas/testsuite/gas/arc/b.d
+++ b/gas/testsuite/gas/arc/b.d
@@ -1,76 +1,46 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
 00000000 <text_label>:
-   0:  80 ff ff 27     27ffff80     b          0 <text_label>
-
-   4:  00 ff ff 27     27ffff00     b          0 <text_label>
-
-   8:  80 fe ff 27     27fffe80     b          0 <text_label>
-
-   c:  01 fe ff 27     27fffe01     bz         0 <text_label>
-
-  10:  81 fd ff 27     27fffd81     bz         0 <text_label>
-
-  14:  02 fd ff 27     27fffd02     bnz        0 <text_label>
-
-  18:  82 fc ff 27     27fffc82     bnz        0 <text_label>
-
-  1c:  03 fc ff 27     27fffc03     bp         0 <text_label>
-
-  20:  83 fb ff 27     27fffb83     bp         0 <text_label>
-
-  24:  04 fb ff 27     27fffb04     bn         0 <text_label>
-
-  28:  84 fa ff 27     27fffa84     bn         0 <text_label>
-
-  2c:  05 fa ff 27     27fffa05     bc         0 <text_label>
-
-  30:  85 f9 ff 27     27fff985     bc         0 <text_label>
-
-  34:  05 f9 ff 27     27fff905     bc         0 <text_label>
-
-  38:  86 f8 ff 27     27fff886     bnc        0 <text_label>
-
-  3c:  06 f8 ff 27     27fff806     bnc        0 <text_label>
-
-  40:  86 f7 ff 27     27fff786     bnc        0 <text_label>
-
-  44:  07 f7 ff 27     27fff707     bv         0 <text_label>
-
-  48:  87 f6 ff 27     27fff687     bv         0 <text_label>
-
-  4c:  08 f6 ff 27     27fff608     bnv        0 <text_label>
-
-  50:  88 f5 ff 27     27fff588     bnv        0 <text_label>
-
-  54:  09 f5 ff 27     27fff509     bgt        0 <text_label>
-
-  58:  8a f4 ff 27     27fff48a     bge        0 <text_label>
-
-  5c:  0b f4 ff 27     27fff40b     blt        0 <text_label>
-
-  60:  8c f3 ff 27     27fff38c     ble        0 <text_label>
-
-  64:  0d f3 ff 27     27fff30d     bhi        0 <text_label>
-
-  68:  8e f2 ff 27     27fff28e     bls        0 <text_label>
-
-  6c:  0f f2 ff 27     27fff20f     bpnz       0 <text_label>
-
-  70:  a0 f1 ff 27     27fff1a0     b.d        0 <text_label>
-
-  74:  00 f1 ff 27     27fff100     b          0 <text_label>
-
-  78:  c0 f0 ff 27     27fff0c0     b.jd       0 <text_label>
-
-  7c:  21 f0 ff 27     27fff021     bz.d       0 <text_label>
-
-  80:  82 ef ff 27     27ffef82     bnz        0 <text_label>
-
-  84:  46 ef ff 27     27ffef46     bnc.jd     0 <text_label>
-
+   0:  0001 0000               b       0 <text_label>
+   4:  07fc ffc0               b       -4
+   8:  07f8 ffc0               b       -8
+   c:  07f4 ffc1               beq     -12
+  10:  07f0 ffc1               beq     -16
+  14:  07ec ffc2               bne     -20
+  18:  07e8 ffc2               bne     -24
+  1c:  07e4 ffc3               bp      -28
+  20:  07e0 ffc3               bp      -32
+  24:  07dc ffc4               bn      -36
+  28:  07d8 ffc4               bn      -40
+  2c:  07d4 ffc5               bc      -44
+  30:  07d0 ffc5               bc      -48
+  34:  07cc ffc5               bc      -52
+  38:  07c8 ffc6               bnc     -56
+  3c:  07c4 ffc6               bnc     -60
+  40:  07c0 ffc6               bnc     -64
+  44:  07bc ffc7               bv      -68
+  48:  07b8 ffc7               bv      -72
+  4c:  07b4 ffc8               bnv     -76
+  50:  07b0 ffc8               bnv     -80
+  54:  07ac ffc9               bgt     -84
+  58:  07a8 ffca               bge     -88
+  5c:  07a4 ffcb               blt     -92
+  60:  07a0 ffcc               ble     -96
+  64:  079c ffcd               bhi     -100
+  68:  0798 ffce               bls     -104
+  6c:  0794 ffcf               bpnz    -108
+  70:  0791 ffef               b.d     0 <text_label>
+  74:  264a 7000               mov     0,0
+  78:  0789 ffcf               b       0 <text_label>
+  7c:  0785 ffef               b.d     0 <text_label>
+  80:  264a 7000               mov     0,0
+  84:  077c ffe1               b.deq   -132
+  88:  264a 7000               mov     0,0
+  8c:  0774 ffc2               bne     -140
+  90:  0770 ffe6               b.dnc   -144
+  94:  264a 7000               mov     0,0

diff --git a/gas/testsuite/gas/arc/b.s b/gas/testsuite/gas/arc/b.s
index a215fe4..0cb7783 100644 (file)
--- a/gas/testsuite/gas/arc/b.s
+++ b/gas/testsuite/gas/arc/b.s
@@ -1,5 +1,5 @@
 # b test
-       
+
 text_label:
 
        b       text_label
@@ -32,9 +32,13 @@ text_label:
        bpnz    text_label
 
        b.d     text_label
+       nop
        b.nd    text_label
-       b.jd    text_label
+       b.d     text_label
+       nop
 
        beq.d   text_label
+       nop
        bne.nd  text_label
-       bcc.jd  text_label
+       bcc.d   text_label
+       nop

diff --git a/gas/testsuite/gas/arc/bic.d b/gas/testsuite/gas/arc/bic.d
index 5b2a233..348a428 100644 (file)
--- a/gas/testsuite/gas/arc/bic.d
+++ b/gas/testsuite/gas/arc/bic.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 70     70008400     bic        r0,r1,r2
-   4:  00 b8 4d 73     734db800     bic        gp,fp,sp
-   8:  00 3e af 73     73af3e00     bic        ilink1,ilink2,blink
-   c:  00 f8 1d 77     771df800     bic        r56,r59,lp_count
-  10:  00 fe 00 70     7000fe00     bic        r0,r1,0
-  14:  00 84 1f 70     701f8400     bic        r0,0,r2
-  18:  00 84 e0 77     77e08400     bic        0,r1,r2
-  1c:  ff ff 00 70     7000ffff     bic        r0,r1,-1
-  20:  ff 85 1f 70     701f85ff     bic        r0,-1,r2
-  24:  00 84 e0 77     77e08400     bic        0,r1,r2
-  28:  ff fe 00 70     7000feff     bic        r0,r1,255
-  2c:  ff 84 1f 70     701f84ff     bic        r0,255,r2
-  30:  00 84 e0 77     77e08400     bic        0,r1,r2
-  34:  00 ff 00 70     7000ff00     bic        r0,r1,-256
-  38:  00 85 1f 70     701f8500     bic        r0,-256,r2
-  3c:  00 84 e0 77     77e08400     bic        0,r1,r2
-  40:  00 fc 00 70     7000fc00     bic        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 70     701f0400     bic        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 70     701ffcff     bic        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 70     701f7eff     bic        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 70     7000fc00     bic        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 70     70008400     bic        r0,r1,r2
-  6c:  00 0a 62 70     70620a00     bic        r3,r4,r5
-  70:  01 90 c3 70     70c39001     bic.z      r6,r7,r8
-  74:  01 16 25 71     71251601     bic.z      r9,r10,r11
-  78:  02 9c 86 71     71869c02     bic.nz     r12,r13,r14
-  7c:  02 22 e8 71     71e82202     bic.nz     r15,r16,r17
-  80:  03 a8 49 72     7249a803     bic.p      r18,r19,r20
-  84:  03 2e ab 72     72ab2e03     bic.p      r21,r22,r23
-  88:  04 b4 0c 73     730cb404     bic.n      r24,r25,gp
-  8c:  04 3a 6e 73     736e3a04     bic.n      fp,sp,ilink1
-  90:  05 c0 cf 73     73cfc005     bic.c      ilink2,blink,r32
-  94:  05 46 31 74     74314605     bic.c      r33,r34,r35
-  98:  05 cc 92 74     7492cc05     bic.c      r36,r37,r38
-  9c:  06 52 f4 74     74f45206     bic.nc     r39,r40,r41
-  a0:  06 d8 55 75     7555d806     bic.nc     r42,r43,r44
-  a4:  06 5e b7 75     75b75e06     bic.nc     r45,r46,r47
-  a8:  07 e4 18 76     7618e407     bic.v      r48,r49,r50
-  ac:  07 6a 1a 77     771a6a07     bic.v      r56,r52,r53
-  b0:  08 f0 1b 77     771bf008     bic.nv     r56,r55,r56
-  b4:  08 76 1d 77     771d7608     bic.nv     r56,r58,r59
-  b8:  09 00 9e 77     779e0009     bic.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 70     70007c0a     bic.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 70     703f020b     bic.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 70     707f060d     bic.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 77     77df080e     bic.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 77     77c2fc0f     bic.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 70     70008500     bic.f      r0,r1,r2
-  e8:  01 fa 00 70     7000fa01     bic.f      r0,r1,1
-  ec:  01 84 1e 70     701e8401     bic.f      r0,1,r2
-  f0:  00 85 e0 77     77e08500     bic.f      0,r1,r2
-  f4:  00 fd 00 70     7000fd00     bic.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 70     701f0500     bic.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 70     70008501     bic.z.f    r0,r1,r2
- 108:  02 fd 00 70     7000fd02     bic.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 70     701f050b     bic.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 77     77c08509     bic.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 70     7000fd0c     bic.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 70     701f050a     bic.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2106 0080                  bic     r0,r1,r2
+0x[0-9a-f]+ 2306 371a                  bic     gp,fp,sp
+0x[0-9a-f]+ 2606 37dd                  bic     ilink,r30,blink
+0x[0-9a-f]+ 2146 0000                  bic     r0,r1,0
+0x[0-9a-f]+ 2606 7080 0000 0000        bic     r0,0,r2
+0x[0-9a-f]+ 2106 00be                  bic     0,r1,r2
+0x[0-9a-f]+ 2106 0f80 ffff ffff        bic     r0,r1,0xffffffff
+0x[0-9a-f]+ 2606 7080 ffff ffff        bic     r0,0xffffffff,r2
+0x[0-9a-f]+ 2106 0f80 0000 00ff        bic     r0,r1,0xff
+0x[0-9a-f]+ 2606 7080 0000 00ff        bic     r0,0xff,r2
+0x[0-9a-f]+ 2106 0f80 ffff ff00        bic     r0,r1,0xffffff00
+0x[0-9a-f]+ 2606 7080 ffff ff00        bic     r0,0xffffff00,r2
+0x[0-9a-f]+ 2106 0f80 0000 0100        bic     r0,r1,0x100
+0x[0-9a-f]+ 2606 7080 ffff feff        bic     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2606 7f80 0000 0100        bic     r0,0x100,0x100
+0x[0-9a-f]+ 2106 0f80 0000 0000        bic     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c6 0080                  bic     r0,r0,r2
+0x[0-9a-f]+ 23c6 0140                  bic     r3,r3,r5
+0x[0-9a-f]+ 26c6 0201                  biceq   r6,r6,r8
+0x[0-9a-f]+ 21c6 12c1                  biceq   r9,r9,r11
+0x[0-9a-f]+ 24c6 1382                  bicne   r12,r12,r14
+0x[0-9a-f]+ 27c6 1442                  bicne   r15,r15,r17
+0x[0-9a-f]+ 22c6 2503                  bicp    r18,r18,r20
+0x[0-9a-f]+ 25c6 25c3                  bicp    r21,r21,r23
+0x[0-9a-f]+ 20c6 3684                  bicn    r24,r24,gp
+0x[0-9a-f]+ 23c6 3744                  bicn    fp,fp,ilink
+0x[0-9a-f]+ 26c6 37c5                  bicc    r30,r30,blink
+0x[0-9a-f]+ 23c6 00c5                  bicc    r3,r3,r3
+0x[0-9a-f]+ 23c6 0205                  bicc    r3,r3,r8
+0x[0-9a-f]+ 23c6 0106                  bicnc   r3,r3,r4
+0x[0-9a-f]+ 24c6 0106                  bicnc   r4,r4,r4
+0x[0-9a-f]+ 24c6 01c6                  bicnc   r4,r4,r7
+0x[0-9a-f]+ 24c6 0147                  bicv    r4,r4,r5
+0x[0-9a-f]+ 25c6 0147                  bicv    r5,r5,r5
+0x[0-9a-f]+ 25c6 0148                  bicnv   r5,r5,r5
+0x[0-9a-f]+ 25c6 0148                  bicnv   r5,r5,r5
+0x[0-9a-f]+ 26c6 0009                  bicgt   r6,r6,r0
+0x[0-9a-f]+ 20c6 002a                  bicge   r0,r0,0
+0x[0-9a-f]+ 21c6 006b                  biclt   r1,r1,0x1
+0x[0-9a-f]+ 23c6 00ed                  bichi   r3,r3,0x3
+0x[0-9a-f]+ 24c6 012e                  bicls   r4,r4,0x4
+0x[0-9a-f]+ 25c6 016f                  bicpnz  r5,r5,0x5
+0x[0-9a-f]+ 2106 8080                  bic.f   r0,r1,r2
+0x[0-9a-f]+ 2146 8040                  bic.f   r0,r1,0x1
+0x[0-9a-f]+ 2606 f080 0000 0001        bic.f   r0,0x1,r2
+0x[0-9a-f]+ 2106 80be                  bic.f   0,r1,r2
+0x[0-9a-f]+ 2106 8f80 0000 0200        bic.f   r0,r1,0x200
+0x[0-9a-f]+ 2606 f080 0000 0200        bic.f   r0,0x200,r2
+0x[0-9a-f]+ 21c6 8081                  bic.feq r1,r1,r2
+0x[0-9a-f]+ 20c6 8022                  bic.fne r0,r0,0
+0x[0-9a-f]+ 22c6 808b                  bic.flt r2,r2,r2
+0x[0-9a-f]+ 26c6 f0a9 0000 0001        bic.fgt 0,0x1,0x2
+0x[0-9a-f]+ 26c6 ff8c 0000 0200        bic.fle 0,0x200,0x200
+0x[0-9a-f]+ 26c6 f0aa 0000 0200        bic.fge 0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/bic.s b/gas/testsuite/gas/arc/bic.s
index fc5eb19..0e10e20 100644 (file)
--- a/gas/testsuite/gas/arc/bic.s
+++ b/gas/testsuite/gas/arc/bic.s
@@ -3,55 +3,50 @@
        bic r0,r1,r2
        bic r26,fp,sp
        bic ilink1,ilink2,blink
-       bic r56,r59,lp_count
 
        bic r0,r1,0
        bic r0,0,r2
        bic 0,r1,r2
        bic r0,r1,-1
        bic r0,-1,r2
-       bic -1,r1,r2
        bic r0,r1,255
        bic r0,255,r2
-       bic 255,r1,r2
        bic r0,r1,-256
        bic r0,-256,r2
-       bic -256,r1,r2
 
        bic r0,r1,256
        bic r0,-257,r2
 
-       bic r0,255,256
-       bic r0,256,255
+       bic r0,256,256
 
        bic r0,r1,foo
 
-       bic.al r0,r1,r2
-       bic.ra r3,r4,r5
-       bic.eq r6,r7,r8
-       bic.z r9,r10,r11
-       bic.ne r12,r13,r14
-       bic.nz r15,r16,r17
-       bic.pl r18,r19,r20
-       bic.p r21,r22,r23
-       bic.mi r24,r25,r26
-       bic.n r27,r28,r29
-       bic.cs r30,r31,r32
-       bic.c r33,r34,r35
-       bic.lo r36,r37,r38
-       bic.cc r39,r40,r41
-       bic.nc r42,r43,r44
-       bic.hs r45,r46,r47
-       bic.vs r48,r49,r50
-       bic.v r56,r52,r53
-       bic.vc r56,r55,r56
-       bic.nv r56,r58,r59
-       bic.gt r60,r60,r0
+       bic.al r0,r0,r2
+       bic.ra r3,r3,r5
+       bic.eq r6,r6,r8
+       bic.z  r9,r9,r11
+       bic.ne r12,r12,r14
+       bic.nz r15,r15,r17
+       bic.pl r18,r18,r20
+       bic.p  r21,r21,r23
+       bic.mi r24,r24,r26
+       bic.n  r27,r27,r29
+       bic.cs r30,r30,r31
+       bic.c  r3,r3,r3
+       bic.lo r3,r3,r8
+       bic.cc r3,r3,r4
+       bic.nc r4,r4,r4
+       bic.hs r4,r4,r7
+       bic.vs r4,r4,r5
+       bic.v  r5,r5,r5
+       bic.vc r5,r5,r5
+       bic.nv r5,r5,r5
+       bic.gt r6,r6,r0
        bic.ge r0,r0,0
-       bic.lt r1,1,r1
-       bic.hi r3,3,r3
-       bic.ls 4,4,r4
-       bic.pnz 5,r5,5
+       bic.lt r1,r1,1
+       bic.hi r3,r3,3
+       bic.ls r4,r4,4
+       bic.pnz r5,r5,5
 
        bic.f r0,r1,r2
        bic.f r0,r1,1
@@ -60,9 +55,9 @@
        bic.f r0,r1,512
        bic.f r0,512,r2
 
-       bic.eq.f r0,r1,r2
-       bic.ne.f r0,r1,0
-       bic.lt.f r0,0,r2
-       bic.gt.f 0,r1,r2
-       bic.le.f r0,r1,512
-       bic.ge.f r0,512,r2
+       bic.eq.f r1,r1,r2
+       bic.ne.f r0,r0,0
+       bic.lt.f r2,r2,r2
+       bic.gt.f 0,1,2
+       bic.le.f 0,512,512
+       bic.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/bl.d b/gas/testsuite/gas/arc/bl.d
index 0cc19db..3967275 100644 (file)
--- a/gas/testsuite/gas/arc/bl.d
+++ b/gas/testsuite/gas/arc/bl.d
@@ -1,76 +1,46 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <text_label>:
-   0:  80 ff ff 2f     2fffff80     bl         0 <text_label>
-
-   4:  00 ff ff 2f     2fffff00     bl         0 <text_label>
-
-   8:  80 fe ff 2f     2ffffe80     bl         0 <text_label>
-
-   c:  01 fe ff 2f     2ffffe01     blz        0 <text_label>
-
-  10:  81 fd ff 2f     2ffffd81     blz        0 <text_label>
-
-  14:  02 fd ff 2f     2ffffd02     blnz       0 <text_label>
-
-  18:  82 fc ff 2f     2ffffc82     blnz       0 <text_label>
-
-  1c:  03 fc ff 2f     2ffffc03     blp        0 <text_label>
-
-  20:  83 fb ff 2f     2ffffb83     blp        0 <text_label>
-
-  24:  04 fb ff 2f     2ffffb04     bln        0 <text_label>
-
-  28:  84 fa ff 2f     2ffffa84     bln        0 <text_label>
-
-  2c:  05 fa ff 2f     2ffffa05     blc        0 <text_label>
-
-  30:  85 f9 ff 2f     2ffff985     blc        0 <text_label>
-
-  34:  05 f9 ff 2f     2ffff905     blc        0 <text_label>
-
-  38:  86 f8 ff 2f     2ffff886     blnc       0 <text_label>
-
-  3c:  06 f8 ff 2f     2ffff806     blnc       0 <text_label>
-
-  40:  86 f7 ff 2f     2ffff786     blnc       0 <text_label>
-
-  44:  07 f7 ff 2f     2ffff707     blv        0 <text_label>
-
-  48:  87 f6 ff 2f     2ffff687     blv        0 <text_label>
-
-  4c:  08 f6 ff 2f     2ffff608     blnv       0 <text_label>
-
-  50:  88 f5 ff 2f     2ffff588     blnv       0 <text_label>
-
-  54:  09 f5 ff 2f     2ffff509     blgt       0 <text_label>
-
-  58:  8a f4 ff 2f     2ffff48a     blge       0 <text_label>
-
-  5c:  0b f4 ff 2f     2ffff40b     bllt       0 <text_label>
-
-  60:  8c f3 ff 2f     2ffff38c     blle       0 <text_label>
-
-  64:  0d f3 ff 2f     2ffff30d     blhi       0 <text_label>
-
-  68:  8e f2 ff 2f     2ffff28e     blls       0 <text_label>
-
-  6c:  0f f2 ff 2f     2ffff20f     blpnz      0 <text_label>
-
-  70:  a0 f1 ff 2f     2ffff1a0     bl.d       0 <text_label>
-
-  74:  00 f1 ff 2f     2ffff100     bl         0 <text_label>
-
-  78:  c0 f0 ff 2f     2ffff0c0     bl.jd      0 <text_label>
-
-  7c:  21 f0 ff 2f     2ffff021     blz.d      0 <text_label>
-
-  80:  82 ef ff 2f     2fffef82     blnz       0 <text_label>
-
-  84:  46 ef ff 2f     2fffef46     blnc.jd    0 <text_label>
-
+[0-9a-f]+ <text_label>:
+   0:  0802 0000               bl      0 <text_label>
+   4:  0ffc ffc0               bl      0 <text_label>
+   8:  0ff8 ffc0               bl      0 <text_label>
+   c:  0ff4 ffc1               bleq    0 <text_label>
+  10:  0ff0 ffc1               bleq    0 <text_label>
+  14:  0fec ffc2               blne    0 <text_label>
+  18:  0fe8 ffc2               blne    0 <text_label>
+  1c:  0fe4 ffc3               blp     0 <text_label>
+  20:  0fe0 ffc3               blp     0 <text_label>
+  24:  0fdc ffc4               bln     0 <text_label>
+  28:  0fd8 ffc4               bln     0 <text_label>
+  2c:  0fd4 ffc5               blc     0 <text_label>
+  30:  0fd0 ffc5               blc     0 <text_label>
+  34:  0fcc ffc5               blc     0 <text_label>
+  38:  0fc8 ffc6               blnc    0 <text_label>
+  3c:  0fc4 ffc6               blnc    0 <text_label>
+  40:  0fc0 ffc6               blnc    0 <text_label>
+  44:  0fbc ffc7               blv     0 <text_label>
+  48:  0fb8 ffc7               blv     0 <text_label>
+  4c:  0fb4 ffc8               blnv    0 <text_label>
+  50:  0fb0 ffc8               blnv    0 <text_label>
+  54:  0fac ffc9               blgt    0 <text_label>
+  58:  0fa8 ffca               blge    0 <text_label>
+  5c:  0fa4 ffcb               bllt    0 <text_label>
+  60:  0fa0 ffcc               blle    0 <text_label>
+  64:  0f9c ffcd               blhi    0 <text_label>
+  68:  0f98 ffce               blls    0 <text_label>
+  6c:  0f94 ffcf               blpnz   0 <text_label>
+  70:  0f92 ffef               bl.d    0 <text_label>
+  74:  78e0                    nop_s
+  76:  0f8e ffcf               bl      0 <text_label>
+  7a:  78e0                    nop_s
+  7c:  0f84 ffe1               bleq.d  0 <text_label>
+  80:  78e0                    nop_s
+  82:  0f80 ffc2               blne    0 <text_label>
+  86:  78e0                    nop_s
+  88:  0f78 ffe6               blnc.d  0 <text_label>
+  8c:  78e0                    nop_s

diff --git a/gas/testsuite/gas/arc/bl.s b/gas/testsuite/gas/arc/bl.s
index 8181f39..b23d652 100644 (file)
--- a/gas/testsuite/gas/arc/bl.s
+++ b/gas/testsuite/gas/arc/bl.s
@@ -1,5 +1,5 @@
 # bl test
-       
+
 text_label:
 
        bl      text_label
@@ -32,9 +32,13 @@ text_label:
        blpnz   text_label
 
        bl.d    text_label
+       nop_s
        bl.nd   text_label
-       bl.jd   text_label
+       nop_s
 
        bleq.d  text_label
+       nop_s
        blne.nd text_label
-       blcc.jd text_label
+       nop_s
+       blcc.d  text_label
+       nop_s

diff --git a/gas/testsuite/gas/arc/branch.d b/gas/testsuite/gas/arc/branch.d
deleted file mode 100644 (file)
index 4c9b014..0000000
--- a/gas/testsuite/gas/arc/branch.d
+++ /dev/null
@@ -1,45 +0,0 @@
-#objdump: -dr
-#name: @OC@
-
-# Test the @OC@ insn.
-
-.*: +file format elf32-.*arc
-
-Disassembly of section .text:
-00000000 <text_label> @IC+7@ffff80     @OC@ 00000000 <text_label>
-00000004 <text_label\+4> @IC+7@ffff00  @OC@ 00000000 <text_label>
-00000008 <text_label\+8> @IC+7@fffe80  @OC@ 00000000 <text_label>
-0000000c <text_label\+c> @IC+7@fffe01  @OC@eq 00000000 <text_label>
-00000010 <text_label\+10> @IC+7@fffd81 @OC@eq 00000000 <text_label>
-00000014 <text_label\+14> @IC+7@fffd02 @OC@ne 00000000 <text_label>
-00000018 <text_label\+18> @IC+7@fffc82 @OC@ne 00000000 <text_label>
-0000001c <text_label\+1c> @IC+7@fffc03 @OC@p 00000000 <text_label>
-00000020 <text_label\+20> @IC+7@fffb83 @OC@p 00000000 <text_label>
-00000024 <text_label\+24> @IC+7@fffb04 @OC@n 00000000 <text_label>
-00000028 <text_label\+28> @IC+7@fffa84 @OC@n 00000000 <text_label>
-0000002c <text_label\+2c> @IC+7@fffa05 @OC@c 00000000 <text_label>
-00000030 <text_label\+30> @IC+7@fff985 @OC@c 00000000 <text_label>
-00000034 <text_label\+34> @IC+7@fff905 @OC@c 00000000 <text_label>
-00000038 <text_label\+38> @IC+7@fff886 @OC@nc 00000000 <text_label>
-0000003c <text_label\+3c> @IC+7@fff806 @OC@nc 00000000 <text_label>
-00000040 <text_label\+40> @IC+7@fff786 @OC@nc 00000000 <text_label>
-00000044 <text_label\+44> @IC+7@fff707 @OC@v 00000000 <text_label>
-00000048 <text_label\+48> @IC+7@fff687 @OC@v 00000000 <text_label>
-0000004c <text_label\+4c> @IC+7@fff608 @OC@nv 00000000 <text_label>
-00000050 <text_label\+50> @IC+7@fff588 @OC@nv 00000000 <text_label>
-00000054 <text_label\+54> @IC+7@fff509 @OC@gt 00000000 <text_label>
-00000058 <text_label\+58> @IC+7@fff48a @OC@ge 00000000 <text_label>
-0000005c <text_label\+5c> @IC+7@fff40b @OC@lt 00000000 <text_label>
-00000060 <text_label\+60> @IC+7@fff38c @OC@le 00000000 <text_label>
-00000064 <text_label\+64> @IC+7@fff30d @OC@hi 00000000 <text_label>
-00000068 <text_label\+68> @IC+7@fff28e @OC@ls 00000000 <text_label>
-0000006c <text_label\+6c> @IC+7@fff20f @OC@pnz 00000000 <text_label>
-00000070 <text_label\+70> @IC+7@ffff80 @OC@ 00000070 <text_label\+70>
-               RELOC: 00000070 R_ARC_B22_PCREL external_text_label
-00000074 <text_label\+74> @IC+0@000000 @OC@ 00000078 <text_label\+78>
-00000078 <text_label\+78> @IC+7@fff0a0 @OC@.d 00000000 <text_label>
-0000007c <text_label\+7c> @IC+7@fff000 @OC@ 00000000 <text_label>
-00000080 <text_label\+80> @IC+7@ffefc0 @OC@.jd 00000000 <text_label>
-00000084 <text_label\+84> @IC+7@ffef21 @OC@eq.d 00000000 <text_label>
-00000088 <text_label\+88> @IC+7@ffee82 @OC@ne 00000000 <text_label>
-0000008c <text_label\+8c> @IC+7@ffee46 @OC@nc.jd 00000000 <text_label>

diff --git a/gas/testsuite/gas/arc/branch.s b/gas/testsuite/gas/arc/branch.s
deleted file mode 100644 (file)
index 8bf1618..0000000
--- a/gas/testsuite/gas/arc/branch.s
+++ /dev/null
@@ -1,47 +0,0 @@
-# @OC@ test
-       
-text_label:
-
-# Condition tests
-       @OC@    text_label
-       @OC@al  text_label
-       @OC@ra  text_label
-       @OC@eq  text_label
-       @OC@z   text_label
-       @OC@ne  text_label
-       @OC@nz  text_label
-       @OC@pl  text_label
-       @OC@p   text_label
-       @OC@mi  text_label
-       @OC@n   text_label
-       @OC@cs  text_label
-       @OC@c   text_label
-       @OC@lo  text_label
-       @OC@cc  text_label
-       @OC@nc  text_label
-       @OC@hs  text_label
-       @OC@vs  text_label
-       @OC@v   text_label
-       @OC@vc  text_label
-       @OC@nv  text_label
-       @OC@gt  text_label
-       @OC@ge  text_label
-       @OC@lt  text_label
-       @OC@le  text_label
-       @OC@hi  text_label
-       @OC@ls  text_label
-       @OC@pnz text_label
-
-       @OC@    external_text_label
-
-       @OC@    0
-
-# Delay slots
-       @OC@.d  text_label
-       @OC@.nd text_label
-       @OC@.jd text_label
-
-# Condition tests and delay slots
-       @OC@eq.d        text_label
-       @OC@ne.nd       text_label
-       @OC@cc.jd       text_label

diff --git a/gas/testsuite/gas/arc/brk.d b/gas/testsuite/gas/arc/brk.d
index 70f9e4f..9a48863 100644 (file)
--- a/gas/testsuite/gas/arc/brk.d
+++ b/gas/testsuite/gas/arc/brk.d
@@ -1,11 +1,9 @@
-#as: -EL -marc7
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <main>:
-   0:  00 84 00 40     40008400     add        r0,r1,r2
-   4:  00 fe ff 1f     1ffffe00     brk        
-   8:  00 0a 62 50     50620a00     sub        r3,r4,r5
+0x00000000 2100 0080                   add     r0,r1,r2
+0x00000004 256f 003f                   brk
+0x00000008 2402 0143                   sub     r3,r4,r5

diff --git a/gas/testsuite/gas/arc/brk.s b/gas/testsuite/gas/arc/brk.s
index 00b0761..cd3202e 100644 (file)
--- a/gas/testsuite/gas/arc/brk.s
+++ b/gas/testsuite/gas/arc/brk.s
@@ -1,7 +1,5 @@
 # brk test
 
-main:
-
-       add     r0,r1,r2        
+       add     r0,r1,r2
        brk
        sub     r3,r4,r5

diff --git a/gas/testsuite/gas/arc/extb.d b/gas/testsuite/gas/arc/extb.d
index 1ceca8a..6884d9d 100644 (file)
--- a/gas/testsuite/gas/arc/extb.d
+++ b/gas/testsuite/gas/arc/extb.d
@@ -1,51 +1,22 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 8e 00 18     18008e00     extb       r0,r1
-   4:  00 0e 6e 1b     1b6e0e00     extb       fp,sp
-   8:  00 8e 1f 18     181f8e00     extb       r0,0
-   c:  ff 8f 3f 18     183f8fff     extb       r1,-1
-  10:  00 0e e1 1f     1fe10e00     extb       0,r2
-  14:  00 8e e1 1f     1fe18e00     extb       0,r3
-  18:  ff 8e 9f 18     189f8eff     extb       r4,255
-  1c:  00 8e e2 1f     1fe28e00     extb       0,r5
-  20:  00 8f df 18     18df8f00     extb       r6,-256
-  24:  00 8e e3 1f     1fe38e00     extb       0,r7
-  28:  00 0e 1f 19     191f0e00     extb       r8,0x100
-  2c:  00 01 00 00 
-  30:  00 0e 3f 19     193f0e00     extb       r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 0e 7f 19     197f0e00     extb       r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 0e ff 1f     1fff0e00     extb       0,0x100
-  44:  00 01 00 00 
-  48:  00 0e 1f 18     181f0e00     extb       r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 8e 45 19     19458e01     extb.z     r10,r11
-  54:  02 8e 86 19     19868e02     extb.nz    r12,r13
-  58:  0b 0e df 19     19df0e0b     extb.lt    r14,0
-  5c:  00 00 00 00 
-  60:  09 0e ff 19     19ff0e09     extb.gt    r15,0x200
-  64:  00 02 00 00 
-  68:  00 8f 00 18     18008f00     extb.f     r0,r1
-  6c:  01 8e 5e 18     185e8e01     extb.f     r2,1
-  70:  00 0f e2 1f     1fe20f00     extb.f     0,r4
-  74:  00 0f bf 18     18bf0f00     extb.f     r5,0x200
-  78:  00 02 00 00 
-  7c:  00 0f df 1f     1fdf0f00     extb.f     0,0x200
-  80:  00 02 00 00 
-  84:  01 8f 00 18     18008f01     extb.z.f   r0,r1
-  88:  02 0f 3f 18     183f0f02     extb.nz.f  r1,0
-  8c:  00 00 00 00 
-  90:  0b 0f c1 1f     1fc10f0b     extb.lt.f  0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 0f 1f 18     181f0f0c     extb.le.f  r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 0f df 1f     1fdf0f04     extb.n.f   0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 202f 0047                  extb    r0,r1
+0x[0-9a-f]+ 232f 3707                  extb    fp,sp
+0x[0-9a-f]+ 206f 0007                  extb    r0,0
+0x[0-9a-f]+ 212f 0f87 ffff ffff        extb    r1,0xffffffff
+0x[0-9a-f]+ 262f 7087                  extb    0,r2
+0x[0-9a-f]+ 242f 0f87 0000 00ff        extb    r4,0xff
+0x[0-9a-f]+ 262f 0f87 ffff ff00        extb    r6,0xffffff00
+0x[0-9a-f]+ 202f 1f87 0000 0100        extb    r8,0x100
+0x[0-9a-f]+ 212f 1f87 ffff feff        extb    r9,0xfffffeff
+0x[0-9a-f]+ 232f 1f87 4242 4242        extb    r11,0x42424242
+0x[0-9a-f]+ 202f 0f87 0000 0000        extb    r0,0
+                       44: ARC_32_ME   foo
+0x[0-9a-f]+ 202f 8047                  extb.f  r0,r1
+0x[0-9a-f]+ 226f 8047                  extb.f  r2,0x1
+0x[0-9a-f]+ 262f f107                  extb.f  0,r4
+0x[0-9a-f]+ 252f 8f87 0000 0200        extb.f  r5,0x200

diff --git a/gas/testsuite/gas/arc/extb.s b/gas/testsuite/gas/arc/extb.s
index e872975..050c73b 100644 (file)
--- a/gas/testsuite/gas/arc/extb.s
+++ b/gas/testsuite/gas/arc/extb.s
@@ -6,33 +6,16 @@
        extb r0,0
        extb r1,-1
        extb 0,r2
-       extb -1,r3
        extb r4,255
-       extb 255,r5
        extb r6,-256
-       extb -256,r7
 
        extb r8,256
        extb r9,-257
        extb r11,0x42424242
 
-       extb 255,256
-
        extb r0,foo
 
-       extb.eq r10,r11
-       extb.ne r12,r13
-       extb.lt r14,0
-       extb.gt r15,512
-
        extb.f r0,r1
        extb.f r2,1
        extb.f 0,r4
        extb.f r5,512
-       extb.f 512,512
-
-       extb.eq.f r0,r1
-       extb.ne.f r1,0
-       extb.lt.f 0,r2
-       extb.le.f r0,512
-       extb.n.f 512,512

diff --git a/gas/testsuite/gas/arc/extensions.d b/gas/testsuite/gas/arc/extensions.d
index dc0d80b..73d8a00 100644 (file)
--- a/gas/testsuite/gas/arc/extensions.d
+++ b/gas/testsuite/gas/arc/extensions.d
@@ -1,5 +1,6 @@
-#as: -EL -marc8
+#as: -EL
 #objdump: -dr -EL
+#skip: *-*-*
 
 .*: +file format elf32-.*arc
 
@@ -9,4 +10,4 @@ Disassembly of section .text:
    0:  12 02 00 40     40000212     add.isbusy r0,r0,r1
    4:  00 02 60 45     45600200     add        rwscreg,r0,r1
    8:  00 d8 00 40     4000d800     add        r0,r1,roscreg
-   c:  00 02 a0 45     45a00200     add        woscreg,r0,r1
\ No newline at end of file
+   c:  00 02 a0 45     45a00200     add        woscreg,r0,r1

diff --git a/gas/testsuite/gas/arc/extw.d b/gas/testsuite/gas/arc/extw.d
index 500f2fa..c33768b 100644 (file)
--- a/gas/testsuite/gas/arc/extw.d
+++ b/gas/testsuite/gas/arc/extw.d
@@ -1,51 +1,22 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 90 00 18     18009000     extw       r0,r1
-   4:  00 10 6e 1b     1b6e1000     extw       fp,sp
-   8:  00 90 1f 18     181f9000     extw       r0,0
-   c:  ff 91 3f 18     183f91ff     extw       r1,-1
-  10:  00 10 e1 1f     1fe11000     extw       0,r2
-  14:  00 90 e1 1f     1fe19000     extw       0,r3
-  18:  ff 90 9f 18     189f90ff     extw       r4,255
-  1c:  00 90 e2 1f     1fe29000     extw       0,r5
-  20:  00 91 df 18     18df9100     extw       r6,-256
-  24:  00 90 e3 1f     1fe39000     extw       0,r7
-  28:  00 10 1f 19     191f1000     extw       r8,0x100
-  2c:  00 01 00 00 
-  30:  00 10 3f 19     193f1000     extw       r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 10 7f 19     197f1000     extw       r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 10 ff 1f     1fff1000     extw       0,0x100
-  44:  00 01 00 00 
-  48:  00 10 1f 18     181f1000     extw       r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 90 45 19     19459001     extw.z     r10,r11
-  54:  02 90 86 19     19869002     extw.nz    r12,r13
-  58:  0b 10 df 19     19df100b     extw.lt    r14,0
-  5c:  00 00 00 00 
-  60:  09 10 ff 19     19ff1009     extw.gt    r15,0x200
-  64:  00 02 00 00 
-  68:  00 91 00 18     18009100     extw.f     r0,r1
-  6c:  01 90 5e 18     185e9001     extw.f     r2,1
-  70:  00 11 e2 1f     1fe21100     extw.f     0,r4
-  74:  00 11 bf 18     18bf1100     extw.f     r5,0x200
-  78:  00 02 00 00 
-  7c:  00 11 df 1f     1fdf1100     extw.f     0,0x200
-  80:  00 02 00 00 
-  84:  01 91 00 18     18009101     extw.z.f   r0,r1
-  88:  02 11 3f 18     183f1102     extw.nz.f  r1,0
-  8c:  00 00 00 00 
-  90:  0b 11 c1 1f     1fc1110b     extw.lt.f  0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 11 1f 18     181f110c     extw.le.f  r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 11 df 1f     1fdf1104     extw.n.f   0,0x200
-  a4:  00 02 00 00 
+0x00000000 202f 0048                   ext[hw]+        r0,r1
+0x00000004 232f 3708                   ext[hw]+        fp,sp
+0x00000008 206f 0008                   ext[hw]+        r0,0
+0x0000000c 212f 0f88 ffff ffff         ext[hw]+        r1,0xffffffff
+0x00000014 262f 7088                   ext[hw]+        0,r2
+0x00000018 242f 0f88 0000 00ff         ext[hw]+        r4,0xff
+0x00000020 262f 0f88 ffff ff00         ext[hw]+        r6,0xffffff00
+0x00000028 202f 1f88 0000 0100         ext[hw]+        r8,0x100
+0x00000030 212f 1f88 ffff feff         ext[hw]+        r9,0xfffffeff
+0x00000038 232f 1f88 4242 4242         ext[hw]+        r11,0x42424242
+0x00000040 202f 0f88 0000 0000         ext[hw]+        r0,0
+                       44: ARC_32_ME   foo
+0x00000048 202f 8048                   ext[hw]+.f      r0,r1
+0x0000004c 226f 8048                   ext[hw]+.f      r2,0x1
+0x00000050 262f f108                   ext[hw]+.f      0,r4
+0x00000054 252f 8f88 0000 0200         ext[hw]+.f      r5,0x200

diff --git a/gas/testsuite/gas/arc/extw.s b/gas/testsuite/gas/arc/extw.s
index 060a8e3..9cde2aa 100644 (file)
--- a/gas/testsuite/gas/arc/extw.s
+++ b/gas/testsuite/gas/arc/extw.s
@@ -6,33 +6,16 @@
        extw r0,0
        extw r1,-1
        extw 0,r2
-       extw -1,r3
        extw r4,255
-       extw 255,r5
        extw r6,-256
-       extw -256,r7
 
        extw r8,256
        extw r9,-257
        extw r11,0x42424242
 
-       extw 255,256
-
        extw r0,foo
 
-       extw.eq r10,r11
-       extw.ne r12,r13
-       extw.lt r14,0
-       extw.gt r15,512
-
        extw.f r0,r1
        extw.f r2,1
        extw.f 0,r4
        extw.f r5,512
-       extw.f 512,512
-
-       extw.eq.f r0,r1
-       extw.ne.f r1,0
-       extw.lt.f 0,r2
-       extw.le.f r0,512
-       extw.n.f 512,512

diff --git a/gas/testsuite/gas/arc/flag.d b/gas/testsuite/gas/arc/flag.d
index 55c59de..5371439 100644 (file)
--- a/gas/testsuite/gas/arc/flag.d
+++ b/gas/testsuite/gas/arc/flag.d
@@ -1,38 +1,26 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 00 a0 1f     1fa00000     flag       r0
-   4:  01 80 bf 1f     1fbf8001     flag       1
-   8:  02 80 bf 1f     1fbf8002     flag       2
-   c:  04 80 bf 1f     1fbf8004     flag       4
-  10:  08 80 bf 1f     1fbf8008     flag       8
-  14:  10 80 bf 1f     1fbf8010     flag       16
-  18:  20 80 bf 1f     1fbf8020     flag       32
-  1c:  40 80 bf 1f     1fbf8040     flag       64
-  20:  80 80 bf 1f     1fbf8080     flag       128
-  24:  00 00 bf 1f     1fbf0000     flag       0x8000_0001
-  28:  01 00 00 80 
-  2c:  0b 00 a0 1f     1fa0000b     flag.lt    r0
-  30:  09 00 bf 1f     1fbf0009     flag.gt    1
-  34:  01 00 00 00 
-  38:  09 00 bf 1f     1fbf0009     flag.gt    2
-  3c:  02 00 00 00 
-  40:  09 00 bf 1f     1fbf0009     flag.gt    4
-  44:  04 00 00 00 
-  48:  09 00 bf 1f     1fbf0009     flag.gt    8
-  4c:  08 00 00 00 
-  50:  09 00 bf 1f     1fbf0009     flag.gt    16
-  54:  10 00 00 00 
-  58:  09 00 bf 1f     1fbf0009     flag.gt    32
-  5c:  20 00 00 00 
-  60:  09 00 bf 1f     1fbf0009     flag.gt    64
-  64:  40 00 00 00 
-  68:  09 00 bf 1f     1fbf0009     flag.gt    128
-  6c:  80 00 00 00 
-  70:  0a 00 bf 1f     1fbf000a     flag.ge    0x8000_0001
-  74:  01 00 00 80 
+0x[0-9a-f]+ 2029 0000                  flag    r0
+0x[0-9a-f]+ 2069 0040                  flag    0x1
+0x[0-9a-f]+ 2069 0080                  flag    0x2
+0x[0-9a-f]+ 2069 0100                  flag    0x4
+0x[0-9a-f]+ 2069 0200                  flag    0x8
+0x[0-9a-f]+ 2069 0400                  flag    0x10
+0x[0-9a-f]+ 2069 0800                  flag    0x20
+0x[0-9a-f]+ 20a9 0001                  flag    64
+0x[0-9a-f]+ 20a9 0002                  flag    128
+0x[0-9a-f]+ 2029 0f80 8000 0001        flag    0x80000001
+0x[0-9a-f]+ 20e9 000b                  flag.lt r0
+0x[0-9a-f]+ 20e9 0069                  flag.gt 0x1
+0x[0-9a-f]+ 20e9 00a9                  flag.gt 0x2
+0x[0-9a-f]+ 20e9 0129                  flag.gt 0x4
+0x[0-9a-f]+ 20e9 0229                  flag.gt 0x8
+0x[0-9a-f]+ 20e9 0429                  flag.gt 0x10
+0x[0-9a-f]+ 20e9 0829                  flag.gt 0x20
+0x[0-9a-f]+ 20e9 0f89 0000 0040        flag.gt 0x40
+0x[0-9a-f]+ 20e9 0f89 0000 0080        flag.gt 0x80
+0x[0-9a-f]+ 20e9 0f8a 8000 0001        flag.ge 0x80000001

diff --git a/gas/testsuite/gas/arc/insn3.d b/gas/testsuite/gas/arc/insn3.d
deleted file mode 100644 (file)
index c0207a7..0000000
--- a/gas/testsuite/gas/arc/insn3.d
+++ /dev/null
@@ -1,44 +0,0 @@
-#objdump: -dr
-#name: @OC@
-
-# Test the @OC@ insn.
-
-.*: +file format elf32-.*arc
-
-Disassembly of section .text:
-00000000 1800@I3+80@00 @OC@ r0,r1
-00000004 1b6e@I3+00@00 @OC@ fp,sp
-00000008 181f@I3+80@00 @OC@ r0,0
-0000000c 183f@I3+81@ff @OC@ r1,-1
-00000010 1fe1@I3+00@00 @OC@ 0,r2
-00000014 1fe1@I3+81@ff @OC@ -1,r3
-00000018 189f@I3+80@ff @OC@ r4,255
-0000001c 1fe2@I3+80@ff @OC@ 255,r5
-00000020 18df@I3+81@00 @OC@ r6,-256
-00000024 1fe3@I3+81@00 @OC@ -256,r7
-00000028 191f@I3+00@00 @OC@ r8,256
-00000030 193f@I3+00@00 @OC@ r9,-257
-00000038 1fc5@I3+00@00 @OC@ 511,r10
-00000040 197f@I3+00@00 @OC@ r11,1111638594
-00000048 1fc6@I3+00@00 @OC@ 305419896,r12
-00000050 1fff@I3+00@ff @OC@ 255,256
-00000058 1fdf@I3+80@ff @OC@ 256,255
-00000060 181f@I3+00@00 @OC@ r0,0
-               RELOC: 00000064 R_ARC_32 foo
-00000068 1945@I3+80@01 @OC@.eq r10,r11
-0000006c 1986@I3+80@02 @OC@.ne r12,r13
-00000070 19df@I3+00@0b @OC@.lt r14,0
-00000078 19ff@I3+00@09 @OC@.gt r15,512
-00000080 1800@I3+81@00 @OC@.f r0,r1
-00000084 185e@I3+80@01 @OC@.f r2,1
-00000088 1fa2@I3+00@00 @OC@.f 0,r4
-0000008c 18bf@I3+01@00 @OC@.f r5,512
-00000094 1fc3@I3+01@00 @OC@.f 512,r6
-0000009c 1fdf@I3+01@00 @OC@.f 512,512
-000000a4 1800@I3+81@01 @OC@.eq.f r0,r1
-000000a8 183f@I3+01@02 @OC@.ne.f r1,0
-000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2
-000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2
-000000c0 181f@I3+01@0c @OC@.le.f r0,512
-000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2
-000000d0 1fdf@I3+01@04 @OC@.n.f 512,512

diff --git a/gas/testsuite/gas/arc/insn3.s b/gas/testsuite/gas/arc/insn3.s
deleted file mode 100644 (file)
index f12fb88..0000000
--- a/gas/testsuite/gas/arc/insn3.s
+++ /dev/null
@@ -1,52 +0,0 @@
-# Insn 3 @OC@ test
-
-# reg,reg
-       @OC@ r0,r1
-       @OC@ fp,sp
-
-# shimm values
-       @OC@ r0,0
-       @OC@ r1,-1
-       @OC@ 0,r2
-       @OC@ -1,r3
-       @OC@ r4,255
-       @OC@ 255,r5
-       @OC@ r6,-256
-       @OC@ -256,r7
-
-# limm values
-       @OC@ r8,256
-       @OC@ r9,-257
-       @OC@ 511,r10
-       @OC@ r11,0x42424242
-       @OC@ 0x12345678,r12
-
-# shimm and limm
-       @OC@ 255,256
-       @OC@ 256,255
-
-# symbols
-       @OC@ r0,foo
-
-# conditional execution
-       @OC@.eq r10,r11
-       @OC@.ne r12,r13
-       @OC@.lt r14,0
-       @OC@.gt r15,512
-
-# flag setting
-       @OC@.f r0,r1
-       @OC@.f r2,1
-       @OC@.f 0,r4
-       @OC@.f r5,512
-       @OC@.f 512,r6
-       @OC@.f 512,512
-
-# conditional execution + flag setting
-       @OC@.eq.f r0,r1
-       @OC@.ne.f r1,0
-       @OC@.lt.f 0,r2
-       @OC@.gt.f 1,r2
-       @OC@.le.f r0,512
-       @OC@.ge.f 512,r2
-       @OC@.n.f 512,512

diff --git a/gas/testsuite/gas/arc/j.d b/gas/testsuite/gas/arc/j.d
index 87e8004..6e28d1f 100644 (file)
--- a/gas/testsuite/gas/arc/j.d
+++ b/gas/testsuite/gas/arc/j.d
@@ -1,127 +1,67 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <text_label>:
-   0:  00 00 1f 38     381f0000     j          0 <text_label>
-
-   4:  00 00 00 00 
-                       4: R_ARC_B26    .text
-   8:  00 00 1f 38     381f0000     j          0 <text_label>
-
-   c:  00 00 00 00 
-                       c: R_ARC_B26    .text
-  10:  00 00 1f 38     381f0000     j          0 <text_label>
-
-  14:  00 00 00 00 
-                       14: R_ARC_B26   .text
-  18:  01 00 1f 38     381f0001     jz         0 <text_label>
-
-  1c:  00 00 00 00 
-                       1c: R_ARC_B26   .text
-  20:  01 00 1f 38     381f0001     jz         0 <text_label>
-
-  24:  00 00 00 00 
-                       24: R_ARC_B26   .text
-  28:  02 00 1f 38     381f0002     jnz        0 <text_label>
-
-  2c:  00 00 00 00 
-                       2c: R_ARC_B26   .text
-  30:  02 00 1f 38     381f0002     jnz        0 <text_label>
-
-  34:  00 00 00 00 
-                       34: R_ARC_B26   .text
-  38:  03 00 1f 38     381f0003     jp         0 <text_label>
-
-  3c:  00 00 00 00 
-                       3c: R_ARC_B26   .text
-  40:  03 00 1f 38     381f0003     jp         0 <text_label>
-
-  44:  00 00 00 00 
-                       44: R_ARC_B26   .text
-  48:  04 00 1f 38     381f0004     jn         0 <text_label>
-
-  4c:  00 00 00 00 
-                       4c: R_ARC_B26   .text
-  50:  04 00 1f 38     381f0004     jn         0 <text_label>
-
-  54:  00 00 00 00 
-                       54: R_ARC_B26   .text
-  58:  05 00 1f 38     381f0005     jc         0 <text_label>
-
-  5c:  00 00 00 00 
-                       5c: R_ARC_B26   .text
-  60:  05 00 1f 38     381f0005     jc         0 <text_label>
-
-  64:  00 00 00 00 
-                       64: R_ARC_B26   .text
-  68:  05 00 1f 38     381f0005     jc         0 <text_label>
-
-  6c:  00 00 00 00 
-                       6c: R_ARC_B26   .text
-  70:  06 00 1f 38     381f0006     jnc        0 <text_label>
-
-  74:  00 00 00 00 
-                       74: R_ARC_B26   .text
-  78:  06 00 1f 38     381f0006     jnc        0 <text_label>
-
-  7c:  00 00 00 00 
-                       7c: R_ARC_B26   .text
-  80:  06 00 1f 38     381f0006     jnc        0 <text_label>
-
-  84:  00 00 00 00 
-                       84: R_ARC_B26   .text
-  88:  07 00 1f 38     381f0007     jv         0 <text_label>
-
-  8c:  00 00 00 00 
-                       8c: R_ARC_B26   .text
-  90:  07 00 1f 38     381f0007     jv         0 <text_label>
-
-  94:  00 00 00 00 
-                       94: R_ARC_B26   .text
-  98:  08 00 1f 38     381f0008     jnv        0 <text_label>
-
-  9c:  00 00 00 00 
-                       9c: R_ARC_B26   .text
-  a0:  08 00 1f 38     381f0008     jnv        0 <text_label>
-
-  a4:  00 00 00 00 
-                       a4: R_ARC_B26   .text
-  a8:  09 00 1f 38     381f0009     jgt        0 <text_label>
-
-  ac:  00 00 00 00 
-                       ac: R_ARC_B26   .text
-  b0:  0a 00 1f 38     381f000a     jge        0 <text_label>
-
-  b4:  00 00 00 00 
-                       b4: R_ARC_B26   .text
-  b8:  0b 00 1f 38     381f000b     jlt        0 <text_label>
-
-  bc:  00 00 00 00 
-                       bc: R_ARC_B26   .text
-  c0:  0c 00 1f 38     381f000c     jle        0 <text_label>
-
-  c4:  00 00 00 00 
-                       c4: R_ARC_B26   .text
-  c8:  0d 00 1f 38     381f000d     jhi        0 <text_label>
-
-  cc:  00 00 00 00 
-                       cc: R_ARC_B26   .text
-  d0:  0e 00 1f 38     381f000e     jls        0 <text_label>
-
-  d4:  00 00 00 00 
-                       d4: R_ARC_B26   .text
-  d8:  0f 00 1f 38     381f000f     jpnz       0 <text_label>
-
-  dc:  00 00 00 00 
-                       dc: R_ARC_B26   .text
-  e0:  00 00 1f 38     381f0000     j          0 <text_label>
-
-  e4:  00 00 00 00 
-                       e4: R_ARC_B26   external_text_label
-  e8:  00 00 1f 38     381f0000     j          0 <text_label>
-
-  ec:  00 00 00 00 
+[0-9a-f]+ <text_label>:
+   0:  2020 0f80 0000 0000     j       0
+                       4: ARC_32_ME    text_label
+   8:  20e0 0f80 0000 0000     j       0
+                       c: ARC_32_ME    text_label
+  10:  20e0 0f80 0000 0000     j       0
+                       14: ARC_32_ME   text_label
+  18:  20e0 0f81 0000 0000     jeq     0
+                       1c: ARC_32_ME   text_label
+  20:  20e0 0f81 0000 0000     jeq     0
+                       24: ARC_32_ME   text_label
+  28:  20e0 0f82 0000 0000     jne     0
+                       2c: ARC_32_ME   text_label
+  30:  20e0 0f82 0000 0000     jne     0
+                       34: ARC_32_ME   text_label
+  38:  20e0 0f83 0000 0000     jp      0
+                       3c: ARC_32_ME   text_label
+  40:  20e0 0f83 0000 0000     jp      0
+                       44: ARC_32_ME   text_label
+  48:  20e0 0f84 0000 0000     jn      0
+                       4c: ARC_32_ME   text_label
+  50:  20e0 0f84 0000 0000     jn      0
+                       54: ARC_32_ME   text_label
+  58:  20e0 0f85 0000 0000     jc      0
+                       5c: ARC_32_ME   text_label
+  60:  20e0 0f85 0000 0000     jc      0
+                       64: ARC_32_ME   text_label
+  68:  20e0 0f85 0000 0000     jc      0
+                       6c: ARC_32_ME   text_label
+  70:  20e0 0f86 0000 0000     jnc     0
+                       74: ARC_32_ME   text_label
+  78:  20e0 0f86 0000 0000     jnc     0
+                       7c: ARC_32_ME   text_label
+  80:  20e0 0f86 0000 0000     jnc     0
+                       84: ARC_32_ME   text_label
+  88:  20e0 0f87 0000 0000     jv      0
+                       8c: ARC_32_ME   text_label
+  90:  20e0 0f87 0000 0000     jv      0
+                       94: ARC_32_ME   text_label
+  98:  20e0 0f88 0000 0000     jnv     0
+                       9c: ARC_32_ME   text_label
+  a0:  20e0 0f88 0000 0000     jnv     0
+                       a4: ARC_32_ME   text_label
+  a8:  20e0 0f89 0000 0000     jgt     0
+                       ac: ARC_32_ME   text_label
+  b0:  20e0 0f8a 0000 0000     jge     0
+                       b4: ARC_32_ME   text_label
+  b8:  20e0 0f8b 0000 0000     jlt     0
+                       bc: ARC_32_ME   text_label
+  c0:  20e0 0f8c 0000 0000     jle     0
+                       c4: ARC_32_ME   text_label
+  c8:  20e0 0f8d 0000 0000     jhi     0
+                       cc: ARC_32_ME   text_label
+  d0:  20e0 0f8e 0000 0000     jls     0
+                       d4: ARC_32_ME   text_label
+  d8:  20e0 0f8f 0000 0000     jpnz    0
+                       dc: ARC_32_ME   text_label
+  e0:  2020 0f80 0000 0000     j       0
+                       e4: ARC_32_ME   external_text_label
+  e8:  20a0 0000               j       0

diff --git a/gas/testsuite/gas/arc/j.s b/gas/testsuite/gas/arc/j.s
index 64abbf5..24a6f38 100644 (file)
--- a/gas/testsuite/gas/arc/j.s
+++ b/gas/testsuite/gas/arc/j.s
@@ -1,6 +1,6 @@
 # j test
-       
-text_label:    
+
+text_label:
 
        j       text_label
        jal     text_label

diff --git a/gas/testsuite/gas/arc/jl.d b/gas/testsuite/gas/arc/jl.d
index 3701f9a..7330c15 100644 (file)
--- a/gas/testsuite/gas/arc/jl.d
+++ b/gas/testsuite/gas/arc/jl.d
@@ -1,25 +1,14 @@
-#as: -EL -marc6
-#objdump: -dr -EL
+#as: -mcpu=archs
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <text_label>:
-   0:  40 02 1f 38     381f0240     jl         0 <text_label>
-
-   4:  00 00 00 00 
-                       4: R_ARC_B26    .text
-   8:  40 03 1f 38     381f0340     jl.f       0 <text_label>
-
-   c:  00 00 00 00 
-                       c: R_ARC_B26    .text
-  10:  02 82 00 38     38008202     jlnz       \[r1\]
-  14:  40 02 1f 38     381f0240     jl         0 <text_label>
-
-  18:  00 00 00 00 
-                       18: R_ARC_B26   .text
-  1c:  40 03 1f 38     381f0340     jl.f       0 <text_label>
-
-  20:  00 00 00 00 
-                       20: R_ARC_B26   .text
+[0-9a-f]+ <text_label>:
+   0:  2022 0f80 0000 0000     jl      0
+                       4: ARC_32_ME    text_label
+   8:  20e3 0042               jlne.d  \[r1\]
+   c:  78e0                    nop_s
+   e:  20e2 0f80 0000 0000     jl      0
+                       12: ARC_32_ME   text_label

diff --git a/gas/testsuite/gas/arc/jl.s b/gas/testsuite/gas/arc/jl.s
index 74a9e20..bb660c7 100644 (file)
--- a/gas/testsuite/gas/arc/jl.s
+++ b/gas/testsuite/gas/arc/jl.s
@@ -3,7 +3,6 @@
 text_label:
 
        jl      text_label
-       jl.f    text_label
-       jlnz.nd [r1]
+       jlnz.d  [r1]
+       nop_s
        jlal    text_label
-       jlal.f  text_label

diff --git a/gas/testsuite/gas/arc/ld.d b/gas/testsuite/gas/arc/ld.d
index 2680ae9..eef573f 100644 (file)
--- a/gas/testsuite/gas/arc/ld.d
+++ b/gas/testsuite/gas/arc/ld.d
@@ -1,16 +1,16 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <.text>:
-   0:  00 84 00 00     00008400     ld         r0,\[r1,r2\]
-   4:  02 84 00 00     00008402     ldb        r0,\[r1,r2\]
-   8:  08 88 21 00     00218808     ld.a       r1,\[r3,r4\]
-   c:  05 06 21 00     00210605     ldw.x      r1,\[r2,r3\]
-  10:  0d 88 41 00     0041880d     ldw.x.a    r2,\[r3,r4\]
-  14:  00 80 1f 08     081f8000     ld         r0,\[0\]
-  18:  1e 80 00 08     0800801e     ld         r0,\[r1,30\]
-  1c:  ec 01 21 08     082101ec     ld         r1,\[r2,-20\]
+[0-9a-f]+ <.text>:
+   0:  2130 0080               ld      r0,\[r1,r2\]
+   4:  2132 0080               ldb     r0,\[r1,r2\]
+   8:  2370 0101               ld.aw   r1,\[r3,r4\]
+   c:  2235 00c1               ld[hw]+.x       r1,\[r2,r3\]
+  10:  2375 0102               ld[hw]+.aw.x    r2,\[r3,r4\]
+  14:  1600 7000 0000 0000     ld      r0,\[0\]
+  1c:  111e 0000               ld      r0,\[r1,30\]
+  20:  12ec 8001               ld      r1,\[r2,-20\]

diff --git a/gas/testsuite/gas/arc/ld.s b/gas/testsuite/gas/arc/ld.s
index 7d0a5b8..e77bee5 100644 (file)
--- a/gas/testsuite/gas/arc/ld.s
+++ b/gas/testsuite/gas/arc/ld.s
@@ -1,10 +1,10 @@
 # ld test
-       
+
        ld      r0,[r1,r2]
        ldb     r0,[r1,r2]
        ld.a    r1,[r3,r4]
        ldw.x   r1,[r2,r3]
        ldw.x.a r2,[r3,r4]
        ld      r0,[0]
-        ld      r0,[r1,30]
-        ld      r1,[r2,-20]
+       ld      r0,[r1,30]
+       ld      r1,[r2,-20]

diff --git a/gas/testsuite/gas/arc/ld2.d b/gas/testsuite/gas/arc/ld2.d
index 1f1df97..8e44c41 100644 (file)
--- a/gas/testsuite/gas/arc/ld2.d
+++ b/gas/testsuite/gas/arc/ld2.d
@@ -1,21 +1,19 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <.text>:
-   0:  00 80 00 08     08008000     ld         r0,\[r1\]
-   4:  01 00 a3 08     08a30001     ld         r5,\[r6,1\]
-   8:  00 00 7f 0a     0a7f0000     ld         r19,\[0\]
-   c:  00 00 00 00 
-                       c: R_ARC_32     foo
-  10:  0a 10 81 08     0881100a     ld.a       r4,\[r2,10\]
-  14:  00 00 3f 08     083f0000     ld         r1,\[0x384\]
-  18:  84 03 00 00 
-  1c:  0f 84 41 08     0841840f     ldb        r2,\[r3,15\]
-  20:  fe 09 62 08     086209fe     ldw        r3,\[r4,-2\]
-  24:  00 20 21 08     08212000     lr         r1,\[r2\]
-  28:  14 a0 3f 08     083fa014     lr         r1,\[0x14\]
-  2c:  00 a0 1f 08     081fa000     lr         r0,\[status\]
+[0-9a-f]+ <.text>:
+   0:  1100 0000               ld      r0,\[r1\]
+   4:  1601 0005               ld      r5,\[r6,1\]
+   8:  1600 7013 0000 0000     ld      r19,\[0\]
+                       c: ARC_32_ME    foo
+  10:  120a 0204               ld.aw   r4,\[r2,10\]
+  14:  1600 7001 0000 0384     ld      r1,\[0x384\]
+  1c:  130f 0082               ldb     r2,\[r3,15\]
+  20:  14fe 8103               ld[hw]+ r3,\[r4,-2\]
+  24:  212a 0080               lr      r1,\[r2\]
+  28:  216a 0500               lr      r1,\[0x14\]
+  2c:  206a 0000               lr      r0,\[0\]

diff --git a/gas/testsuite/gas/arc/ld2.s b/gas/testsuite/gas/arc/ld2.s
index c18556a..aae01ec 100644 (file)
--- a/gas/testsuite/gas/arc/ld2.s
+++ b/gas/testsuite/gas/arc/ld2.s
@@ -7,7 +7,7 @@
        ld      r1,[900]
        ldb     r2,[r3,15]
        ldw     r3,[r4,-2]
-       
+
        lr      r1,[r2]
        lr      r1,[20]
        lr      r0,[status]

diff --git a/gas/testsuite/gas/arc/lp.d b/gas/testsuite/gas/arc/lp.d
index 3b1827c..50bfd4a 100644 (file)
--- a/gas/testsuite/gas/arc/lp.d
+++ b/gas/testsuite/gas/arc/lp.d
@@ -1,76 +1,37 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=archs
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <text_label>:
-   0:  80 ff ff 37     37ffff80     lp         0 <text_label>
-
-   4:  00 ff ff 37     37ffff00     lp         0 <text_label>
-
-   8:  80 fe ff 37     37fffe80     lp         0 <text_label>
-
-   c:  01 fe ff 37     37fffe01     lpz        0 <text_label>
-
-  10:  81 fd ff 37     37fffd81     lpz        0 <text_label>
-
-  14:  02 fd ff 37     37fffd02     lpnz       0 <text_label>
-
-  18:  82 fc ff 37     37fffc82     lpnz       0 <text_label>
-
-  1c:  03 fc ff 37     37fffc03     lpp        0 <text_label>
-
-  20:  83 fb ff 37     37fffb83     lpp        0 <text_label>
-
-  24:  04 fb ff 37     37fffb04     lpn        0 <text_label>
-
-  28:  84 fa ff 37     37fffa84     lpn        0 <text_label>
-
-  2c:  05 fa ff 37     37fffa05     lpc        0 <text_label>
-
-  30:  85 f9 ff 37     37fff985     lpc        0 <text_label>
-
-  34:  05 f9 ff 37     37fff905     lpc        0 <text_label>
-
-  38:  86 f8 ff 37     37fff886     lpnc       0 <text_label>
-
-  3c:  06 f8 ff 37     37fff806     lpnc       0 <text_label>
-
-  40:  86 f7 ff 37     37fff786     lpnc       0 <text_label>
-
-  44:  07 f7 ff 37     37fff707     lpv        0 <text_label>
-
-  48:  87 f6 ff 37     37fff687     lpv        0 <text_label>
-
-  4c:  08 f6 ff 37     37fff608     lpnv       0 <text_label>
-
-  50:  88 f5 ff 37     37fff588     lpnv       0 <text_label>
-
-  54:  09 f5 ff 37     37fff509     lpgt       0 <text_label>
-
-  58:  8a f4 ff 37     37fff48a     lpge       0 <text_label>
-
-  5c:  0b f4 ff 37     37fff40b     lplt       0 <text_label>
-
-  60:  8c f3 ff 37     37fff38c     lple       0 <text_label>
-
-  64:  0d f3 ff 37     37fff30d     lphi       0 <text_label>
-
-  68:  8e f2 ff 37     37fff28e     lpls       0 <text_label>
-
-  6c:  0f f2 ff 37     37fff20f     lppnz      0 <text_label>
-
-  70:  a0 f1 ff 37     37fff1a0     lp.d       0 <text_label>
-
-  74:  00 f1 ff 37     37fff100     lp         0 <text_label>
-
-  78:  c0 f0 ff 37     37fff0c0     lp.jd      0 <text_label>
-
-  7c:  21 f0 ff 37     37fff021     lpz.d      0 <text_label>
-
-  80:  82 ef ff 37     37ffef82     lpnz       0 <text_label>
-
-  84:  46 ef ff 37     37ffef46     lpnc.jd    0 <text_label>
-
+[0-9a-f]+ <text_label-0x72>:
+   0:  20a8 0e40               lp      72 <text_label>
+   4:  20e8 0de0               lp      72 <text_label>
+   8:  20e8 0d60               lp      72 <text_label>
+   c:  20e8 0ce1               lpeq    72 <text_label>
+  10:  20e8 0c61               lpeq    72 <text_label>
+  14:  20e8 0be2               lpne    72 <text_label>
+  18:  20e8 0b62               lpne    72 <text_label>
+  1c:  20e8 0ae3               lpp     72 <text_label>
+  20:  20e8 0a63               lpp     72 <text_label>
+  24:  20e8 09e4               lpn     72 <text_label>
+  28:  20e8 0964               lpn     72 <text_label>
+  2c:  20e8 08e5               lpc     72 <text_label>
+  30:  20e8 0865               lpc     72 <text_label>
+  34:  20e8 07e5               lpc     72 <text_label>
+  38:  20e8 0766               lpnc    72 <text_label>
+  3c:  20e8 06e6               lpnc    72 <text_label>
+  40:  20e8 0666               lpnc    72 <text_label>
+  44:  20e8 05e7               lpv     72 <text_label>
+  48:  20e8 0567               lpv     72 <text_label>
+  4c:  20e8 04e8               lpnv    72 <text_label>
+  50:  20e8 0468               lpnv    72 <text_label>
+  54:  20e8 03e9               lpgt    72 <text_label>
+  58:  20e8 036a               lpge    72 <text_label>
+  5c:  20e8 02eb               lplt    72 <text_label>
+  60:  20e8 026c               lple    72 <text_label>
+  64:  20e8 01ed               lphi    72 <text_label>
+  68:  20e8 016e               lpls    72 <text_label>
+  6c:  20e8 00ef               lppnz   72 <text_label>
+  70:  78e0                    nop_s

diff --git a/gas/testsuite/gas/arc/lp.s b/gas/testsuite/gas/arc/lp.s
index 1913976..29b07ca 100644 (file)
--- a/gas/testsuite/gas/arc/lp.s
+++ b/gas/testsuite/gas/arc/lp.s
@@ -1,6 +1,4 @@
 # lp test
-       
-text_label:
 
        lp      text_label
        lpal    text_label
@@ -31,10 +29,5 @@ text_label:
        lpls    text_label
        lppnz   text_label
 
-       lp.d    text_label
-       lp.nd   text_label
-       lp.jd   text_label
-
-       lpeq.d  text_label
-       lpne.nd text_label
-       lpcc.jd text_label
+       nop_s
+text_label:

diff --git a/gas/testsuite/gas/arc/lsr.d b/gas/testsuite/gas/arc/lsr.d
index 27247a2..28ff4b9 100644 (file)
--- a/gas/testsuite/gas/arc/lsr.d
+++ b/gas/testsuite/gas/arc/lsr.d
@@ -1,51 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 18     18008400     lsr        r0,r1
-   4:  00 04 6e 1b     1b6e0400     lsr        fp,sp
-   8:  00 84 1f 18     181f8400     lsr        r0,0
-   c:  ff 85 3f 18     183f85ff     lsr        r1,-1
-  10:  00 04 e1 1f     1fe10400     lsr        0,r2
-  14:  00 84 e1 1f     1fe18400     lsr        0,r3
-  18:  ff 84 9f 18     189f84ff     lsr        r4,255
-  1c:  00 84 e2 1f     1fe28400     lsr        0,r5
-  20:  00 85 df 18     18df8500     lsr        r6,-256
-  24:  00 84 e3 1f     1fe38400     lsr        0,r7
-  28:  00 04 1f 19     191f0400     lsr        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 04 3f 19     193f0400     lsr        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 04 7f 19     197f0400     lsr        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 04 ff 1f     1fff0400     lsr        0,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 18     181f0400     lsr        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 84 45 19     19458401     lsr.z      r10,r11
-  54:  02 84 86 19     19868402     lsr.nz     r12,r13
-  58:  0b 04 df 19     19df040b     lsr.lt     r14,0
-  5c:  00 00 00 00 
-  60:  09 04 ff 19     19ff0409     lsr.gt     r15,0x200
-  64:  00 02 00 00 
-  68:  00 85 00 18     18008500     lsr.f      r0,r1
-  6c:  01 84 5e 18     185e8401     lsr.f      r2,1
-  70:  00 05 e2 1f     1fe20500     lsr.f      0,r4
-  74:  00 05 bf 18     18bf0500     lsr.f      r5,0x200
-  78:  00 02 00 00 
-  7c:  00 05 df 1f     1fdf0500     lsr.f      0,0x200
-  80:  00 02 00 00 
-  84:  01 85 00 18     18008501     lsr.z.f    r0,r1
-  88:  02 05 3f 18     183f0502     lsr.nz.f   r1,0
-  8c:  00 00 00 00 
-  90:  0b 05 c1 1f     1fc1050b     lsr.lt.f   0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 05 1f 18     181f050c     lsr.le.f   r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 05 df 1f     1fdf0504     lsr.n.f    0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 2901 0080                  lsr     r0,r1,r2
+0x[0-9a-f]+ 2b01 371a                  lsr     gp,fp,sp
+0x[0-9a-f]+ 2e01 37dd                  lsr     ilink,r30,blink
+0x[0-9a-f]+ 2941 0000                  lsr     r0,r1,0
+0x[0-9a-f]+ 2e01 7080 0000 0000        lsr     r0,0,r2
+0x[0-9a-f]+ 2901 00be                  lsr     0,r1,r2
+0x[0-9a-f]+ 2901 0f80 ffff ffff        lsr     r0,r1,0xffffffff
+0x[0-9a-f]+ 2e01 7080 ffff ffff        lsr     r0,0xffffffff,r2
+0x[0-9a-f]+ 2901 0f80 0000 00ff        lsr     r0,r1,0xff
+0x[0-9a-f]+ 2e01 7080 0000 00ff        lsr     r0,0xff,r2
+0x[0-9a-f]+ 2901 0f80 ffff ff00        lsr     r0,r1,0xffffff00
+0x[0-9a-f]+ 2e01 7080 ffff ff00        lsr     r0,0xffffff00,r2
+0x[0-9a-f]+ 2901 0f80 0000 0100        lsr     r0,r1,0x100
+0x[0-9a-f]+ 2e01 7080 ffff feff        lsr     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2e01 7f80 0000 0100        lsr     r0,0x100,0x100
+0x[0-9a-f]+ 2901 0f80 0000 0000        lsr     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 28c1 0080                  lsr     r0,r0,r2
+0x[0-9a-f]+ 2bc1 0140                  lsr     r3,r3,r5
+0x[0-9a-f]+ 2ec1 0201                  lsr.eq  r6,r6,r8
+0x[0-9a-f]+ 29c1 12c1                  lsr.eq  r9,r9,r11
+0x[0-9a-f]+ 2cc1 1382                  lsr.ne  r12,r12,r14
+0x[0-9a-f]+ 2fc1 1442                  lsr.ne  r15,r15,r17
+0x[0-9a-f]+ 2ac1 2503                  lsr.p   r18,r18,r20
+0x[0-9a-f]+ 2dc1 25c3                  lsr.p   r21,r21,r23
+0x[0-9a-f]+ 28c1 3684                  lsr.n   r24,r24,gp
+0x[0-9a-f]+ 2bc1 3744                  lsr.n   fp,fp,ilink
+0x[0-9a-f]+ 2ec1 37c5                  lsr.c   r30,r30,blink
+0x[0-9a-f]+ 2bc1 00c5                  lsr.c   r3,r3,r3
+0x[0-9a-f]+ 2bc1 0205                  lsr.c   r3,r3,r8
+0x[0-9a-f]+ 2bc1 0106                  lsr.nc  r3,r3,r4
+0x[0-9a-f]+ 2cc1 0106                  lsr.nc  r4,r4,r4
+0x[0-9a-f]+ 2cc1 01c6                  lsr.nc  r4,r4,r7
+0x[0-9a-f]+ 2cc1 0147                  lsr.v   r4,r4,r5
+0x[0-9a-f]+ 2dc1 0147                  lsr.v   r5,r5,r5
+0x[0-9a-f]+ 2dc1 0148                  lsr.nv  r5,r5,r5
+0x[0-9a-f]+ 2dc1 0148                  lsr.nv  r5,r5,r5
+0x[0-9a-f]+ 2ec1 0009                  lsr.gt  r6,r6,r0
+0x[0-9a-f]+ 28c1 002a                  lsr.ge  r0,r0,0
+0x[0-9a-f]+ 29c1 006b                  lsr.lt  r1,r1,0x1
+0x[0-9a-f]+ 2bc1 00ed                  lsr.hi  r3,r3,0x3
+0x[0-9a-f]+ 2cc1 012e                  lsr.ls  r4,r4,0x4
+0x[0-9a-f]+ 2dc1 016f                  lsr.pnz r5,r5,0x5
+0x[0-9a-f]+ 2901 8080                  lsr.f   r0,r1,r2
+0x[0-9a-f]+ 2941 8040                  lsr.f   r0,r1,0x1
+0x[0-9a-f]+ 2e01 f080 0000 0001        lsr.f   r0,0x1,r2
+0x[0-9a-f]+ 2901 80be                  lsr.f   0,r1,r2
+0x[0-9a-f]+ 2901 8f80 0000 0200        lsr.f   r0,r1,0x200
+0x[0-9a-f]+ 2e01 f080 0000 0200        lsr.f   r0,0x200,r2
+0x[0-9a-f]+ 29c1 8081                  lsr.f.eq        r1,r1,r2
+0x[0-9a-f]+ 28c1 8022                  lsr.f.ne        r0,r0,0
+0x[0-9a-f]+ 2ac1 808b                  lsr.f.lt        r2,r2,r2
+0x[0-9a-f]+ 2ec1 f0a9 0000 0001        lsr.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 2ec1 ff8c 0000 0200        lsr.f.le        0,0x200,0x200
+0x[0-9a-f]+ 2ec1 f0aa 0000 0200        lsr.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/lsr.s b/gas/testsuite/gas/arc/lsr.s
index 3f539d8..66f754d 100644 (file)
--- a/gas/testsuite/gas/arc/lsr.s
+++ b/gas/testsuite/gas/arc/lsr.s
@@ -1,38 +1,63 @@
 # lsr test
 
-       lsr r0,r1
-       lsr fp,sp
-
-       lsr r0,0
-       lsr r1,-1
-       lsr 0,r2
-       lsr -1,r3
-       lsr r4,255
-       lsr 255,r5
-       lsr r6,-256
-       lsr -256,r7
-
-       lsr r8,256
-       lsr r9,-257
-       lsr r11,0x42424242
-
-       lsr 255,256
-
-       lsr r0,foo
-
-       lsr.eq r10,r11
-       lsr.ne r12,r13
-       lsr.lt r14,0
-       lsr.gt r15,512
-
-       lsr.f r0,r1
-       lsr.f r2,1
-       lsr.f 0,r4
-       lsr.f r5,512
-       lsr.f 512,512
-
-       lsr.eq.f r0,r1
-       lsr.ne.f r1,0
-       lsr.lt.f 0,r2
-       lsr.le.f r0,512
-       lsr.n.f 512,512
+       lsr r0,r1,r2
+       lsr r26,fp,sp
+       lsr ilink1,ilink2,blink
+
+       lsr r0,r1,0
+       lsr r0,0,r2
+       lsr 0,r1,r2
+       lsr r0,r1,-1
+       lsr r0,-1,r2
+       lsr r0,r1,255
+       lsr r0,255,r2
+       lsr r0,r1,-256
+       lsr r0,-256,r2
+
+       lsr r0,r1,256
+       lsr r0,-257,r2
+
+       lsr r0,256,256
+
+       lsr r0,r1,foo
+
+       lsr.al r0,r0,r2
+       lsr.ra r3,r3,r5
+       lsr.eq r6,r6,r8
+       lsr.z  r9,r9,r11
+       lsr.ne r12,r12,r14
+       lsr.nz r15,r15,r17
+       lsr.pl r18,r18,r20
+       lsr.p  r21,r21,r23
+       lsr.mi r24,r24,r26
+       lsr.n  r27,r27,r29
+       lsr.cs r30,r30,r31
+       lsr.c  r3,r3,r3
+       lsr.lo r3,r3,r8
+       lsr.cc r3,r3,r4
+       lsr.nc r4,r4,r4
+       lsr.hs r4,r4,r7
+       lsr.vs r4,r4,r5
+       lsr.v  r5,r5,r5
+       lsr.vc r5,r5,r5
+       lsr.nv r5,r5,r5
+       lsr.gt r6,r6,r0
+       lsr.ge r0,r0,0
+       lsr.lt r1,r1,1
+       lsr.hi r3,r3,3
+       lsr.ls r4,r4,4
+       lsr.pnz r5,r5,5
+
+       lsr.f r0,r1,r2
+       lsr.f r0,r1,1
+       lsr.f r0,1,r2
+       lsr.f 0,r1,r2
+       lsr.f r0,r1,512
+       lsr.f r0,512,r2
+
+       lsr.eq.f r1,r1,r2
+       lsr.ne.f r0,r0,0
+       lsr.lt.f r2,r2,r2
+       lsr.gt.f 0,1,2
+       lsr.le.f 0,512,512
+       lsr.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/math.d b/gas/testsuite/gas/arc/math.d
deleted file mode 100644 (file)
index ccb79c5..0000000
--- a/gas/testsuite/gas/arc/math.d
+++ /dev/null
@@ -1,78 +0,0 @@
-#objdump: -dr
-#name: @OC@
-
-# Test the @OC@ insn.
-
-.*: +file format elf32-.*arc
-
-Disassembly of section .text:
-00000000 @IC+0@008400  @OC@ r0,r1,r2
-00000004 @IC+3@4db800  @OC@ r26,fp,sp
-00000008 @IC+3@af3e00  @OC@ ilink1,ilink2,blink
-0000000c @IC+7@5df800  @OC@ r58,r59,lp_count
-00000010 @IC+0@00fe00  @OC@ r0,r1,0
-00000014 @IC+0@1f8400  @OC@ r0,0,r2
-00000018 @IC+7@e08400  @OC@ 0,r1,r2
-0000001c @IC+0@00ffff  @OC@ r0,r1,-1
-00000020 @IC+0@1f85ff  @OC@ r0,-1,r2
-00000024 @IC+7@e085ff  @OC@ -1,r1,r2
-00000028 @IC+0@00feff  @OC@ r0,r1,255
-0000002c @IC+0@1f84ff  @OC@ r0,255,r2
-00000030 @IC+7@e084ff  @OC@ 255,r1,r2
-00000034 @IC+0@00ff00  @OC@ r0,r1,-256
-00000038 @IC+0@1f8500  @OC@ r0,-256,r2
-0000003c @IC+7@e08500  @OC@ -256,r1,r2
-00000040 @IC+0@00fc00  @OC@ r0,r1,256
-00000048 @IC+0@1f0400  @OC@ r0,-257,r2
-00000050 @IC+7@c08400  @OC@ 511,r1,r2
-00000058 @IC+0@1f0400  @OC@ r0,1111638594,r2
-00000060 @IC+7@c0fc00  @OC@ 305419896,r1,305419896
-00000068 @IC+0@1ffcff  @OC@ r0,255,256
-00000070 @IC+0@1f7eff  @OC@ r0,256,255
-00000078 @IC+7@e0fcff  @OC@ 255,r1,256
-00000080 @IC+7@ff04ff  @OC@ 255,256,r2
-00000088 @IC+7@c0feff  @OC@ 256,r1,255
-00000090 @IC+7@df84ff  @OC@ 256,255,r2
-00000098 @IC+0@00fc00  @OC@ r0,r1,0
-               RELOC: 0000009c R_ARC_32 foo
-000000a0 @IC+0@008400  @OC@ r0,r1,r2
-000000a4 @IC+0@620a00  @OC@ r3,r4,r5
-000000a8 @IC+0@c39001  @OC@.eq r6,r7,r8
-000000ac @IC+1@251601  @OC@.eq r9,r10,r11
-000000b0 @IC+1@869c02  @OC@.ne r12,r13,r14
-000000b4 @IC+1@e82202  @OC@.ne r15,r16,r17
-000000b8 @IC+2@49a803  @OC@.p r18,r19,r20
-000000bc @IC+2@ab2e03  @OC@.p r21,r22,r23
-000000c0 @IC+3@0cb404  @OC@.n r24,r25,r26
-000000c4 @IC+3@6e3a04  @OC@.n fp,sp,ilink1
-000000c8 @IC+3@cfc005  @OC@.c ilink2,blink,r32
-000000cc @IC+4@314605  @OC@.c r33,r34,r35
-000000d0 @IC+4@92cc05  @OC@.c r36,r37,r38
-000000d4 @IC+4@f45206  @OC@.nc r39,r40,r41
-000000d8 @IC+5@55d806  @OC@.nc r42,r43,r44
-000000dc @IC+5@b75e06  @OC@.nc r45,r46,r47
-000000e0 @IC+6@18e407  @OC@.v r48,r49,r50
-000000e4 @IC+6@7a6a07  @OC@.v r51,r52,r53
-000000e8 @IC+6@dbf008  @OC@.nv r54,r55,r56
-000000ec @IC+7@3d7608  @OC@.nv r57,r58,r59
-000000f0 @IC+7@9e0009  @OC@.gt lp_count,lp_count,r0
-000000f4 @IC+0@007c0a  @OC@.ge r0,r0,0
-000000fc @IC+0@3f020b  @OC@.lt r1,1,r1
-00000104 @IC+7@c0840c  @OC@.le 2,r1,r2
-0000010c @IC+0@7f060d  @OC@.hi r3,3,r3
-00000114 @IC+7@df080e  @OC@.ls 4,4,r4
-0000011c @IC+7@c2fc0f  @OC@.pnz 5,r5,5
-00000124 @IC+0@008500  @OC@.f r0,r1,r2
-00000128 @IC+0@00fa01  @OC@.f r0,r1,1
-0000012c @IC+0@1e8401  @OC@.f r0,1,r2
-00000130 @IC+7@a08400  @OC@.f 0,r1,r2
-00000134 @IC+0@00fd00  @OC@.f r0,r1,512
-0000013c @IC+0@1f0500  @OC@.f r0,512,r2
-00000144 @IC+7@c08500  @OC@.f 512,r1,r2
-0000014c @IC+0@008501  @OC@.eq.f r0,r1,r2
-00000150 @IC+0@00fd02  @OC@.ne.f r0,r1,0
-00000158 @IC+0@1f050b  @OC@.lt.f r0,0,r2
-00000160 @IC+7@c08509  @OC@.gt.f 0,r1,r2
-00000168 @IC+0@00fd0c  @OC@.le.f r0,r1,512
-00000170 @IC+0@1f050a  @OC@.ge.f r0,512,r2
-00000178 @IC+7@c08504  @OC@.n.f 512,r1,r2

diff --git a/gas/testsuite/gas/arc/math.s b/gas/testsuite/gas/arc/math.s
deleted file mode 100644 (file)
index 775169a..0000000
--- a/gas/testsuite/gas/arc/math.s
+++ /dev/null
@@ -1,89 +0,0 @@
-# @OC@ test
-
-# Stay away from operands with duplicate arguments (eg:        add r0,r1,r1).
-# They will be disassembled as they're macro counterparts (eg: asl r0,r1).
-
-# reg,reg,reg
-       @OC@ r0,r1,r2
-       @OC@ r26,fp,sp
-       @OC@ ilink1,ilink2,blink
-       @OC@ r58,r59,lp_count
-
-# shimm values
-       @OC@ r0,r1,0
-       @OC@ r0,0,r2
-       @OC@ 0,r1,r2
-       @OC@ r0,r1,-1
-       @OC@ r0,-1,r2
-       @OC@ -1,r1,r2
-       @OC@ r0,r1,255
-       @OC@ r0,255,r2
-       @OC@ 255,r1,r2
-       @OC@ r0,r1,-256
-       @OC@ r0,-256,r2
-       @OC@ -256,r1,r2
-
-# limm values
-       @OC@ r0,r1,256
-       @OC@ r0,-257,r2
-       @OC@ 511,r1,r2
-       @OC@ r0,0x42424242,r2
-       @OC@ 0x12345678,r1,0x12345678
-
-# shimm and limm
-       @OC@ r0,255,256
-       @OC@ r0,256,255
-       @OC@ 255,r1,256
-       @OC@ 255,256,r2
-       @OC@ 256,r1,255
-       @OC@ 256,255,r2
-
-# symbols
-       @OC@ r0,r1,foo
-
-# conditional execution
-       @OC@.al r0,r1,r2
-       @OC@.ra r3,r4,r5
-       @OC@.eq r6,r7,r8
-       @OC@.z r9,r10,r11
-       @OC@.ne r12,r13,r14
-       @OC@.nz r15,r16,r17
-       @OC@.pl r18,r19,r20
-       @OC@.p r21,r22,r23
-       @OC@.mi r24,r25,r26
-       @OC@.n r27,r28,r29
-       @OC@.cs r30,r31,r32
-       @OC@.c r33,r34,r35
-       @OC@.lo r36,r37,r38
-       @OC@.cc r39,r40,r41
-       @OC@.nc r42,r43,r44
-       @OC@.hs r45,r46,r47
-       @OC@.vs r48,r49,r50
-       @OC@.v r51,r52,r53
-       @OC@.vc r54,r55,r56
-       @OC@.nv r57,r58,r59
-       @OC@.gt r60,r60,r0
-       @OC@.ge r0,r0,0
-       @OC@.lt r1,1,r1
-       @OC@.le 2,r1,r2
-       @OC@.hi r3,3,r3
-       @OC@.ls 4,4,r4
-       @OC@.pnz 5,r5,5
-
-# flag setting
-       @OC@.f r0,r1,r2
-       @OC@.f r0,r1,1
-       @OC@.f r0,1,r2
-       @OC@.f 0,r1,r2
-       @OC@.f r0,r1,512
-       @OC@.f r0,512,r2
-       @OC@.f 512,r1,r2
-
-# conditional execution + flag setting
-       @OC@.eq.f r0,r1,r2
-       @OC@.ne.f r0,r1,0
-       @OC@.lt.f r0,0,r2
-       @OC@.gt.f 0,r1,r2
-       @OC@.le.f r0,r1,512
-       @OC@.ge.f r0,512,r2
-       @OC@.n.f 512,r1,r2

diff --git a/gas/testsuite/gas/arc/mov.d b/gas/testsuite/gas/arc/mov.d
index cff11d7..6ce6c55 100644 (file)
--- a/gas/testsuite/gas/arc/mov.d
+++ b/gas/testsuite/gas/arc/mov.d
@@ -1,68 +1,56 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 82 00 60     60008200     mov        r0,r1
-   4:  00 38 6e 63     636e3800     mov        fp,sp
-   8:  00 fe 1f 60     601ffe00     mov        r0,0
-   c:  ff ff 3f 60     603fffff     mov        r1,-1
-  10:  00 04 e1 67     67e10400     mov        0,r2
-  14:  00 86 e1 67     67e18600     mov        0,r3
-  18:  ff fe 9f 60     609ffeff     mov        r4,255
-  1c:  00 8a e2 67     67e28a00     mov        0,r5
-  20:  00 ff df 60     60dfff00     mov        r6,-256
-  24:  00 8e e3 67     67e38e00     mov        0,r7
-  28:  00 7c 1f 61     611f7c00     mov        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 7c 3f 61     613f7c00     mov        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 7c 7f 61     617f7c00     mov        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 7c ff 67     67ff7c00     mov        0,0x100
-  44:  00 01 00 00 
-  48:  00 7c 1f 60     601f7c00     mov        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  00 82 00 60     60008200     mov        r0,r1
-  54:  00 08 62 60     60620800     mov        r3,r4
-  58:  01 8e c3 60     60c38e01     mov.z      r6,r7
-  5c:  01 14 25 61     61251401     mov.z      r9,r10
-  60:  02 9a 86 61     61869a02     mov.nz     r12,r13
-  64:  02 20 e8 61     61e82002     mov.nz     r15,r16
-  68:  03 a6 49 62     6249a603     mov.p      r18,r19
-  6c:  03 2c ab 62     62ab2c03     mov.p      r21,r22
-  70:  04 b2 0c 63     630cb204     mov.n      r24,r25
-  74:  04 38 6e 63     636e3804     mov.n      fp,sp
-  78:  05 be cf 63     63cfbe05     mov.c      ilink2,blink
-  7c:  05 44 31 64     64314405     mov.c      r33,r34
-  80:  05 ca 92 64     6492ca05     mov.c      r36,r37
-  84:  06 50 f4 64     64f45006     mov.nc     r39,r40
-  88:  06 d6 55 65     6555d606     mov.nc     r42,r43
-  8c:  06 5c b7 65     65b75c06     mov.nc     r45,r46
-  90:  07 e2 18 66     6618e207     mov.v      r48,r49
-  94:  07 64 39 66     66396407     mov.v      r49,r50
-  98:  08 ee 3b 66     663bee08     mov.nv     r49,r55
-  9c:  08 74 3d 66     663d7408     mov.nv     r49,r58
-  a0:  09 78 9e 67     679e7809     mov.gt     lp_count,lp_count
-  a4:  0a 7c 1f 60     601f7c0a     mov.ge     r0,0
-  a8:  00 00 00 00 
-  ac:  0c 7c df 67     67df7c0c     mov.le     0,2
-  b0:  02 00 00 00 
-  b4:  0d 86 61 60     6061860d     mov.hi     r3,r3
-  b8:  0e 08 82 60     6082080e     mov.ls     r4,r4
-  bc:  0f 8a a2 60     60a28a0f     mov.pnz    r5,r5
-  c0:  00 83 00 60     60008300     mov.f      r0,r1
-  c4:  01 fa 5e 60     605efa01     mov.f      r2,1
-  c8:  00 87 e1 67     67e18700     mov.f      0,r3
-  cc:  00 09 e2 67     67e20900     mov.f      0,r4
-  d0:  00 7d bf 60     60bf7d00     mov.f      r5,0x200
-  d4:  00 02 00 00 
-  d8:  00 7d df 67     67df7d00     mov.f      0,0x200
-  dc:  00 02 00 00 
-  e0:  01 83 00 60     60008301     mov.z.f    r0,r1
-  e4:  02 7d 3f 60     603f7d02     mov.nz.f   r1,0
-  e8:  00 00 00 00 
+0x[0-9a-f]+ 200a 0040                  mov     r0,r1
+0x[0-9a-f]+ 230a 3700                  mov     fp,sp
+0x[0-9a-f]+ 204a 0000                  mov     r0,0
+0x[0-9a-f]+ 218a 0fff                  mov     r1,-1
+0x[0-9a-f]+ 260a 7080                  mov     0,r2
+0x[0-9a-f]+ 248a 0fc3                  mov     r4,255
+0x[0-9a-f]+ 268a 7fc3                  mov     0,255
+0x[0-9a-f]+ 268a 003c                  mov     r6,-256
+0x[0-9a-f]+ 230a 1f80 4242 4242        mov     r11,0x42424242
+0x[0-9a-f]+ 260a 7f80 1234 5678        mov     0,0x12345678
+0x[0-9a-f]+ 200a 0f80 0000 0000        mov     r0,0
+                       34: ARC_32_ME   foo
+0x[0-9a-f]+ 20ca 0040                  mov     r0,r1
+0x[0-9a-f]+ 23ca 0100                  mov     r3,r4
+0x[0-9a-f]+ 26ca 01c1                  mov.eq  r6,r7
+0x[0-9a-f]+ 21ca 1281                  mov.eq  r9,r10
+0x[0-9a-f]+ 24ca 1342                  mov.ne  r12,r13
+0x[0-9a-f]+ 27ca 1402                  mov.ne  r15,r16
+0x[0-9a-f]+ 22ca 24c3                  mov.p   r18,r19
+0x[0-9a-f]+ 25ca 2583                  mov.p   r21,r22
+0x[0-9a-f]+ 20ca 3644                  mov.n   r24,r25
+0x[0-9a-f]+ 23ca 3704                  mov.n   fp,sp
+0x[0-9a-f]+ 20ca 0045                  mov.c   r0,r1
+0x[0-9a-f]+ 23ca 0105                  mov.c   r3,r4
+0x[0-9a-f]+ 26ca 01c5                  mov.c   r6,r7
+0x[0-9a-f]+ 21ca 1006                  mov.nc  r9,r0
+0x[0-9a-f]+ 22ca 00c6                  mov.nc  r2,r3
+0x[0-9a-f]+ 25ca 0186                  mov.nc  r5,r6
+0x[0-9a-f]+ 20ca 1247                  mov.v   r8,r9
+0x[0-9a-f]+ 21ca 0087                  mov.v   r1,r2
+0x[0-9a-f]+ 24ca 0148                  mov.nv  r4,r5
+0x[0-9a-f]+ 27ca 0208                  mov.nv  r7,r8
+0x[0-9a-f]+ 20ca 0009                  mov.gt  r0,r0
+0x[0-9a-f]+ 20ca 002a                  mov.ge  r0,0
+0x[0-9a-f]+ 26ca 704b                  mov.lt  0,r1
+0x[0-9a-f]+ 26ca 70ac                  mov.le  0,0x2
+0x[0-9a-f]+ 23ca 00cd                  mov.hi  r3,r3
+0x[0-9a-f]+ 24ca 010e                  mov.ls  r4,r4
+0x[0-9a-f]+ 25ca 014f                  mov.pnz r5,r5
+0x[0-9a-f]+ 200a 8040                  mov.f   r0,r1
+0x[0-9a-f]+ 224a 8040                  mov.f   r2,0x1
+0x[0-9a-f]+ 260a f100                  mov.f   0,r4
+0x[0-9a-f]+ 258a 8008                  mov.f   r5,512
+0x[0-9a-f]+ 20ca 8041                  mov.f.eq        r0,r1
+0x[0-9a-f]+ 21ca 8022                  mov.f.ne        r1,0
+0x[0-9a-f]+ 26ca f08b                  mov.f.lt        0,r2
+0x[0-9a-f]+ 26ca f089                  mov.f.gt        0,r2
+0x[0-9a-f]+ 20ca 8f8c 0000 0200        mov.f.le        r0,0x200
+0x[0-9a-f]+ 26ca f08a                  mov.f.ge        0,r2
+0x[0-9a-f]+ 26ca ff84 0000 0200        mov.f.n 0,0x200

diff --git a/gas/testsuite/gas/arc/mov.s b/gas/testsuite/gas/arc/mov.s
index fdee0b7..676bcfa 100644 (file)
--- a/gas/testsuite/gas/arc/mov.s
+++ b/gas/testsuite/gas/arc/mov.s
@@ -1,58 +1,64 @@
 # mov test
 
+# reg,reg
        mov r0,r1
        mov fp,sp
 
+# shimm values
        mov r0,0
        mov r1,-1
        mov 0,r2
-       mov -1,r3
        mov r4,255
-       mov 255,r5
+       mov 0,255
        mov r6,-256
-       mov -256,r7
 
-       mov r8,256
-       mov r9,-257
+# limm values
        mov r11,0x42424242
+       mov 0, 0x12345678
 
-       mov 255,256
-
-       mov r0,foo
+# symbols
+       mov r0,@foo
 
+# conditional execution
        mov.al r0,r1
        mov.ra r3,r4
        mov.eq r6,r7
-       mov.z r9,r10
+       mov.z  r9,r10
        mov.ne r12,r13
        mov.nz r15,r16
        mov.pl r18,r19
-       mov.p r21,r22
+       mov.p  r21,r22
        mov.mi r24,r25
-       mov.n r27,r28
-       mov.cs r30,r31
-       mov.c r33,r34
-       mov.lo r36,r37
-       mov.cc r39,r40
-       mov.nc r42,r43
-       mov.hs r45,r46
-       mov.vs r48,r49
-       mov.v r49,r50
-       mov.vc r49,r55
-       mov.nv r49,r58
-       mov.gt r60,r60
+       mov.n  r27,r28
+       mov.cs r0,r1
+       mov.c  r3,r4
+       mov.lo r6,r7
+       mov.cc r9,r0
+       mov.nc r2,r3
+       mov.hs r5,r6
+       mov.vs r8,r9
+       mov.v  r1,r2
+       mov.vc r4,r5
+       mov.nv r7,r8
+       mov.gt r0,r0
        mov.ge r0,0
-       mov.le 2,2
+       mov.lt 0,r1
+       mov.le 0,2
        mov.hi r3,r3
        mov.ls r4,r4
        mov.pnz r5,r5
 
+# flag setting
        mov.f r0,r1
        mov.f r2,1
-       mov.f 1,r3
        mov.f 0,r4
        mov.f r5,512
-       mov.f 512,512
 
+# conditional execution + flag setting
        mov.eq.f r0,r1
        mov.ne.f r1,0
+       mov.lt.f 0,r2
+       mov.gt.f 0,r2
+       mov.le.f r0,512
+       mov.ge.f 0,r2
+       mov.n.f  0,512

diff --git a/gas/testsuite/gas/arc/nop.d b/gas/testsuite/gas/arc/nop.d
index 1a714cd..32e0375 100644 (file)
--- a/gas/testsuite/gas/arc/nop.d
+++ b/gas/testsuite/gas/arc/nop.d
@@ -1,9 +1,7 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  ff ff ff 7f     7fffffff     nop        
+0x00000000 78e0                        nop_s

diff --git a/gas/testsuite/gas/arc/nop.s b/gas/testsuite/gas/arc/nop.s
index 02b2681..615694a 100644 (file)
--- a/gas/testsuite/gas/arc/nop.s
+++ b/gas/testsuite/gas/arc/nop.s
@@ -1,3 +1,3 @@
 # nop test
 
-       nop
+       nop_s

diff --git a/gas/testsuite/gas/arc/or.d b/gas/testsuite/gas/arc/or.d
index 11e6f3c..33232d5 100644 (file)
--- a/gas/testsuite/gas/arc/or.d
+++ b/gas/testsuite/gas/arc/or.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 68     68008400     or         r0,r1,r2
-   4:  00 b8 4d 6b     6b4db800     or         gp,fp,sp
-   8:  00 3e af 6b     6baf3e00     or         ilink1,ilink2,blink
-   c:  00 f8 1d 6f     6f1df800     or         r56,r59,lp_count
-  10:  00 fe 00 68     6800fe00     or         r0,r1,0
-  14:  00 84 1f 68     681f8400     or         r0,0,r2
-  18:  00 84 e0 6f     6fe08400     or         0,r1,r2
-  1c:  ff ff 00 68     6800ffff     or         r0,r1,-1
-  20:  ff 85 1f 68     681f85ff     or         r0,-1,r2
-  24:  00 84 e0 6f     6fe08400     or         0,r1,r2
-  28:  ff fe 00 68     6800feff     or         r0,r1,255
-  2c:  ff 84 1f 68     681f84ff     or         r0,255,r2
-  30:  00 84 e0 6f     6fe08400     or         0,r1,r2
-  34:  00 ff 00 68     6800ff00     or         r0,r1,-256
-  38:  00 85 1f 68     681f8500     or         r0,-256,r2
-  3c:  00 84 e0 6f     6fe08400     or         0,r1,r2
-  40:  00 fc 00 68     6800fc00     or         r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 68     681f0400     or         r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 68     681ffcff     or         r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 68     681f7eff     or         r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 68     6800fc00     or         r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 68     68008400     or         r0,r1,r2
-  6c:  00 0a 62 68     68620a00     or         r3,r4,r5
-  70:  01 90 c3 68     68c39001     or.z       r6,r7,r8
-  74:  01 16 25 69     69251601     or.z       r9,r10,r11
-  78:  02 9c 86 69     69869c02     or.nz      r12,r13,r14
-  7c:  02 22 e8 69     69e82202     or.nz      r15,r16,r17
-  80:  03 a8 49 6a     6a49a803     or.p       r18,r19,r20
-  84:  03 2e ab 6a     6aab2e03     or.p       r21,r22,r23
-  88:  04 b4 0c 6b     6b0cb404     or.n       r24,r25,gp
-  8c:  04 3a 6e 6b     6b6e3a04     or.n       fp,sp,ilink1
-  90:  05 c0 cf 6b     6bcfc005     or.c       ilink2,blink,r32
-  94:  05 46 31 6c     6c314605     or.c       r33,r34,r35
-  98:  05 cc 92 6c     6c92cc05     or.c       r36,r37,r38
-  9c:  06 52 f4 6c     6cf45206     or.nc      r39,r40,r41
-  a0:  06 d8 55 6d     6d55d806     or.nc      r42,r43,r44
-  a4:  06 5e b7 6d     6db75e06     or.nc      r45,r46,r47
-  a8:  07 e4 18 6e     6e18e407     or.v       r48,r49,r50
-  ac:  07 6a 1a 6f     6f1a6a07     or.v       r56,r52,r53
-  b0:  08 f0 1b 6f     6f1bf008     or.nv      r56,r55,r56
-  b4:  08 76 1d 6f     6f1d7608     or.nv      r56,r58,r59
-  b8:  09 00 9e 6f     6f9e0009     or.gt      lp_count,lp_count,r0
-  bc:  0a 7c 00 68     68007c0a     or.ge      r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 68     683f020b     or.lt      r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 68     687f060d     or.hi      r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 6f     6fdf080e     or.ls      0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 6f     6fc2fc0f     or.pnz     0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 68     68008500     or.f       r0,r1,r2
-  e8:  01 fa 00 68     6800fa01     or.f       r0,r1,1
-  ec:  01 84 1e 68     681e8401     or.f       r0,1,r2
-  f0:  00 85 e0 6f     6fe08500     or.f       0,r1,r2
-  f4:  00 fd 00 68     6800fd00     or.f       r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 68     681f0500     or.f       r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 68     68008501     or.z.f     r0,r1,r2
- 108:  02 fd 00 68     6800fd02     or.nz.f    r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 68     681f050b     or.lt.f    r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 6f     6fc08509     or.gt.f    0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 68     6800fd0c     or.le.f    r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 68     681f050a     or.ge.f    r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2105 0080                  or      r0,r1,r2
+0x[0-9a-f]+ 2305 371a                  or      gp,fp,sp
+0x[0-9a-f]+ 2605 37dd                  or      ilink,r30,blink
+0x[0-9a-f]+ 2145 0000                  or      r0,r1,0
+0x[0-9a-f]+ 2605 7080 0000 0000        or      r0,0,r2
+0x[0-9a-f]+ 2105 00be                  or      0,r1,r2
+0x[0-9a-f]+ 2105 0f80 ffff ffff        or      r0,r1,0xffffffff
+0x[0-9a-f]+ 2605 7080 ffff ffff        or      r0,0xffffffff,r2
+0x[0-9a-f]+ 2105 0f80 0000 00ff        or      r0,r1,0xff
+0x[0-9a-f]+ 2605 7080 0000 00ff        or      r0,0xff,r2
+0x[0-9a-f]+ 2105 0f80 ffff ff00        or      r0,r1,0xffffff00
+0x[0-9a-f]+ 2605 7080 ffff ff00        or      r0,0xffffff00,r2
+0x[0-9a-f]+ 2105 0f80 0000 0100        or      r0,r1,0x100
+0x[0-9a-f]+ 2605 7080 ffff feff        or      r0,0xfffffeff,r2
+0x[0-9a-f]+ 2605 7f80 0000 0100        or      r0,0x100,0x100
+0x[0-9a-f]+ 2105 0f80 0000 0000        or      r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c5 0080                  or      r0,r0,r2
+0x[0-9a-f]+ 23c5 0140                  or      r3,r3,r5
+0x[0-9a-f]+ 26c5 0201                  or.eq   r6,r6,r8
+0x[0-9a-f]+ 21c5 12c1                  or.eq   r9,r9,r11
+0x[0-9a-f]+ 24c5 1382                  or.ne   r12,r12,r14
+0x[0-9a-f]+ 27c5 1442                  or.ne   r15,r15,r17
+0x[0-9a-f]+ 22c5 2503                  or.p    r18,r18,r20
+0x[0-9a-f]+ 25c5 25c3                  or.p    r21,r21,r23
+0x[0-9a-f]+ 20c5 3684                  or.n    r24,r24,gp
+0x[0-9a-f]+ 23c5 3744                  or.n    fp,fp,ilink
+0x[0-9a-f]+ 26c5 37c5                  or.c    r30,r30,blink
+0x[0-9a-f]+ 23c5 00c5                  or.c    r3,r3,r3
+0x[0-9a-f]+ 23c5 0205                  or.c    r3,r3,r8
+0x[0-9a-f]+ 23c5 0106                  or.nc   r3,r3,r4
+0x[0-9a-f]+ 24c5 0106                  or.nc   r4,r4,r4
+0x[0-9a-f]+ 24c5 01c6                  or.nc   r4,r4,r7
+0x[0-9a-f]+ 24c5 0147                  or.v    r4,r4,r5
+0x[0-9a-f]+ 25c5 0147                  or.v    r5,r5,r5
+0x[0-9a-f]+ 25c5 0148                  or.nv   r5,r5,r5
+0x[0-9a-f]+ 25c5 0148                  or.nv   r5,r5,r5
+0x[0-9a-f]+ 26c5 0009                  or.gt   r6,r6,r0
+0x[0-9a-f]+ 20c5 002a                  or.ge   r0,r0,0
+0x[0-9a-f]+ 21c5 006b                  or.lt   r1,r1,0x1
+0x[0-9a-f]+ 23c5 00ed                  or.hi   r3,r3,0x3
+0x[0-9a-f]+ 24c5 012e                  or.ls   r4,r4,0x4
+0x[0-9a-f]+ 25c5 016f                  or.pnz  r5,r5,0x5
+0x[0-9a-f]+ 2105 8080                  or.f    r0,r1,r2
+0x[0-9a-f]+ 2145 8040                  or.f    r0,r1,0x1
+0x[0-9a-f]+ 2605 f080 0000 0001        or.f    r0,0x1,r2
+0x[0-9a-f]+ 2105 80be                  or.f    0,r1,r2
+0x[0-9a-f]+ 2105 8f80 0000 0200        or.f    r0,r1,0x200
+0x[0-9a-f]+ 2605 f080 0000 0200        or.f    r0,0x200,r2
+0x[0-9a-f]+ 21c5 8081                  or.f.eq r1,r1,r2
+0x[0-9a-f]+ 20c5 8022                  or.f.ne r0,r0,0
+0x[0-9a-f]+ 22c5 808b                  or.f.lt r2,r2,r2
+0x[0-9a-f]+ 26c5 f0a9 0000 0001        or.f.gt 0,0x1,0x2
+0x[0-9a-f]+ 26c5 ff8c 0000 0200        or.f.le 0,0x200,0x200
+0x[0-9a-f]+ 26c5 f0aa 0000 0200        or.f.ge 0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/or.s b/gas/testsuite/gas/arc/or.s
index e363352..337e3aa 100644 (file)
--- a/gas/testsuite/gas/arc/or.s
+++ b/gas/testsuite/gas/arc/or.s
@@ -3,55 +3,50 @@
        or r0,r1,r2
        or r26,fp,sp
        or ilink1,ilink2,blink
-       or r56,r59,lp_count
 
        or r0,r1,0
        or r0,0,r2
        or 0,r1,r2
        or r0,r1,-1
        or r0,-1,r2
-       or -1,r1,r2
        or r0,r1,255
        or r0,255,r2
-       or 255,r1,r2
        or r0,r1,-256
        or r0,-256,r2
-       or -256,r1,r2
 
        or r0,r1,256
        or r0,-257,r2
 
-       or r0,255,256
-       or r0,256,255
+       or r0,256,256
 
        or r0,r1,foo
 
-       or.al r0,r1,r2
-       or.ra r3,r4,r5
-       or.eq r6,r7,r8
-       or.z r9,r10,r11
-       or.ne r12,r13,r14
-       or.nz r15,r16,r17
-       or.pl r18,r19,r20
-       or.p r21,r22,r23
-       or.mi r24,r25,r26
-       or.n r27,r28,r29
-       or.cs r30,r31,r32
-       or.c r33,r34,r35
-       or.lo r36,r37,r38
-       or.cc r39,r40,r41
-       or.nc r42,r43,r44
-       or.hs r45,r46,r47
-       or.vs r48,r49,r50
-       or.v r56,r52,r53
-       or.vc r56,r55,r56
-       or.nv r56,r58,r59
-       or.gt r60,r60,r0
+       or.al r0,r0,r2
+       or.ra r3,r3,r5
+       or.eq r6,r6,r8
+       or.z  r9,r9,r11
+       or.ne r12,r12,r14
+       or.nz r15,r15,r17
+       or.pl r18,r18,r20
+       or.p  r21,r21,r23
+       or.mi r24,r24,r26
+       or.n  r27,r27,r29
+       or.cs r30,r30,r31
+       or.c  r3,r3,r3
+       or.lo r3,r3,r8
+       or.cc r3,r3,r4
+       or.nc r4,r4,r4
+       or.hs r4,r4,r7
+       or.vs r4,r4,r5
+       or.v  r5,r5,r5
+       or.vc r5,r5,r5
+       or.nv r5,r5,r5
+       or.gt r6,r6,r0
        or.ge r0,r0,0
-       or.lt r1,1,r1
-       or.hi r3,3,r3
-       or.ls 4,4,r4
-       or.pnz 5,r5,5
+       or.lt r1,r1,1
+       or.hi r3,r3,3
+       or.ls r4,r4,4
+       or.pnz r5,r5,5
 
        or.f r0,r1,r2
        or.f r0,r1,1
@@ -60,9 +55,9 @@
        or.f r0,r1,512
        or.f r0,512,r2
 
-       or.eq.f r0,r1,r2
-       or.ne.f r0,r1,0
-       or.lt.f r0,0,r2
-       or.gt.f 0,r1,r2
-       or.le.f r0,r1,512
-       or.ge.f r0,512,r2
+       or.eq.f r1,r1,r2
+       or.ne.f r0,r0,0
+       or.lt.f r2,r2,r2
+       or.gt.f 0,1,2
+       or.le.f 0,512,512
+       or.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/rlc.d b/gas/testsuite/gas/arc/rlc.d
index e83ddc4..f9d42b3 100644 (file)
--- a/gas/testsuite/gas/arc/rlc.d
+++ b/gas/testsuite/gas/arc/rlc.d
@@ -1,68 +1,22 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 82 00 48     48008200     rlc        r0,r1
-   4:  00 38 6e 4b     4b6e3800     rlc        fp,sp
-   8:  00 fe 1f 48     481ffe00     rlc        r0,0
-   c:  ff ff 3f 48     483fffff     rlc        r1,-1
-  10:  00 04 e1 4f     4fe10400     rlc        0,r2
-  14:  00 86 e1 4f     4fe18600     rlc        0,r3
-  18:  ff fe 9f 48     489ffeff     rlc        r4,255
-  1c:  00 8a e2 4f     4fe28a00     rlc        0,r5
-  20:  00 ff df 48     48dfff00     rlc        r6,-256
-  24:  00 8e e3 4f     4fe38e00     rlc        0,r7
-  28:  00 7c 1f 49     491f7c00     rlc        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 7c 3f 49     493f7c00     rlc        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 7c 7f 49     497f7c00     rlc        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 7c ff 4f     4fff7c00     rlc        0,0x100
-  44:  00 01 00 00 
-  48:  00 7c 1f 48     481f7c00     rlc        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  00 82 00 48     48008200     rlc        r0,r1
-  54:  00 08 62 48     48620800     rlc        r3,r4
-  58:  01 8e c3 48     48c38e01     rlc.z      r6,r7
-  5c:  01 14 25 49     49251401     rlc.z      r9,r10
-  60:  02 9a 86 49     49869a02     rlc.nz     r12,r13
-  64:  02 20 e8 49     49e82002     rlc.nz     r15,r16
-  68:  03 a6 49 4a     4a49a603     rlc.p      r18,r19
-  6c:  03 2c ab 4a     4aab2c03     rlc.p      r21,r22
-  70:  04 b2 0c 4b     4b0cb204     rlc.n      r24,r25
-  74:  04 38 6e 4b     4b6e3804     rlc.n      fp,sp
-  78:  05 be cf 4b     4bcfbe05     rlc.c      ilink2,blink
-  7c:  05 44 31 4c     4c314405     rlc.c      r33,r34
-  80:  05 ca 92 4c     4c92ca05     rlc.c      r36,r37
-  84:  06 50 f4 4c     4cf45006     rlc.nc     r39,r40
-  88:  06 d6 55 4d     4d55d606     rlc.nc     r42,r43
-  8c:  06 5c b7 4d     4db75c06     rlc.nc     r45,r46
-  90:  07 e2 18 4e     4e18e207     rlc.v      r48,r49
-  94:  07 64 39 4e     4e396407     rlc.v      r49,r50
-  98:  08 ee 3b 4e     4e3bee08     rlc.nv     r49,r55
-  9c:  08 74 3d 4e     4e3d7408     rlc.nv     r49,r58
-  a0:  09 78 9e 4f     4f9e7809     rlc.gt     lp_count,lp_count
-  a4:  0a 7c 1f 48     481f7c0a     rlc.ge     r0,0
-  a8:  00 00 00 00 
-  ac:  0c 7c df 4f     4fdf7c0c     rlc.le     0,2
-  b0:  02 00 00 00 
-  b4:  0d 86 61 48     4861860d     rlc.hi     r3,r3
-  b8:  0e 08 82 48     4882080e     rlc.ls     r4,r4
-  bc:  0f 8a a2 48     48a28a0f     rlc.pnz    r5,r5
-  c0:  00 83 00 48     48008300     rlc.f      r0,r1
-  c4:  01 fa 5e 48     485efa01     rlc.f      r2,1
-  c8:  00 87 e1 4f     4fe18700     rlc.f      0,r3
-  cc:  00 09 e2 4f     4fe20900     rlc.f      0,r4
-  d0:  00 7d bf 48     48bf7d00     rlc.f      r5,0x200
-  d4:  00 02 00 00 
-  d8:  00 7d df 4f     4fdf7d00     rlc.f      0,0x200
-  dc:  00 02 00 00 
-  e0:  01 83 00 48     48008301     rlc.z.f    r0,r1
-  e4:  02 7d 3f 48     483f7d02     rlc.nz.f   r1,0
-  e8:  00 00 00 00 
+0x[0-9a-f]+ 202f 004b                  rlc     r0,r1
+0x[0-9a-f]+ 232f 370b                  rlc     fp,sp
+0x[0-9a-f]+ 206f 000b                  rlc     r0,0
+0x[0-9a-f]+ 212f 0f8b ffff ffff        rlc     r1,0xffffffff
+0x[0-9a-f]+ 262f 708b                  rlc     0,r2
+0x[0-9a-f]+ 242f 0f8b 0000 00ff        rlc     r4,0xff
+0x[0-9a-f]+ 262f 0f8b ffff ff00        rlc     r6,0xffffff00
+0x[0-9a-f]+ 202f 1f8b 0000 0100        rlc     r8,0x100
+0x[0-9a-f]+ 212f 1f8b ffff feff        rlc     r9,0xfffffeff
+0x[0-9a-f]+ 232f 1f8b 4242 4242        rlc     r11,0x42424242
+0x[0-9a-f]+ 202f 0f8b 0000 0000        rlc     r0,0
+                       44: ARC_32_ME   foo
+0x[0-9a-f]+ 202f 804b                  rlc.f   r0,r1
+0x[0-9a-f]+ 226f 804b                  rlc.f   r2,0x1
+0x[0-9a-f]+ 262f f10b                  rlc.f   0,r4
+0x[0-9a-f]+ 252f 8f8b 0000 0200        rlc.f   r5,0x200

diff --git a/gas/testsuite/gas/arc/rlc.s b/gas/testsuite/gas/arc/rlc.s
index 3e5d093..29d92eb 100644 (file)
--- a/gas/testsuite/gas/arc/rlc.s
+++ b/gas/testsuite/gas/arc/rlc.s
@@ -6,53 +6,16 @@
        rlc r0,0
        rlc r1,-1
        rlc 0,r2
-       rlc -1,r3
        rlc r4,255
-       rlc 255,r5
        rlc r6,-256
-       rlc -256,r7
 
        rlc r8,256
        rlc r9,-257
        rlc r11,0x42424242
 
-       rlc 255,256
-
        rlc r0,foo
 
-       rlc.al r0,r1
-       rlc.ra r3,r4
-       rlc.eq r6,r7
-       rlc.z r9,r10
-       rlc.ne r12,r13
-       rlc.nz r15,r16
-       rlc.pl r18,r19
-       rlc.p r21,r22
-       rlc.mi r24,r25
-       rlc.n r27,r28
-       rlc.cs r30,r31
-       rlc.c r33,r34
-       rlc.lo r36,r37
-       rlc.cc r39,r40
-       rlc.nc r42,r43
-       rlc.hs r45,r46
-       rlc.vs r48,r49
-       rlc.v r49,r50
-       rlc.vc r49,r55
-       rlc.nv r49,r58
-       rlc.gt r60,r60
-       rlc.ge r0,0
-       rlc.le 2,2
-       rlc.hi r3,r3
-       rlc.ls r4,r4
-       rlc.pnz r5,r5
-
        rlc.f r0,r1
        rlc.f r2,1
-       rlc.f 1,r3
        rlc.f 0,r4
        rlc.f r5,512
-       rlc.f 512,512
-
-       rlc.eq.f r0,r1
-       rlc.ne.f r1,0

diff --git a/gas/testsuite/gas/arc/ror.d b/gas/testsuite/gas/arc/ror.d
index 691736b..cd2e92f 100644 (file)
--- a/gas/testsuite/gas/arc/ror.d
+++ b/gas/testsuite/gas/arc/ror.d
@@ -1,51 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 86 00 18     18008600     ror        r0,r1
-   4:  00 06 6e 1b     1b6e0600     ror        fp,sp
-   8:  00 86 1f 18     181f8600     ror        r0,0
-   c:  ff 87 3f 18     183f87ff     ror        r1,-1
-  10:  00 06 e1 1f     1fe10600     ror        0,r2
-  14:  00 86 e1 1f     1fe18600     ror        0,r3
-  18:  ff 86 9f 18     189f86ff     ror        r4,255
-  1c:  00 86 e2 1f     1fe28600     ror        0,r5
-  20:  00 87 df 18     18df8700     ror        r6,-256
-  24:  00 86 e3 1f     1fe38600     ror        0,r7
-  28:  00 06 1f 19     191f0600     ror        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 06 3f 19     193f0600     ror        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 06 7f 19     197f0600     ror        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 06 ff 1f     1fff0600     ror        0,0x100
-  44:  00 01 00 00 
-  48:  00 06 1f 18     181f0600     ror        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 86 45 19     19458601     ror.z      r10,r11
-  54:  02 86 86 19     19868602     ror.nz     r12,r13
-  58:  0b 06 df 19     19df060b     ror.lt     r14,0
-  5c:  00 00 00 00 
-  60:  09 06 ff 19     19ff0609     ror.gt     r15,0x200
-  64:  00 02 00 00 
-  68:  00 87 00 18     18008700     ror.f      r0,r1
-  6c:  01 86 5e 18     185e8601     ror.f      r2,1
-  70:  00 07 e2 1f     1fe20700     ror.f      0,r4
-  74:  00 07 bf 18     18bf0700     ror.f      r5,0x200
-  78:  00 02 00 00 
-  7c:  00 07 df 1f     1fdf0700     ror.f      0,0x200
-  80:  00 02 00 00 
-  84:  01 87 00 18     18008701     ror.z.f    r0,r1
-  88:  02 07 3f 18     183f0702     ror.nz.f   r1,0
-  8c:  00 00 00 00 
-  90:  0b 07 c1 1f     1fc1070b     ror.lt.f   0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 07 1f 18     181f070c     ror.le.f   r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 07 df 1f     1fdf0704     ror.n.f    0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 2903 0080                  ror     r0,r1,r2
+0x[0-9a-f]+ 2b03 371a                  ror     gp,fp,sp
+0x[0-9a-f]+ 2e03 37dd                  ror     ilink,r30,blink
+0x[0-9a-f]+ 2943 0000                  ror     r0,r1,0
+0x[0-9a-f]+ 2e03 7080 0000 0000        ror     r0,0,r2
+0x[0-9a-f]+ 2903 00be                  ror     0,r1,r2
+0x[0-9a-f]+ 2903 0f80 ffff ffff        ror     r0,r1,0xffffffff
+0x[0-9a-f]+ 2e03 7080 ffff ffff        ror     r0,0xffffffff,r2
+0x[0-9a-f]+ 2903 0f80 0000 00ff        ror     r0,r1,0xff
+0x[0-9a-f]+ 2e03 7080 0000 00ff        ror     r0,0xff,r2
+0x[0-9a-f]+ 2903 0f80 ffff ff00        ror     r0,r1,0xffffff00
+0x[0-9a-f]+ 2e03 7080 ffff ff00        ror     r0,0xffffff00,r2
+0x[0-9a-f]+ 2903 0f80 0000 0100        ror     r0,r1,0x100
+0x[0-9a-f]+ 2e03 7080 ffff feff        ror     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2e03 7f80 0000 0100        ror     r0,0x100,0x100
+0x[0-9a-f]+ 2903 0f80 0000 0000        ror     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 28c3 0080                  ror     r0,r0,r2
+0x[0-9a-f]+ 2bc3 0140                  ror     r3,r3,r5
+0x[0-9a-f]+ 2ec3 0201                  ror.eq  r6,r6,r8
+0x[0-9a-f]+ 29c3 12c1                  ror.eq  r9,r9,r11
+0x[0-9a-f]+ 2cc3 1382                  ror.ne  r12,r12,r14
+0x[0-9a-f]+ 2fc3 1442                  ror.ne  r15,r15,r17
+0x[0-9a-f]+ 2ac3 2503                  ror.p   r18,r18,r20
+0x[0-9a-f]+ 2dc3 25c3                  ror.p   r21,r21,r23
+0x[0-9a-f]+ 28c3 3684                  ror.n   r24,r24,gp
+0x[0-9a-f]+ 2bc3 3744                  ror.n   fp,fp,ilink
+0x[0-9a-f]+ 2ec3 37c5                  ror.c   r30,r30,blink
+0x[0-9a-f]+ 2bc3 00c5                  ror.c   r3,r3,r3
+0x[0-9a-f]+ 2bc3 0205                  ror.c   r3,r3,r8
+0x[0-9a-f]+ 2bc3 0106                  ror.nc  r3,r3,r4
+0x[0-9a-f]+ 2cc3 0106                  ror.nc  r4,r4,r4
+0x[0-9a-f]+ 2cc3 01c6                  ror.nc  r4,r4,r7
+0x[0-9a-f]+ 2cc3 0147                  ror.v   r4,r4,r5
+0x[0-9a-f]+ 2dc3 0147                  ror.v   r5,r5,r5
+0x[0-9a-f]+ 2dc3 0148                  ror.nv  r5,r5,r5
+0x[0-9a-f]+ 2dc3 0148                  ror.nv  r5,r5,r5
+0x[0-9a-f]+ 2ec3 0009                  ror.gt  r6,r6,r0
+0x[0-9a-f]+ 28c3 002a                  ror.ge  r0,r0,0
+0x[0-9a-f]+ 29c3 006b                  ror.lt  r1,r1,0x1
+0x[0-9a-f]+ 2bc3 00ed                  ror.hi  r3,r3,0x3
+0x[0-9a-f]+ 2cc3 012e                  ror.ls  r4,r4,0x4
+0x[0-9a-f]+ 2dc3 016f                  ror.pnz r5,r5,0x5
+0x[0-9a-f]+ 2903 8080                  ror.f   r0,r1,r2
+0x[0-9a-f]+ 2943 8040                  ror.f   r0,r1,0x1
+0x[0-9a-f]+ 2e03 f080 0000 0001        ror.f   r0,0x1,r2
+0x[0-9a-f]+ 2903 80be                  ror.f   0,r1,r2
+0x[0-9a-f]+ 2903 8f80 0000 0200        ror.f   r0,r1,0x200
+0x[0-9a-f]+ 2e03 f080 0000 0200        ror.f   r0,0x200,r2
+0x[0-9a-f]+ 29c3 8081                  ror.f.eq        r1,r1,r2
+0x[0-9a-f]+ 28c3 8022                  ror.f.ne        r0,r0,0
+0x[0-9a-f]+ 2ac3 808b                  ror.f.lt        r2,r2,r2
+0x[0-9a-f]+ 2ec3 f0a9 0000 0001        ror.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 2ec3 ff8c 0000 0200        ror.f.le        0,0x200,0x200
+0x[0-9a-f]+ 2ec3 f0aa 0000 0200        ror.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/ror.s b/gas/testsuite/gas/arc/ror.s
index de23351..fadb678 100644 (file)
--- a/gas/testsuite/gas/arc/ror.s
+++ b/gas/testsuite/gas/arc/ror.s
@@ -1,38 +1,63 @@
 # ror test
 
-       ror r0,r1
-       ror fp,sp
-
-       ror r0,0
-       ror r1,-1
-       ror 0,r2
-       ror -1,r3
-       ror r4,255
-       ror 255,r5
-       ror r6,-256
-       ror -256,r7
-
-       ror r8,256
-       ror r9,-257
-       ror r11,0x42424242
-
-       ror 255,256
-
-       ror r0,foo
-
-       ror.eq r10,r11
-       ror.ne r12,r13
-       ror.lt r14,0
-       ror.gt r15,512
-
-       ror.f r0,r1
-       ror.f r2,1
-       ror.f 0,r4
-       ror.f r5,512
-       ror.f 512,512
-
-       ror.eq.f r0,r1
-       ror.ne.f r1,0
-       ror.lt.f 0,r2
-       ror.le.f r0,512
-       ror.n.f 512,512
+       ror r0,r1,r2
+       ror r26,fp,sp
+       ror ilink1,ilink2,blink
+
+       ror r0,r1,0
+       ror r0,0,r2
+       ror 0,r1,r2
+       ror r0,r1,-1
+       ror r0,-1,r2
+       ror r0,r1,255
+       ror r0,255,r2
+       ror r0,r1,-256
+       ror r0,-256,r2
+
+       ror r0,r1,256
+       ror r0,-257,r2
+
+       ror r0,256,256
+
+       ror r0,r1,foo
+
+       ror.al r0,r0,r2
+       ror.ra r3,r3,r5
+       ror.eq r6,r6,r8
+       ror.z  r9,r9,r11
+       ror.ne r12,r12,r14
+       ror.nz r15,r15,r17
+       ror.pl r18,r18,r20
+       ror.p  r21,r21,r23
+       ror.mi r24,r24,r26
+       ror.n  r27,r27,r29
+       ror.cs r30,r30,r31
+       ror.c  r3,r3,r3
+       ror.lo r3,r3,r8
+       ror.cc r3,r3,r4
+       ror.nc r4,r4,r4
+       ror.hs r4,r4,r7
+       ror.vs r4,r4,r5
+       ror.v  r5,r5,r5
+       ror.vc r5,r5,r5
+       ror.nv r5,r5,r5
+       ror.gt r6,r6,r0
+       ror.ge r0,r0,0
+       ror.lt r1,r1,1
+       ror.hi r3,r3,3
+       ror.ls r4,r4,4
+       ror.pnz r5,r5,5
+
+       ror.f r0,r1,r2
+       ror.f r0,r1,1
+       ror.f r0,1,r2
+       ror.f 0,r1,r2
+       ror.f r0,r1,512
+       ror.f r0,512,r2
+
+       ror.eq.f r1,r1,r2
+       ror.ne.f r0,r0,0
+       ror.lt.f r2,r2,r2
+       ror.gt.f 0,1,2
+       ror.le.f 0,512,512
+       ror.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/rrc.d b/gas/testsuite/gas/arc/rrc.d
index 9c702cb..446fc0f 100644 (file)
--- a/gas/testsuite/gas/arc/rrc.d
+++ b/gas/testsuite/gas/arc/rrc.d
@@ -1,51 +1,22 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 88 00 18     18008800     rrc        r0,r1
-   4:  00 08 6e 1b     1b6e0800     rrc        fp,sp
-   8:  00 88 1f 18     181f8800     rrc        r0,0
-   c:  ff 89 3f 18     183f89ff     rrc        r1,-1
-  10:  00 08 e1 1f     1fe10800     rrc        0,r2
-  14:  00 88 e1 1f     1fe18800     rrc        0,r3
-  18:  ff 88 9f 18     189f88ff     rrc        r4,255
-  1c:  00 88 e2 1f     1fe28800     rrc        0,r5
-  20:  00 89 df 18     18df8900     rrc        r6,-256
-  24:  00 88 e3 1f     1fe38800     rrc        0,r7
-  28:  00 08 1f 19     191f0800     rrc        r8,0x100
-  2c:  00 01 00 00 
-  30:  00 08 3f 19     193f0800     rrc        r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 08 7f 19     197f0800     rrc        r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 08 ff 1f     1fff0800     rrc        0,0x100
-  44:  00 01 00 00 
-  48:  00 08 1f 18     181f0800     rrc        r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 88 45 19     19458801     rrc.z      r10,r11
-  54:  02 88 86 19     19868802     rrc.nz     r12,r13
-  58:  0b 08 df 19     19df080b     rrc.lt     r14,0
-  5c:  00 00 00 00 
-  60:  09 08 ff 19     19ff0809     rrc.gt     r15,0x200
-  64:  00 02 00 00 
-  68:  00 89 00 18     18008900     rrc.f      r0,r1
-  6c:  01 88 5e 18     185e8801     rrc.f      r2,1
-  70:  00 09 e2 1f     1fe20900     rrc.f      0,r4
-  74:  00 09 bf 18     18bf0900     rrc.f      r5,0x200
-  78:  00 02 00 00 
-  7c:  00 09 df 1f     1fdf0900     rrc.f      0,0x200
-  80:  00 02 00 00 
-  84:  01 89 00 18     18008901     rrc.z.f    r0,r1
-  88:  02 09 3f 18     183f0902     rrc.nz.f   r1,0
-  8c:  00 00 00 00 
-  90:  0b 09 c1 1f     1fc1090b     rrc.lt.f   0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 09 1f 18     181f090c     rrc.le.f   r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 09 df 1f     1fdf0904     rrc.n.f    0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 202f 0044                  rrc     r0,r1
+0x[0-9a-f]+ 232f 3704                  rrc     fp,sp
+0x[0-9a-f]+ 206f 0004                  rrc     r0,0
+0x[0-9a-f]+ 212f 0f84 ffff ffff        rrc     r1,0xffffffff
+0x[0-9a-f]+ 262f 7084                  rrc     0,r2
+0x[0-9a-f]+ 242f 0f84 0000 00ff        rrc     r4,0xff
+0x[0-9a-f]+ 262f 0f84 ffff ff00        rrc     r6,0xffffff00
+0x[0-9a-f]+ 202f 1f84 0000 0100        rrc     r8,0x100
+0x[0-9a-f]+ 212f 1f84 ffff feff        rrc     r9,0xfffffeff
+0x[0-9a-f]+ 232f 1f84 4242 4242        rrc     r11,0x42424242
+0x[0-9a-f]+ 202f 0f84 0000 0000        rrc     r0,0
+                       44: ARC_32_ME   foo
+0x[0-9a-f]+ 202f 8044                  rrc.f   r0,r1
+0x[0-9a-f]+ 226f 8044                  rrc.f   r2,0x1
+0x[0-9a-f]+ 262f f104                  rrc.f   0,r4
+0x[0-9a-f]+ 252f 8f84 0000 0200        rrc.f   r5,0x200

diff --git a/gas/testsuite/gas/arc/rrc.s b/gas/testsuite/gas/arc/rrc.s
index c0e1780..26f6551 100644 (file)
--- a/gas/testsuite/gas/arc/rrc.s
+++ b/gas/testsuite/gas/arc/rrc.s
@@ -6,33 +6,16 @@
        rrc r0,0
        rrc r1,-1
        rrc 0,r2
-       rrc -1,r3
        rrc r4,255
-       rrc 255,r5
        rrc r6,-256
-       rrc -256,r7
 
        rrc r8,256
        rrc r9,-257
        rrc r11,0x42424242
 
-       rrc 255,256
-
        rrc r0,foo
 
-       rrc.eq r10,r11
-       rrc.ne r12,r13
-       rrc.lt r14,0
-       rrc.gt r15,512
-
        rrc.f r0,r1
        rrc.f r2,1
        rrc.f 0,r4
        rrc.f r5,512
-       rrc.f 512,512
-
-       rrc.eq.f r0,r1
-       rrc.ne.f r1,0
-       rrc.lt.f 0,r2
-       rrc.le.f r0,512
-       rrc.n.f 512,512

diff --git a/gas/testsuite/gas/arc/sbc.d b/gas/testsuite/gas/arc/sbc.d
index 7fa0490..07c147f 100644 (file)
--- a/gas/testsuite/gas/arc/sbc.d
+++ b/gas/testsuite/gas/arc/sbc.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 58     58008400     sbc        r0,r1,r2
-   4:  00 b8 4d 5b     5b4db800     sbc        gp,fp,sp
-   8:  00 3e af 5b     5baf3e00     sbc        ilink1,ilink2,blink
-   c:  00 f8 1d 5f     5f1df800     sbc        r56,r59,lp_count
-  10:  00 fe 00 58     5800fe00     sbc        r0,r1,0
-  14:  00 84 1f 58     581f8400     sbc        r0,0,r2
-  18:  00 84 e0 5f     5fe08400     sbc        0,r1,r2
-  1c:  ff ff 00 58     5800ffff     sbc        r0,r1,-1
-  20:  ff 85 1f 58     581f85ff     sbc        r0,-1,r2
-  24:  00 84 e0 5f     5fe08400     sbc        0,r1,r2
-  28:  ff fe 00 58     5800feff     sbc        r0,r1,255
-  2c:  ff 84 1f 58     581f84ff     sbc        r0,255,r2
-  30:  00 84 e0 5f     5fe08400     sbc        0,r1,r2
-  34:  00 ff 00 58     5800ff00     sbc        r0,r1,-256
-  38:  00 85 1f 58     581f8500     sbc        r0,-256,r2
-  3c:  00 84 e0 5f     5fe08400     sbc        0,r1,r2
-  40:  00 fc 00 58     5800fc00     sbc        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 58     581f0400     sbc        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 58     581ffcff     sbc        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 58     581f7eff     sbc        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 58     5800fc00     sbc        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 58     58008400     sbc        r0,r1,r2
-  6c:  00 0a 62 58     58620a00     sbc        r3,r4,r5
-  70:  01 90 c3 58     58c39001     sbc.z      r6,r7,r8
-  74:  01 16 25 59     59251601     sbc.z      r9,r10,r11
-  78:  02 9c 86 59     59869c02     sbc.nz     r12,r13,r14
-  7c:  02 22 e8 59     59e82202     sbc.nz     r15,r16,r17
-  80:  03 a8 49 5a     5a49a803     sbc.p      r18,r19,r20
-  84:  03 2e ab 5a     5aab2e03     sbc.p      r21,r22,r23
-  88:  04 b4 0c 5b     5b0cb404     sbc.n      r24,r25,gp
-  8c:  04 3a 6e 5b     5b6e3a04     sbc.n      fp,sp,ilink1
-  90:  05 c0 cf 5b     5bcfc005     sbc.c      ilink2,blink,r32
-  94:  05 46 31 5c     5c314605     sbc.c      r33,r34,r35
-  98:  05 cc 92 5c     5c92cc05     sbc.c      r36,r37,r38
-  9c:  06 52 f4 5c     5cf45206     sbc.nc     r39,r40,r41
-  a0:  06 d8 55 5d     5d55d806     sbc.nc     r42,r43,r44
-  a4:  06 5e b7 5d     5db75e06     sbc.nc     r45,r46,r47
-  a8:  07 e4 18 5e     5e18e407     sbc.v      r48,r49,r50
-  ac:  07 6a 1a 5f     5f1a6a07     sbc.v      r56,r52,r53
-  b0:  08 f0 1b 5f     5f1bf008     sbc.nv     r56,r55,r56
-  b4:  08 76 1d 5f     5f1d7608     sbc.nv     r56,r58,r59
-  b8:  09 00 9e 5f     5f9e0009     sbc.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 58     58007c0a     sbc.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 58     583f020b     sbc.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 58     587f060d     sbc.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 5f     5fdf080e     sbc.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 5f     5fc2fc0f     sbc.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 58     58008500     sbc.f      r0,r1,r2
-  e8:  01 fa 00 58     5800fa01     sbc.f      r0,r1,1
-  ec:  01 84 1e 58     581e8401     sbc.f      r0,1,r2
-  f0:  00 85 e0 5f     5fe08500     sbc.f      0,r1,r2
-  f4:  00 fd 00 58     5800fd00     sbc.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 58     581f0500     sbc.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 58     58008501     sbc.z.f    r0,r1,r2
- 108:  02 fd 00 58     5800fd02     sbc.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 58     581f050b     sbc.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 5f     5fc08509     sbc.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 58     5800fd0c     sbc.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 58     581f050a     sbc.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2103 0080                  sbc     r0,r1,r2
+0x[0-9a-f]+ 2303 371a                  sbc     gp,fp,sp
+0x[0-9a-f]+ 2603 37dd                  sbc     ilink,r30,blink
+0x[0-9a-f]+ 2143 0000                  sbc     r0,r1,0
+0x[0-9a-f]+ 2603 7080 0000 0000        sbc     r0,0,r2
+0x[0-9a-f]+ 2103 00be                  sbc     0,r1,r2
+0x[0-9a-f]+ 2103 0f80 ffff ffff        sbc     r0,r1,0xffffffff
+0x[0-9a-f]+ 2603 7080 ffff ffff        sbc     r0,0xffffffff,r2
+0x[0-9a-f]+ 2103 0f80 0000 00ff        sbc     r0,r1,0xff
+0x[0-9a-f]+ 2603 7080 0000 00ff        sbc     r0,0xff,r2
+0x[0-9a-f]+ 2103 0f80 ffff ff00        sbc     r0,r1,0xffffff00
+0x[0-9a-f]+ 2603 7080 ffff ff00        sbc     r0,0xffffff00,r2
+0x[0-9a-f]+ 2103 0f80 0000 0100        sbc     r0,r1,0x100
+0x[0-9a-f]+ 2603 7080 ffff feff        sbc     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2603 7f80 0000 0100        sbc     r0,0x100,0x100
+0x[0-9a-f]+ 2103 0f80 0000 0000        sbc     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c3 0080                  sbc     r0,r0,r2
+0x[0-9a-f]+ 23c3 0140                  sbc     r3,r3,r5
+0x[0-9a-f]+ 26c3 0201                  sbc.eq  r6,r6,r8
+0x[0-9a-f]+ 21c3 12c1                  sbc.eq  r9,r9,r11
+0x[0-9a-f]+ 24c3 1382                  sbc.ne  r12,r12,r14
+0x[0-9a-f]+ 27c3 1442                  sbc.ne  r15,r15,r17
+0x[0-9a-f]+ 22c3 2503                  sbc.p   r18,r18,r20
+0x[0-9a-f]+ 25c3 25c3                  sbc.p   r21,r21,r23
+0x[0-9a-f]+ 20c3 3684                  sbc.n   r24,r24,gp
+0x[0-9a-f]+ 23c3 3744                  sbc.n   fp,fp,ilink
+0x[0-9a-f]+ 26c3 37c5                  sbc.c   r30,r30,blink
+0x[0-9a-f]+ 23c3 00c5                  sbc.c   r3,r3,r3
+0x[0-9a-f]+ 23c3 0205                  sbc.c   r3,r3,r8
+0x[0-9a-f]+ 23c3 0106                  sbc.nc  r3,r3,r4
+0x[0-9a-f]+ 24c3 0106                  sbc.nc  r4,r4,r4
+0x[0-9a-f]+ 24c3 01c6                  sbc.nc  r4,r4,r7
+0x[0-9a-f]+ 24c3 0147                  sbc.v   r4,r4,r5
+0x[0-9a-f]+ 25c3 0147                  sbc.v   r5,r5,r5
+0x[0-9a-f]+ 25c3 0148                  sbc.nv  r5,r5,r5
+0x[0-9a-f]+ 25c3 0148                  sbc.nv  r5,r5,r5
+0x[0-9a-f]+ 26c3 0009                  sbc.gt  r6,r6,r0
+0x[0-9a-f]+ 20c3 002a                  sbc.ge  r0,r0,0
+0x[0-9a-f]+ 21c3 006b                  sbc.lt  r1,r1,0x1
+0x[0-9a-f]+ 23c3 00ed                  sbc.hi  r3,r3,0x3
+0x[0-9a-f]+ 24c3 012e                  sbc.ls  r4,r4,0x4
+0x[0-9a-f]+ 25c3 016f                  sbc.pnz r5,r5,0x5
+0x[0-9a-f]+ 2103 8080                  sbc.f   r0,r1,r2
+0x[0-9a-f]+ 2143 8040                  sbc.f   r0,r1,0x1
+0x[0-9a-f]+ 2603 f080 0000 0001        sbc.f   r0,0x1,r2
+0x[0-9a-f]+ 2103 80be                  sbc.f   0,r1,r2
+0x[0-9a-f]+ 2103 8f80 0000 0200        sbc.f   r0,r1,0x200
+0x[0-9a-f]+ 2603 f080 0000 0200        sbc.f   r0,0x200,r2
+0x[0-9a-f]+ 21c3 8081                  sbc.f.eq        r1,r1,r2
+0x[0-9a-f]+ 20c3 8022                  sbc.f.ne        r0,r0,0
+0x[0-9a-f]+ 22c3 808b                  sbc.f.lt        r2,r2,r2
+0x[0-9a-f]+ 26c3 f0a9 0000 0001        sbc.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 26c3 ff8c 0000 0200        sbc.f.le        0,0x200,0x200
+0x[0-9a-f]+ 26c3 f0aa 0000 0200        sbc.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/sbc.s b/gas/testsuite/gas/arc/sbc.s
index 8eb9646..dd18c28 100644 (file)
--- a/gas/testsuite/gas/arc/sbc.s
+++ b/gas/testsuite/gas/arc/sbc.s
@@ -3,55 +3,50 @@
        sbc r0,r1,r2
        sbc r26,fp,sp
        sbc ilink1,ilink2,blink
-       sbc r56,r59,lp_count
 
        sbc r0,r1,0
        sbc r0,0,r2
        sbc 0,r1,r2
        sbc r0,r1,-1
        sbc r0,-1,r2
-       sbc -1,r1,r2
        sbc r0,r1,255
        sbc r0,255,r2
-       sbc 255,r1,r2
        sbc r0,r1,-256
        sbc r0,-256,r2
-       sbc -256,r1,r2
 
        sbc r0,r1,256
        sbc r0,-257,r2
 
-       sbc r0,255,256
-       sbc r0,256,255
+       sbc r0,256,256
 
        sbc r0,r1,foo
 
-       sbc.al r0,r1,r2
-       sbc.ra r3,r4,r5
-       sbc.eq r6,r7,r8
-       sbc.z r9,r10,r11
-       sbc.ne r12,r13,r14
-       sbc.nz r15,r16,r17
-       sbc.pl r18,r19,r20
-       sbc.p r21,r22,r23
-       sbc.mi r24,r25,r26
-       sbc.n r27,r28,r29
-       sbc.cs r30,r31,r32
-       sbc.c r33,r34,r35
-       sbc.lo r36,r37,r38
-       sbc.cc r39,r40,r41
-       sbc.nc r42,r43,r44
-       sbc.hs r45,r46,r47
-       sbc.vs r48,r49,r50
-       sbc.v r56,r52,r53
-       sbc.vc r56,r55,r56
-       sbc.nv r56,r58,r59
-       sbc.gt r60,r60,r0
+       sbc.al r0,r0,r2
+       sbc.ra r3,r3,r5
+       sbc.eq r6,r6,r8
+       sbc.z  r9,r9,r11
+       sbc.ne r12,r12,r14
+       sbc.nz r15,r15,r17
+       sbc.pl r18,r18,r20
+       sbc.p  r21,r21,r23
+       sbc.mi r24,r24,r26
+       sbc.n  r27,r27,r29
+       sbc.cs r30,r30,r31
+       sbc.c  r3,r3,r3
+       sbc.lo r3,r3,r8
+       sbc.cc r3,r3,r4
+       sbc.nc r4,r4,r4
+       sbc.hs r4,r4,r7
+       sbc.vs r4,r4,r5
+       sbc.v  r5,r5,r5
+       sbc.vc r5,r5,r5
+       sbc.nv r5,r5,r5
+       sbc.gt r6,r6,r0
        sbc.ge r0,r0,0
-       sbc.lt r1,1,r1
-       sbc.hi r3,3,r3
-       sbc.ls 4,4,r4
-       sbc.pnz 5,r5,5
+       sbc.lt r1,r1,1
+       sbc.hi r3,r3,3
+       sbc.ls r4,r4,4
+       sbc.pnz r5,r5,5
 
        sbc.f r0,r1,r2
        sbc.f r0,r1,1
@@ -60,9 +55,9 @@
        sbc.f r0,r1,512
        sbc.f r0,512,r2
 
-       sbc.eq.f r0,r1,r2
-       sbc.ne.f r0,r1,0
-       sbc.lt.f r0,0,r2
-       sbc.gt.f 0,r1,r2
-       sbc.le.f r0,r1,512
-       sbc.ge.f r0,512,r2
+       sbc.eq.f r1,r1,r2
+       sbc.ne.f r0,r0,0
+       sbc.lt.f r2,r2,r2
+       sbc.gt.f 0,1,2
+       sbc.le.f 0,512,512
+       sbc.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/sexb.d b/gas/testsuite/gas/arc/sexb.d
index 96d35d6..bbc4ca5 100644 (file)
--- a/gas/testsuite/gas/arc/sexb.d
+++ b/gas/testsuite/gas/arc/sexb.d
@@ -1,51 +1,22 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 8a 00 18     18008a00     sexb       r0,r1
-   4:  00 0a 6e 1b     1b6e0a00     sexb       fp,sp
-   8:  00 8a 1f 18     181f8a00     sexb       r0,0
-   c:  ff 8b 3f 18     183f8bff     sexb       r1,-1
-  10:  00 0a e1 1f     1fe10a00     sexb       0,r2
-  14:  00 8a e1 1f     1fe18a00     sexb       0,r3
-  18:  ff 8a 9f 18     189f8aff     sexb       r4,255
-  1c:  00 8a e2 1f     1fe28a00     sexb       0,r5
-  20:  00 8b df 18     18df8b00     sexb       r6,-256
-  24:  00 8a e3 1f     1fe38a00     sexb       0,r7
-  28:  00 0a 1f 19     191f0a00     sexb       r8,0x100
-  2c:  00 01 00 00 
-  30:  00 0a 3f 19     193f0a00     sexb       r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 0a 7f 19     197f0a00     sexb       r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 0a ff 1f     1fff0a00     sexb       0,0x100
-  44:  00 01 00 00 
-  48:  00 0a 1f 18     181f0a00     sexb       r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 8a 45 19     19458a01     sexb.z     r10,r11
-  54:  02 8a 86 19     19868a02     sexb.nz    r12,r13
-  58:  0b 0a df 19     19df0a0b     sexb.lt    r14,0
-  5c:  00 00 00 00 
-  60:  09 0a ff 19     19ff0a09     sexb.gt    r15,0x200
-  64:  00 02 00 00 
-  68:  00 8b 00 18     18008b00     sexb.f     r0,r1
-  6c:  01 8a 5e 18     185e8a01     sexb.f     r2,1
-  70:  00 0b e2 1f     1fe20b00     sexb.f     0,r4
-  74:  00 0b bf 18     18bf0b00     sexb.f     r5,0x200
-  78:  00 02 00 00 
-  7c:  00 0b df 1f     1fdf0b00     sexb.f     0,0x200
-  80:  00 02 00 00 
-  84:  01 8b 00 18     18008b01     sexb.z.f   r0,r1
-  88:  02 0b 3f 18     183f0b02     sexb.nz.f  r1,0
-  8c:  00 00 00 00 
-  90:  0b 0b c1 1f     1fc10b0b     sexb.lt.f  0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 0b 1f 18     181f0b0c     sexb.le.f  r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 0b df 1f     1fdf0b04     sexb.n.f   0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 202f 0045                  sexb    r0,r1
+0x[0-9a-f]+ 232f 3705                  sexb    fp,sp
+0x[0-9a-f]+ 206f 0005                  sexb    r0,0
+0x[0-9a-f]+ 212f 0f85 ffff ffff        sexb    r1,0xffffffff
+0x[0-9a-f]+ 262f 7085                  sexb    0,r2
+0x[0-9a-f]+ 242f 0f85 0000 00ff        sexb    r4,0xff
+0x[0-9a-f]+ 262f 0f85 ffff ff00        sexb    r6,0xffffff00
+0x[0-9a-f]+ 202f 1f85 0000 0100        sexb    r8,0x100
+0x[0-9a-f]+ 212f 1f85 ffff feff        sexb    r9,0xfffffeff
+0x[0-9a-f]+ 232f 1f85 4242 4242        sexb    r11,0x42424242
+0x[0-9a-f]+ 202f 0f85 0000 0000        sexb    r0,0
+                       44: ARC_32_ME   foo
+0x[0-9a-f]+ 202f 8045                  sexb.f  r0,r1
+0x[0-9a-f]+ 226f 8045                  sexb.f  r2,0x1
+0x[0-9a-f]+ 262f f105                  sexb.f  0,r4
+0x[0-9a-f]+ 252f 8f85 0000 0200        sexb.f  r5,0x200

diff --git a/gas/testsuite/gas/arc/sexb.s b/gas/testsuite/gas/arc/sexb.s
index a2afc3b..516ffe4 100644 (file)
--- a/gas/testsuite/gas/arc/sexb.s
+++ b/gas/testsuite/gas/arc/sexb.s
@@ -6,33 +6,16 @@
        sexb r0,0
        sexb r1,-1
        sexb 0,r2
-       sexb -1,r3
        sexb r4,255
-       sexb 255,r5
        sexb r6,-256
-       sexb -256,r7
 
        sexb r8,256
        sexb r9,-257
        sexb r11,0x42424242
 
-       sexb 255,256
-
        sexb r0,foo
 
-       sexb.eq r10,r11
-       sexb.ne r12,r13
-       sexb.lt r14,0
-       sexb.gt r15,512
-
        sexb.f r0,r1
        sexb.f r2,1
        sexb.f 0,r4
        sexb.f r5,512
-       sexb.f 512,512
-
-       sexb.eq.f r0,r1
-       sexb.ne.f r1,0
-       sexb.lt.f 0,r2
-       sexb.le.f r0,512
-       sexb.n.f 512,512

diff --git a/gas/testsuite/gas/arc/sexw.d b/gas/testsuite/gas/arc/sexw.d
index 7b6a612..3c918e2 100644 (file)
--- a/gas/testsuite/gas/arc/sexw.d
+++ b/gas/testsuite/gas/arc/sexw.d
@@ -1,51 +1,22 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 8c 00 18     18008c00     sexw       r0,r1
-   4:  00 0c 6e 1b     1b6e0c00     sexw       fp,sp
-   8:  00 8c 1f 18     181f8c00     sexw       r0,0
-   c:  ff 8d 3f 18     183f8dff     sexw       r1,-1
-  10:  00 0c e1 1f     1fe10c00     sexw       0,r2
-  14:  00 8c e1 1f     1fe18c00     sexw       0,r3
-  18:  ff 8c 9f 18     189f8cff     sexw       r4,255
-  1c:  00 8c e2 1f     1fe28c00     sexw       0,r5
-  20:  00 8d df 18     18df8d00     sexw       r6,-256
-  24:  00 8c e3 1f     1fe38c00     sexw       0,r7
-  28:  00 0c 1f 19     191f0c00     sexw       r8,0x100
-  2c:  00 01 00 00 
-  30:  00 0c 3f 19     193f0c00     sexw       r9,0xffff_feff
-  34:  ff fe ff ff 
-  38:  00 0c 7f 19     197f0c00     sexw       r11,0x4242_4242
-  3c:  42 42 42 42 
-  40:  00 0c ff 1f     1fff0c00     sexw       0,0x100
-  44:  00 01 00 00 
-  48:  00 0c 1f 18     181f0c00     sexw       r0,0
-  4c:  00 00 00 00 
-                       4c: R_ARC_32    foo
-  50:  01 8c 45 19     19458c01     sexw.z     r10,r11
-  54:  02 8c 86 19     19868c02     sexw.nz    r12,r13
-  58:  0b 0c df 19     19df0c0b     sexw.lt    r14,0
-  5c:  00 00 00 00 
-  60:  09 0c ff 19     19ff0c09     sexw.gt    r15,0x200
-  64:  00 02 00 00 
-  68:  00 8d 00 18     18008d00     sexw.f     r0,r1
-  6c:  01 8c 5e 18     185e8c01     sexw.f     r2,1
-  70:  00 0d e2 1f     1fe20d00     sexw.f     0,r4
-  74:  00 0d bf 18     18bf0d00     sexw.f     r5,0x200
-  78:  00 02 00 00 
-  7c:  00 0d df 1f     1fdf0d00     sexw.f     0,0x200
-  80:  00 02 00 00 
-  84:  01 8d 00 18     18008d01     sexw.z.f   r0,r1
-  88:  02 0d 3f 18     183f0d02     sexw.nz.f  r1,0
-  8c:  00 00 00 00 
-  90:  0b 0d c1 1f     1fc10d0b     sexw.lt.f  0,r2
-  94:  00 00 00 00     00000000                
-  98:  0c 0d 1f 18     181f0d0c     sexw.le.f  r0,0x200
-  9c:  00 02 00 00 
-  a0:  04 0d df 1f     1fdf0d04     sexw.n.f   0,0x200
-  a4:  00 02 00 00 
+0x[0-9a-f]+ 202f 0046                  sex[wh]+        r0,r1
+0x[0-9a-f]+ 232f 3706                  sex[wh]+        fp,sp
+0x[0-9a-f]+ 206f 0006                  sex[wh]+        r0,0
+0x[0-9a-f]+ 212f 0f86 ffff ffff        sex[wh]+        r1,0xffffffff
+0x[0-9a-f]+ 262f 7086                  sex[wh]+        0,r2
+0x[0-9a-f]+ 242f 0f86 0000 00ff        sex[wh]+        r4,0xff
+0x[0-9a-f]+ 262f 0f86 ffff ff00        sex[wh]+        r6,0xffffff00
+0x[0-9a-f]+ 202f 1f86 0000 0100        sex[wh]+        r8,0x100
+0x[0-9a-f]+ 212f 1f86 ffff feff        sex[wh]+        r9,0xfffffeff
+0x[0-9a-f]+ 232f 1f86 4242 4242        sex[wh]+        r11,0x42424242
+0x[0-9a-f]+ 202f 0f86 0000 0000        sex[wh]+        r0,0
+                       44: ARC_32_ME   foo
+0x[0-9a-f]+ 202f 8046                  sex[wh]+.f      r0,r1
+0x[0-9a-f]+ 226f 8046                  sex[wh]+.f      r2,0x1
+0x[0-9a-f]+ 262f f106                  sex[wh]+.f      0,r4
+0x[0-9a-f]+ 252f 8f86 0000 0200        sex[wh]+.f      r5,0x200

diff --git a/gas/testsuite/gas/arc/sexw.s b/gas/testsuite/gas/arc/sexw.s
index 6d05dab..68d4e3d 100644 (file)
--- a/gas/testsuite/gas/arc/sexw.s
+++ b/gas/testsuite/gas/arc/sexw.s
@@ -6,33 +6,16 @@
        sexw r0,0
        sexw r1,-1
        sexw 0,r2
-       sexw -1,r3
        sexw r4,255
-       sexw 255,r5
        sexw r6,-256
-       sexw -256,r7
 
        sexw r8,256
        sexw r9,-257
        sexw r11,0x42424242
 
-       sexw 255,256
-
        sexw r0,foo
 
-       sexw.eq r10,r11
-       sexw.ne r12,r13
-       sexw.lt r14,0
-       sexw.gt r15,512
-
        sexw.f r0,r1
        sexw.f r2,1
        sexw.f 0,r4
        sexw.f r5,512
-       sexw.f 512,512
-
-       sexw.eq.f r0,r1
-       sexw.ne.f r1,0
-       sexw.lt.f 0,r2
-       sexw.le.f r0,512
-       sexw.n.f 512,512

diff --git a/gas/testsuite/gas/arc/sleep.d b/gas/testsuite/gas/arc/sleep.d
index b6262f6..624c625 100644 (file)
--- a/gas/testsuite/gas/arc/sleep.d
+++ b/gas/testsuite/gas/arc/sleep.d
@@ -1,11 +1,11 @@
-#as: -EL -marc7
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
 00000000 <main>:
-   0:  00 84 00 40     40008400     add        r0,r1,r2
-   4:  01 fe ff 1f     1ffffe01     sleep      
-   8:  00 0a 62 50     50620a00     sub        r3,r4,r5
+   0:  2100 0080               add     r0,r1,r2
+   4:  216f 013f               sleep   0x4
+   8:  2402 0143               sub     r3,r4,r5

diff --git a/gas/testsuite/gas/arc/sleep.s b/gas/testsuite/gas/arc/sleep.s
index c5797fe..cf656e5 100644 (file)
--- a/gas/testsuite/gas/arc/sleep.s
+++ b/gas/testsuite/gas/arc/sleep.s
@@ -2,5 +2,5 @@
 
 main:
        add     r0,r1,r2
-       sleep
+       sleep   0x04
        sub     r3,r4,r5

diff --git a/gas/testsuite/gas/arc/sshift.d b/gas/testsuite/gas/arc/sshift.d
deleted file mode 100644 (file)
index c0207a7..0000000
--- a/gas/testsuite/gas/arc/sshift.d
+++ /dev/null
@@ -1,44 +0,0 @@
-#objdump: -dr
-#name: @OC@
-
-# Test the @OC@ insn.
-
-.*: +file format elf32-.*arc
-
-Disassembly of section .text:
-00000000 1800@I3+80@00 @OC@ r0,r1
-00000004 1b6e@I3+00@00 @OC@ fp,sp
-00000008 181f@I3+80@00 @OC@ r0,0
-0000000c 183f@I3+81@ff @OC@ r1,-1
-00000010 1fe1@I3+00@00 @OC@ 0,r2
-00000014 1fe1@I3+81@ff @OC@ -1,r3
-00000018 189f@I3+80@ff @OC@ r4,255
-0000001c 1fe2@I3+80@ff @OC@ 255,r5
-00000020 18df@I3+81@00 @OC@ r6,-256
-00000024 1fe3@I3+81@00 @OC@ -256,r7
-00000028 191f@I3+00@00 @OC@ r8,256
-00000030 193f@I3+00@00 @OC@ r9,-257
-00000038 1fc5@I3+00@00 @OC@ 511,r10
-00000040 197f@I3+00@00 @OC@ r11,1111638594
-00000048 1fc6@I3+00@00 @OC@ 305419896,r12
-00000050 1fff@I3+00@ff @OC@ 255,256
-00000058 1fdf@I3+80@ff @OC@ 256,255
-00000060 181f@I3+00@00 @OC@ r0,0
-               RELOC: 00000064 R_ARC_32 foo
-00000068 1945@I3+80@01 @OC@.eq r10,r11
-0000006c 1986@I3+80@02 @OC@.ne r12,r13
-00000070 19df@I3+00@0b @OC@.lt r14,0
-00000078 19ff@I3+00@09 @OC@.gt r15,512
-00000080 1800@I3+81@00 @OC@.f r0,r1
-00000084 185e@I3+80@01 @OC@.f r2,1
-00000088 1fa2@I3+00@00 @OC@.f 0,r4
-0000008c 18bf@I3+01@00 @OC@.f r5,512
-00000094 1fc3@I3+01@00 @OC@.f 512,r6
-0000009c 1fdf@I3+01@00 @OC@.f 512,512
-000000a4 1800@I3+81@01 @OC@.eq.f r0,r1
-000000a8 183f@I3+01@02 @OC@.ne.f r1,0
-000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2
-000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2
-000000c0 181f@I3+01@0c @OC@.le.f r0,512
-000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2
-000000d0 1fdf@I3+01@04 @OC@.n.f 512,512

diff --git a/gas/testsuite/gas/arc/sshift.s b/gas/testsuite/gas/arc/sshift.s
deleted file mode 100644 (file)
index e2fa661..0000000
--- a/gas/testsuite/gas/arc/sshift.s
+++ /dev/null
@@ -1,52 +0,0 @@
-# Single shift @OC@ test
-
-# reg,reg
-       @OC@ r0,r1
-       @OC@ fp,sp
-
-# shimm values
-       @OC@ r0,0
-       @OC@ r1,-1
-       @OC@ 0,r2
-       @OC@ -1,r3
-       @OC@ r4,255
-       @OC@ 255,r5
-       @OC@ r6,-256
-       @OC@ -256,r7
-
-# limm values
-       @OC@ r8,256
-       @OC@ r9,-257
-       @OC@ 511,r10
-       @OC@ r11,0x42424242
-       @OC@ 0x12345678,r12
-
-# shimm and limm
-       @OC@ 255,256
-       @OC@ 256,255
-
-# symbols
-       @OC@ r0,foo
-
-# conditional execution
-       @OC@.eq r10,r11
-       @OC@.ne r12,r13
-       @OC@.lt r14,0
-       @OC@.gt r15,512
-
-# flag setting
-       @OC@.f r0,r1
-       @OC@.f r2,1
-       @OC@.f 0,r4
-       @OC@.f r5,512
-       @OC@.f 512,r6
-       @OC@.f 512,512
-
-# conditional execution + flag setting
-       @OC@.eq.f r0,r1
-       @OC@.ne.f r1,0
-       @OC@.lt.f 0,r2
-       @OC@.gt.f 1,r2
-       @OC@.le.f r0,512
-       @OC@.ge.f 512,r2
-       @OC@.n.f 512,512

diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
index 813f1aa..ea4f523 100644 (file)
--- a/gas/testsuite/gas/arc/st.d
+++ b/gas/testsuite/gas/arc/st.d
@@ -1,42 +1,32 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=archs
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <.text>:
-   0:  00 02 01 10     10010200     st         r1,\[r2\]
-   4:  0e 02 01 10     1001020e     st         r1,\[r2,14\]
-   8:  00 02 41 10     10410200     stb        r1,\[r2\]
-   c:  0e 82 01 11     1101820e     st.a       r1,\[r3,14\]
-  10:  02 02 81 11     11810202     stw.a      r1,\[r2,2\]
-  14:  00 02 1f 10     101f0200     st         r1,\[0x384\]
-  18:  84 03 00 00 
-  1c:  00 7e 41 10     10417e00     stb        0,\[r2\]
-  20:  f8 7f 01 10     10017ff8     st         -8,\[r2,-8\]
-  24:  50 7e 1f 10     101f7e50     st         80,\[0x2ee\]
-  28:  9e 02 00 00 
-  2c:  00 04 1f 10     101f0400     st         r2,\[0\]
-  30:  00 00 00 00 
-                       30: R_ARC_32    foo
-  34:  02 02 01 14     14010202     st.di      r1,\[r2,2\]
-  38:  03 02 01 15     15010203     st.a.di    r1,\[r2,3\]
-  3c:  04 02 81 15     15810204     stw.a.di   r1,\[r2,4\]
-  40:  04 7c 06 10     10067c04     st         80,\[r12,4\]
-  44:  50 00 00 00 
-                       44: R_ARC_32    .text
-  48:  04 7c 06 10     10067c04     st         20,\[r12,4\]
-  4c:  14 00 00 00 
-                       4c: R_ARC_B26   .text
-  50:  00 02 01 12     12010200     sr         r1,\[r2\]
-  54:  0e 82 1f 12     121f820e     sr         r1,\[0xe\]
-  58:  00 fc 00 12     1200fc00     sr         0x3e8,\[r1\]
-  5c:  e8 03 00 00 
-  60:  64 7e 01 12     12017e64     sr         100,\[r2\]
-  64:  00 02 1f 12     121f0200     sr         r1,\[0x2710\]
-  68:  10 27 00 00 
-  6c:  64 7e 1f 12     121f7e64     sr         100,\[0x2710\]
-  70:  10 27 00 00 
-  74:  64 fc 1f 12     121ffc64     sr         0x2710,\[0x64\]
-  78:  10 27 00 00 
+[0-9a-f]+ <.L1-0x40>:
+   0:  1a00 0040               st      r1,\[r2\]
+   4:  1a0e 0040               st      r1,\[r2,14\]
+   8:  1a00 0042               stb     r1,\[r2\]
+   c:  1b0e 0048               st.aw   r1,\[r3,14\]
+  10:  1a02 004c               st[hw]+.aw      r1,\[r2,2\]
+  14:  1e00 7040 0000 0384     st      r1,\[0x384\]
+  1c:  1a00 0003               stb     0,\[r2\]
+  20:  1af8 8e01               st      56,\[r2,-8\]
+  24:  1e00 7080 0000 0000     st      r2,\[0\]
+                       28: ARC_32_ME   foo
+  2c:  1a02 0060               st.di   r1,\[r2,2\]
+  30:  1a03 0068               st.di.aw        r1,\[r2,3\]
+  34:  1a04 006c               st[hw]+.di.aw   r1,\[r2,4\]
+  38:  1c04 1f80 0000 0000     st      0,\[r12,4\]
+                       3c: ARC_32_ME   .L1
+
+[0-9a-f]+ <.L1>:
+  40:  212b 0080               sr      r1,\[r2\]
+  44:  216b 0380               sr      r1,\[0xe\]
+  48:  262b 7040 0000 03e8     sr      0x3e8,\[r1\]
+  50:  262b 7080 0000 0064     sr      0x64,\[r2\]
+  58:  212b 0f80 0000 2710     sr      r1,\[0x2710\]
+  60:  266b 7fc0 0000 0064     sr      0x64,\[0x3f\]
+  68:  26ab 7901 0000 2710     sr      0x2710,\[100\]

diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s
index 9acd9f5..546d725 100644 (file)
--- a/gas/testsuite/gas/arc/st.s
+++ b/gas/testsuite/gas/arc/st.s
@@ -8,14 +8,12 @@
        st      r1,[900]
        stb     0,[r2]
        st      -8,[r2,-8]
-       st      80,[750]
-       st      r2,[foo]
+       st      r2,[@foo]
        st.di   r1,[r2,2]
        st.a.di r1,[r2,3]
        stw.a.di r1,[r2,4]
 
-       st .L1,[r12,4]
-       st .L1@h30,[r12,4]
+       st @.L1,[r12,4]
 .L1:
 
        sr      r1,[r2]
@@ -23,5 +21,5 @@
        sr      1000, [r1]
        sr      100,  [r2]
        sr      r1,[10000]
-       sr      100,[10000]
+       sr      100,[63]
        sr      10000,[100]

diff --git a/gas/testsuite/gas/arc/sub.d b/gas/testsuite/gas/arc/sub.d
index e1c333d..81b5a14 100644 (file)
--- a/gas/testsuite/gas/arc/sub.d
+++ b/gas/testsuite/gas/arc/sub.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 50     50008400     sub        r0,r1,r2
-   4:  00 b8 4d 53     534db800     sub        gp,fp,sp
-   8:  00 3e af 53     53af3e00     sub        ilink1,ilink2,blink
-   c:  00 f8 1d 57     571df800     sub        r56,r59,lp_count
-  10:  00 fe 00 50     5000fe00     sub        r0,r1,0
-  14:  00 84 1f 50     501f8400     sub        r0,0,r2
-  18:  00 84 e0 57     57e08400     sub        0,r1,r2
-  1c:  ff ff 00 50     5000ffff     sub        r0,r1,-1
-  20:  ff 85 1f 50     501f85ff     sub        r0,-1,r2
-  24:  00 84 e0 57     57e08400     sub        0,r1,r2
-  28:  ff fe 00 50     5000feff     sub        r0,r1,255
-  2c:  ff 84 1f 50     501f84ff     sub        r0,255,r2
-  30:  00 84 e0 57     57e08400     sub        0,r1,r2
-  34:  00 ff 00 50     5000ff00     sub        r0,r1,-256
-  38:  00 85 1f 50     501f8500     sub        r0,-256,r2
-  3c:  00 84 e0 57     57e08400     sub        0,r1,r2
-  40:  00 fc 00 50     5000fc00     sub        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 50     501f0400     sub        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 50     501ffcff     sub        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 50     501f7eff     sub        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 50     5000fc00     sub        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 50     50008400     sub        r0,r1,r2
-  6c:  00 0a 62 50     50620a00     sub        r3,r4,r5
-  70:  01 90 c3 50     50c39001     sub.z      r6,r7,r8
-  74:  01 16 25 51     51251601     sub.z      r9,r10,r11
-  78:  02 9c 86 51     51869c02     sub.nz     r12,r13,r14
-  7c:  02 22 e8 51     51e82202     sub.nz     r15,r16,r17
-  80:  03 a8 49 52     5249a803     sub.p      r18,r19,r20
-  84:  03 2e ab 52     52ab2e03     sub.p      r21,r22,r23
-  88:  04 b4 0c 53     530cb404     sub.n      r24,r25,gp
-  8c:  04 3a 6e 53     536e3a04     sub.n      fp,sp,ilink1
-  90:  05 c0 cf 53     53cfc005     sub.c      ilink2,blink,r32
-  94:  05 46 31 54     54314605     sub.c      r33,r34,r35
-  98:  05 cc 92 54     5492cc05     sub.c      r36,r37,r38
-  9c:  06 52 f4 54     54f45206     sub.nc     r39,r40,r41
-  a0:  06 d8 55 55     5555d806     sub.nc     r42,r43,r44
-  a4:  06 5e b7 55     55b75e06     sub.nc     r45,r46,r47
-  a8:  07 e4 18 56     5618e407     sub.v      r48,r49,r50
-  ac:  07 6a 1a 57     571a6a07     sub.v      r56,r52,r53
-  b0:  08 f0 1b 57     571bf008     sub.nv     r56,r55,r56
-  b4:  08 76 1d 57     571d7608     sub.nv     r56,r58,r59
-  b8:  09 00 9e 57     579e0009     sub.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 50     50007c0a     sub.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 50     503f020b     sub.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 50     507f060d     sub.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 57     57df080e     sub.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 57     57c2fc0f     sub.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 50     50008500     sub.f      r0,r1,r2
-  e8:  01 fa 00 50     5000fa01     sub.f      r0,r1,1
-  ec:  01 84 1e 50     501e8401     sub.f      r0,1,r2
-  f0:  00 85 e0 57     57e08500     sub.f      0,r1,r2
-  f4:  00 fd 00 50     5000fd00     sub.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 50     501f0500     sub.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 50     50008501     sub.z.f    r0,r1,r2
- 108:  02 fd 00 50     5000fd02     sub.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 50     501f050b     sub.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 57     57c08509     sub.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 50     5000fd0c     sub.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 50     501f050a     sub.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2102 0080                  sub     r0,r1,r2
+0x[0-9a-f]+ 2302 371a                  sub     gp,fp,sp
+0x[0-9a-f]+ 2602 37dd                  sub     ilink,r30,blink
+0x[0-9a-f]+ 2142 0000                  sub     r0,r1,0
+0x[0-9a-f]+ 2602 7080 0000 0000        sub     r0,0,r2
+0x[0-9a-f]+ 2102 00be                  sub     0,r1,r2
+0x[0-9a-f]+ 2102 0f80 ffff ffff        sub     r0,r1,0xffffffff
+0x[0-9a-f]+ 2602 7080 ffff ffff        sub     r0,0xffffffff,r2
+0x[0-9a-f]+ 2102 0f80 0000 00ff        sub     r0,r1,0xff
+0x[0-9a-f]+ 2602 7080 0000 00ff        sub     r0,0xff,r2
+0x[0-9a-f]+ 2102 0f80 ffff ff00        sub     r0,r1,0xffffff00
+0x[0-9a-f]+ 2602 7080 ffff ff00        sub     r0,0xffffff00,r2
+0x[0-9a-f]+ 2102 0f80 0000 0100        sub     r0,r1,0x100
+0x[0-9a-f]+ 2602 7080 ffff feff        sub     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2602 7f80 0000 0100        sub     r0,0x100,0x100
+0x[0-9a-f]+ 2102 0f80 0000 0000        sub     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c2 0080                  sub     r0,r0,r2
+0x[0-9a-f]+ 23c2 0140                  sub     r3,r3,r5
+0x[0-9a-f]+ 26c2 0201                  sub.eq  r6,r6,r8
+0x[0-9a-f]+ 21c2 12c1                  sub.eq  r9,r9,r11
+0x[0-9a-f]+ 24c2 1382                  sub.ne  r12,r12,r14
+0x[0-9a-f]+ 27c2 1442                  sub.ne  r15,r15,r17
+0x[0-9a-f]+ 22c2 2503                  sub.p   r18,r18,r20
+0x[0-9a-f]+ 25c2 25c3                  sub.p   r21,r21,r23
+0x[0-9a-f]+ 20c2 3684                  sub.n   r24,r24,gp
+0x[0-9a-f]+ 23c2 3744                  sub.n   fp,fp,ilink
+0x[0-9a-f]+ 26c2 37c5                  sub.c   r30,r30,blink
+0x[0-9a-f]+ 23c2 00c5                  sub.c   r3,r3,r3
+0x[0-9a-f]+ 23c2 0205                  sub.c   r3,r3,r8
+0x[0-9a-f]+ 23c2 0106                  sub.nc  r3,r3,r4
+0x[0-9a-f]+ 24c2 0106                  sub.nc  r4,r4,r4
+0x[0-9a-f]+ 24c2 01c6                  sub.nc  r4,r4,r7
+0x[0-9a-f]+ 24c2 0147                  sub.v   r4,r4,r5
+0x[0-9a-f]+ 25c2 0147                  sub.v   r5,r5,r5
+0x[0-9a-f]+ 25c2 0148                  sub.nv  r5,r5,r5
+0x[0-9a-f]+ 25c2 0148                  sub.nv  r5,r5,r5
+0x[0-9a-f]+ 26c2 0009                  sub.gt  r6,r6,r0
+0x[0-9a-f]+ 20c2 002a                  sub.ge  r0,r0,0
+0x[0-9a-f]+ 21c2 006b                  sub.lt  r1,r1,0x1
+0x[0-9a-f]+ 23c2 00ed                  sub.hi  r3,r3,0x3
+0x[0-9a-f]+ 24c2 012e                  sub.ls  r4,r4,0x4
+0x[0-9a-f]+ 25c2 016f                  sub.pnz r5,r5,0x5
+0x[0-9a-f]+ 2102 8080                  sub.f   r0,r1,r2
+0x[0-9a-f]+ 2142 8040                  sub.f   r0,r1,0x1
+0x[0-9a-f]+ 2602 f080 0000 0001        sub.f   r0,0x1,r2
+0x[0-9a-f]+ 2102 80be                  sub.f   0,r1,r2
+0x[0-9a-f]+ 2102 8f80 0000 0200        sub.f   r0,r1,0x200
+0x[0-9a-f]+ 2602 f080 0000 0200        sub.f   r0,0x200,r2
+0x[0-9a-f]+ 21c2 8081                  sub.f.eq        r1,r1,r2
+0x[0-9a-f]+ 20c2 8022                  sub.f.ne        r0,r0,0
+0x[0-9a-f]+ 22c2 808b                  sub.f.lt        r2,r2,r2
+0x[0-9a-f]+ 26c2 f0a9 0000 0001        sub.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 26c2 ff8c 0000 0200        sub.f.le        0,0x200,0x200
+0x[0-9a-f]+ 26c2 f0aa 0000 0200        sub.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/sub.s b/gas/testsuite/gas/arc/sub.s
index 6dd5009..963ae22 100644 (file)
--- a/gas/testsuite/gas/arc/sub.s
+++ b/gas/testsuite/gas/arc/sub.s
@@ -3,55 +3,50 @@
        sub r0,r1,r2
        sub r26,fp,sp
        sub ilink1,ilink2,blink
-       sub r56,r59,lp_count
 
        sub r0,r1,0
        sub r0,0,r2
        sub 0,r1,r2
        sub r0,r1,-1
        sub r0,-1,r2
-       sub -1,r1,r2
        sub r0,r1,255
        sub r0,255,r2
-       sub 255,r1,r2
        sub r0,r1,-256
        sub r0,-256,r2
-       sub -256,r1,r2
 
        sub r0,r1,256
        sub r0,-257,r2
 
-       sub r0,255,256
-       sub r0,256,255
+       sub r0,256,256
 
        sub r0,r1,foo
 
-       sub.al r0,r1,r2
-       sub.ra r3,r4,r5
-       sub.eq r6,r7,r8
-       sub.z r9,r10,r11
-       sub.ne r12,r13,r14
-       sub.nz r15,r16,r17
-       sub.pl r18,r19,r20
-       sub.p r21,r22,r23
-       sub.mi r24,r25,r26
-       sub.n r27,r28,r29
-       sub.cs r30,r31,r32
-       sub.c r33,r34,r35
-       sub.lo r36,r37,r38
-       sub.cc r39,r40,r41
-       sub.nc r42,r43,r44
-       sub.hs r45,r46,r47
-       sub.vs r48,r49,r50
-       sub.v r56,r52,r53
-       sub.vc r56,r55,r56
-       sub.nv r56,r58,r59
-       sub.gt r60,r60,r0
+       sub.al r0,r0,r2
+       sub.ra r3,r3,r5
+       sub.eq r6,r6,r8
+       sub.z  r9,r9,r11
+       sub.ne r12,r12,r14
+       sub.nz r15,r15,r17
+       sub.pl r18,r18,r20
+       sub.p  r21,r21,r23
+       sub.mi r24,r24,r26
+       sub.n  r27,r27,r29
+       sub.cs r30,r30,r31
+       sub.c  r3,r3,r3
+       sub.lo r3,r3,r8
+       sub.cc r3,r3,r4
+       sub.nc r4,r4,r4
+       sub.hs r4,r4,r7
+       sub.vs r4,r4,r5
+       sub.v  r5,r5,r5
+       sub.vc r5,r5,r5
+       sub.nv r5,r5,r5
+       sub.gt r6,r6,r0
        sub.ge r0,r0,0
-       sub.lt r1,1,r1
-       sub.hi r3,3,r3
-       sub.ls 4,4,r4
-       sub.pnz 5,r5,5
+       sub.lt r1,r1,1
+       sub.hi r3,r3,3
+       sub.ls r4,r4,4
+       sub.pnz r5,r5,5
 
        sub.f r0,r1,r2
        sub.f r0,r1,1
@@ -60,9 +55,9 @@
        sub.f r0,r1,512
        sub.f r0,512,r2
 
-       sub.eq.f r0,r1,r2
-       sub.ne.f r0,r1,0
-       sub.lt.f r0,0,r2
-       sub.gt.f 0,r1,r2
-       sub.le.f r0,r1,512
-       sub.ge.f r0,512,r2
+       sub.eq.f r1,r1,r2
+       sub.ne.f r0,r0,0
+       sub.lt.f r2,r2,r2
+       sub.gt.f 0,1,2
+       sub.le.f 0,512,512
+       sub.ge.f 0,512,2

diff --git a/gas/testsuite/gas/arc/swi.d b/gas/testsuite/gas/arc/swi.d
index 58654ec..385f2a3 100644 (file)
--- a/gas/testsuite/gas/arc/swi.d
+++ b/gas/testsuite/gas/arc/swi.d
@@ -1,11 +1,11 @@
-#as: -EL -marc8
-#objdump: -dr -EL
+#as: -mcpu=archs
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
 00000000 <main>:
-   0:  00 84 00 40     40008400     add        r0,r1,r2
-   4:  02 fe ff 1f     1ffffe02     swi        
-   8:  00 0a 62 50     50620a00     sub        r3,r4,r5
+   0:  2100 0080               add     r0,r1,r2
+   4:  226f 003f               swi
+   8:  2402 0143               sub     r3,r4,r5

diff --git a/gas/testsuite/gas/arc/warn.exp b/gas/testsuite/gas/arc/warn.exp
index 3f04853..a94857b 100644 (file)
--- a/gas/testsuite/gas/arc/warn.exp
+++ b/gas/testsuite/gas/arc/warn.exp
@@ -19,6 +19,6 @@
 if [istarget arc*-*-*] {
     load_lib gas-dg.exp
     dg-init
-    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" ""
+    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*warn*.s $srcdir/$subdir/*err*.s]] "" ""
     dg-finish
 }

diff --git a/gas/testsuite/gas/arc/warn.s b/gas/testsuite/gas/arc/warn.s
index 6df1185..e89aa99 100644 (file)
--- a/gas/testsuite/gas/arc/warn.s
+++ b/gas/testsuite/gas/arc/warn.s
@@ -3,14 +3,10 @@
 ; { dg-do assemble { target arc-*-* } }
 
        b.d foo
-       mov r0,256      ; { dg-warning "8 byte instruction in delay slot" "8 byte instruction in delay slot" }
+       mov r0,256      
 
-       j.d foo         ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump instruction with delay slot" }
+       j.d foo         ; { dg-warning "inappropriate arguments for opcode" "inappropriate arguments for opcode" }
        mov r0,r1
 
 foo:
-.extCoreRegister roscreg,45,r,can_shortcut
-.extCoreRegister woscreg,46,w,can_shortcut
-        .section .text
-         add    r0,woscreg,r1   ; { dg-warning "Error: attempt to read writeonly register" }
-         add    roscreg,r1,r2   ; { dg-warning "Error: attempt to set readonly register" }
+

diff --git a/gas/testsuite/gas/arc/xor.d b/gas/testsuite/gas/arc/xor.d
index 46fdedd..6a635a7 100644 (file)
--- a/gas/testsuite/gas/arc/xor.d
+++ b/gas/testsuite/gas/arc/xor.d
@@ -1,85 +1,61 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --prefix-addresses --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
-
-00000000 <.text>:
-   0:  00 84 00 78     78008400     xor        r0,r1,r2
-   4:  00 b8 4d 7b     7b4db800     xor        gp,fp,sp
-   8:  00 3e af 7b     7baf3e00     xor        ilink1,ilink2,blink
-   c:  00 f8 1d 7f     7f1df800     xor        r56,r59,lp_count
-  10:  00 fe 00 78     7800fe00     xor        r0,r1,0
-  14:  00 84 1f 78     781f8400     xor        r0,0,r2
-  18:  00 84 e0 7f     7fe08400     xor        0,r1,r2
-  1c:  ff ff 00 78     7800ffff     xor        r0,r1,-1
-  20:  ff 85 1f 78     781f85ff     xor        r0,-1,r2
-  24:  00 84 e0 7f     7fe08400     xor        0,r1,r2
-  28:  ff fe 00 78     7800feff     xor        r0,r1,255
-  2c:  ff 84 1f 78     781f84ff     xor        r0,255,r2
-  30:  00 84 e0 7f     7fe08400     xor        0,r1,r2
-  34:  00 ff 00 78     7800ff00     xor        r0,r1,-256
-  38:  00 85 1f 78     781f8500     xor        r0,-256,r2
-  3c:  00 84 e0 7f     7fe08400     xor        0,r1,r2
-  40:  00 fc 00 78     7800fc00     xor        r0,r1,0x100
-  44:  00 01 00 00 
-  48:  00 04 1f 78     781f0400     xor        r0,0xffff_feff,r2
-  4c:  ff fe ff ff 
-  50:  ff fc 1f 78     781ffcff     xor        r0,255,0x100
-  54:  00 01 00 00 
-  58:  ff 7e 1f 78     781f7eff     xor        r0,0x100,255
-  5c:  00 01 00 00 
-  60:  00 fc 00 78     7800fc00     xor        r0,r1,0
-  64:  00 00 00 00 
-                       64: R_ARC_32    foo
-  68:  00 84 00 78     78008400     xor        r0,r1,r2
-  6c:  00 0a 62 78     78620a00     xor        r3,r4,r5
-  70:  01 90 c3 78     78c39001     xor.z      r6,r7,r8
-  74:  01 16 25 79     79251601     xor.z      r9,r10,r11
-  78:  02 9c 86 79     79869c02     xor.nz     r12,r13,r14
-  7c:  02 22 e8 79     79e82202     xor.nz     r15,r16,r17
-  80:  03 a8 49 7a     7a49a803     xor.p      r18,r19,r20
-  84:  03 2e ab 7a     7aab2e03     xor.p      r21,r22,r23
-  88:  04 b4 0c 7b     7b0cb404     xor.n      r24,r25,gp
-  8c:  04 3a 6e 7b     7b6e3a04     xor.n      fp,sp,ilink1
-  90:  05 c0 cf 7b     7bcfc005     xor.c      ilink2,blink,r32
-  94:  05 46 31 7c     7c314605     xor.c      r33,r34,r35
-  98:  05 cc 92 7c     7c92cc05     xor.c      r36,r37,r38
-  9c:  06 52 f4 7c     7cf45206     xor.nc     r39,r40,r41
-  a0:  06 d8 55 7d     7d55d806     xor.nc     r42,r43,r44
-  a4:  06 5e b7 7d     7db75e06     xor.nc     r45,r46,r47
-  a8:  07 e4 18 7e     7e18e407     xor.v      r48,r49,r50
-  ac:  07 6a 1a 7f     7f1a6a07     xor.v      r56,r52,r53
-  b0:  08 f0 1b 7f     7f1bf008     xor.nv     r56,r55,r56
-  b4:  08 76 1d 7f     7f1d7608     xor.nv     r56,r58,r59
-  b8:  09 00 9e 7f     7f9e0009     xor.gt     lp_count,lp_count,r0
-  bc:  0a 7c 00 78     78007c0a     xor.ge     r0,r0,0
-  c0:  00 00 00 00 
-  c4:  0b 02 3f 78     783f020b     xor.lt     r1,1,r1
-  c8:  01 00 00 00 
-  cc:  0d 06 7f 78     787f060d     xor.hi     r3,3,r3
-  d0:  03 00 00 00 
-  d4:  0e 08 df 7f     7fdf080e     xor.ls     0,4,r4
-  d8:  04 00 00 00 
-  dc:  0f fc c2 7f     7fc2fc0f     xor.pnz    0,r5,5
-  e0:  05 00 00 00 
-  e4:  00 85 00 78     78008500     xor.f      r0,r1,r2
-  e8:  01 fa 00 78     7800fa01     xor.f      r0,r1,1
-  ec:  01 84 1e 78     781e8401     xor.f      r0,1,r2
-  f0:  00 85 e0 7f     7fe08500     xor.f      0,r1,r2
-  f4:  00 fd 00 78     7800fd00     xor.f      r0,r1,0x200
-  f8:  00 02 00 00 
-  fc:  00 05 1f 78     781f0500     xor.f      r0,0x200,r2
- 100:  00 02 00 00 
- 104:  01 85 00 78     78008501     xor.z.f    r0,r1,r2
- 108:  02 fd 00 78     7800fd02     xor.nz.f   r0,r1,0
- 10c:  00 00 00 00 
- 110:  0b 05 1f 78     781f050b     xor.lt.f   r0,0,r2
- 114:  00 00 00 00 
- 118:  09 85 c0 7f     7fc08509     xor.gt.f   0,r1,r2
- 11c:  00 00 00 00     00000000                
- 120:  0c fd 00 78     7800fd0c     xor.le.f   r0,r1,0x200
- 124:  00 02 00 00 
- 128:  0a 05 1f 78     781f050a     xor.ge.f   r0,0x200,r2
- 12c:  00 02 00 00 
+0x[0-9a-f]+ 2107 0080                  xor     r0,r1,r2
+0x[0-9a-f]+ 2307 371a                  xor     gp,fp,sp
+0x[0-9a-f]+ 2607 37dd                  xor     ilink,r30,blink
+0x[0-9a-f]+ 2147 0000                  xor     r0,r1,0
+0x[0-9a-f]+ 2607 7080 0000 0000        xor     r0,0,r2
+0x[0-9a-f]+ 2107 00be                  xor     0,r1,r2
+0x[0-9a-f]+ 2107 0f80 ffff ffff        xor     r0,r1,0xffffffff
+0x[0-9a-f]+ 2607 7080 ffff ffff        xor     r0,0xffffffff,r2
+0x[0-9a-f]+ 2107 0f80 0000 00ff        xor     r0,r1,0xff
+0x[0-9a-f]+ 2607 7080 0000 00ff        xor     r0,0xff,r2
+0x[0-9a-f]+ 2107 0f80 ffff ff00        xor     r0,r1,0xffffff00
+0x[0-9a-f]+ 2607 7080 ffff ff00        xor     r0,0xffffff00,r2
+0x[0-9a-f]+ 2107 0f80 0000 0100        xor     r0,r1,0x100
+0x[0-9a-f]+ 2607 7080 ffff feff        xor     r0,0xfffffeff,r2
+0x[0-9a-f]+ 2607 7f80 0000 0100        xor     r0,0x100,0x100
+0x[0-9a-f]+ 2107 0f80 0000 0000        xor     r0,r1,0
+                       68: ARC_32_ME   foo
+0x[0-9a-f]+ 20c7 0080                  xor     r0,r0,r2
+0x[0-9a-f]+ 23c7 0140                  xor     r3,r3,r5
+0x[0-9a-f]+ 26c7 0201                  xor.eq  r6,r6,r8
+0x[0-9a-f]+ 21c7 12c1                  xor.eq  r9,r9,r11
+0x[0-9a-f]+ 24c7 1382                  xor.ne  r12,r12,r14
+0x[0-9a-f]+ 27c7 1442                  xor.ne  r15,r15,r17
+0x[0-9a-f]+ 22c7 2503                  xor.p   r18,r18,r20
+0x[0-9a-f]+ 25c7 25c3                  xor.p   r21,r21,r23
+0x[0-9a-f]+ 20c7 3684                  xor.n   r24,r24,gp
+0x[0-9a-f]+ 23c7 3744                  xor.n   fp,fp,ilink
+0x[0-9a-f]+ 26c7 37c5                  xor.c   r30,r30,blink
+0x[0-9a-f]+ 23c7 00c5                  xor.c   r3,r3,r3
+0x[0-9a-f]+ 23c7 0205                  xor.c   r3,r3,r8
+0x[0-9a-f]+ 23c7 0106                  xor.nc  r3,r3,r4
+0x[0-9a-f]+ 24c7 0106                  xor.nc  r4,r4,r4
+0x[0-9a-f]+ 24c7 01c6                  xor.nc  r4,r4,r7
+0x[0-9a-f]+ 24c7 0147                  xor.v   r4,r4,r5
+0x[0-9a-f]+ 25c7 0147                  xor.v   r5,r5,r5
+0x[0-9a-f]+ 25c7 0148                  xor.nv  r5,r5,r5
+0x[0-9a-f]+ 25c7 0148                  xor.nv  r5,r5,r5
+0x[0-9a-f]+ 26c7 0009                  xor.gt  r6,r6,r0
+0x[0-9a-f]+ 20c7 002a                  xor.ge  r0,r0,0
+0x[0-9a-f]+ 21c7 006b                  xor.lt  r1,r1,0x1
+0x[0-9a-f]+ 23c7 00ed                  xor.hi  r3,r3,0x3
+0x[0-9a-f]+ 24c7 012e                  xor.ls  r4,r4,0x4
+0x[0-9a-f]+ 25c7 016f                  xor.pnz r5,r5,0x5
+0x[0-9a-f]+ 2107 8080                  xor.f   r0,r1,r2
+0x[0-9a-f]+ 2147 8040                  xor.f   r0,r1,0x1
+0x[0-9a-f]+ 2607 f080 0000 0001        xor.f   r0,0x1,r2
+0x[0-9a-f]+ 2107 80be                  xor.f   0,r1,r2
+0x[0-9a-f]+ 2107 8f80 0000 0200        xor.f   r0,r1,0x200
+0x[0-9a-f]+ 2607 f080 0000 0200        xor.f   r0,0x200,r2
+0x[0-9a-f]+ 21c7 8081                  xor.f.eq        r1,r1,r2
+0x[0-9a-f]+ 20c7 8022                  xor.f.ne        r0,r0,0
+0x[0-9a-f]+ 22c7 808b                  xor.f.lt        r2,r2,r2
+0x[0-9a-f]+ 26c7 f0a9 0000 0001        xor.f.gt        0,0x1,0x2
+0x[0-9a-f]+ 26c7 ff8c 0000 0200        xor.f.le        0,0x200,0x200
+0x[0-9a-f]+ 26c7 f0aa 0000 0200        xor.f.ge        0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/xor.s b/gas/testsuite/gas/arc/xor.s
index 090107a..56f3c6e 100644 (file)
--- a/gas/testsuite/gas/arc/xor.s
+++ b/gas/testsuite/gas/arc/xor.s
@@ -3,55 +3,50 @@
        xor r0,r1,r2
        xor r26,fp,sp
        xor ilink1,ilink2,blink
-       xor r56,r59,lp_count
 
        xor r0,r1,0
        xor r0,0,r2
        xor 0,r1,r2
        xor r0,r1,-1
        xor r0,-1,r2
-       xor -1,r1,r2
        xor r0,r1,255
        xor r0,255,r2
-       xor 255,r1,r2
        xor r0,r1,-256
        xor r0,-256,r2
-       xor -256,r1,r2
 
        xor r0,r1,256
        xor r0,-257,r2
 
-       xor r0,255,256
-       xor r0,256,255
+       xor r0,256,256
 
        xor r0,r1,foo
 
-       xor.al r0,r1,r2
-       xor.ra r3,r4,r5
-       xor.eq r6,r7,r8
-       xor.z r9,r10,r11
-       xor.ne r12,r13,r14
-       xor.nz r15,r16,r17
-       xor.pl r18,r19,r20
-       xor.p r21,r22,r23
-       xor.mi r24,r25,r26
-       xor.n r27,r28,r29
-       xor.cs r30,r31,r32
-       xor.c r33,r34,r35
-       xor.lo r36,r37,r38
-       xor.cc r39,r40,r41
-       xor.nc r42,r43,r44
-       xor.hs r45,r46,r47
-       xor.vs r48,r49,r50
-       xor.v r56,r52,r53
-       xor.vc r56,r55,r56
-       xor.nv r56,r58,r59
-       xor.gt r60,r60,r0
+       xor.al r0,r0,r2
+       xor.ra r3,r3,r5
+       xor.eq r6,r6,r8
+       xor.z  r9,r9,r11
+       xor.ne r12,r12,r14
+       xor.nz r15,r15,r17
+       xor.pl r18,r18,r20
+       xor.p  r21,r21,r23
+       xor.mi r24,r24,r26
+       xor.n  r27,r27,r29
+       xor.cs r30,r30,r31
+       xor.c  r3,r3,r3
+       xor.lo r3,r3,r8
+       xor.cc r3,r3,r4
+       xor.nc r4,r4,r4
+       xor.hs r4,r4,r7
+       xor.vs r4,r4,r5
+       xor.v  r5,r5,r5
+       xor.vc r5,r5,r5
+       xor.nv r5,r5,r5
+       xor.gt r6,r6,r0
        xor.ge r0,r0,0
-       xor.lt r1,1,r1
-       xor.hi r3,3,r3
-       xor.ls 4,4,r4
-       xor.pnz 5,r5,5
+       xor.lt r1,r1,1
+       xor.hi r3,r3,3
+       xor.ls r4,r4,4
+       xor.pnz r5,r5,5
 
        xor.f r0,r1,r2
        xor.f r0,r1,1
@@ -60,9 +55,9 @@
        xor.f r0,r1,512
        xor.f r0,512,r2
 
-       xor.eq.f r0,r1,r2
-       xor.ne.f r0,r1,0
-       xor.lt.f r0,0,r2
-       xor.gt.f 0,r1,r2
-       xor.le.f r0,r1,512
-       xor.ge.f r0,512,r2
+       xor.eq.f r1,r1,r2
+       xor.ne.f r0,r0,0
+       xor.lt.f r2,r2,r2
+       xor.gt.f 0,1,2
+       xor.le.f 0,512,512
+       xor.ge.f 0,512,2

diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp
index 496e01a..fc81da1 100644 (file)
--- a/gas/testsuite/gas/elf/elf.exp
+++ b/gas/testsuite/gas/elf/elf.exp
@@ -90,6 +90,7 @@ if { [is_elf_format] } then {
     # optimization because it interfers with link-time relaxation of
     # function prologues.
     if {![istarget "mn10300-*-*"]
+       && ![istarget "arc-*-*"]
        && ![istarget "xtensa*-*-*"]
        && ![istarget "msp430*-*-*"]
        && ![istarget "nds32*-*-*"]
@@ -148,7 +149,7 @@ if { [is_elf_format] } then {
            # against ordinary symbols into relocations against section symbols.
            # This is usually revealed by the error message:
            #  symbol `sym' required but not present
-       setup_xfail "m681*-*-*" "m68hc*-*-*"
+       setup_xfail "m681*-*-*" "m68hc*-*-*" "arc-*-*"
            run_dump_test redef
            run_dump_test equ-reloc
        }

diff --git a/include/ChangeLog b/include/ChangeLog
index e4914ed..5301696 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * dis-asm.h (arc_get_disassembler): Correct declaration.
+
 2015-09-30  Nick Clifton  <nickc@redhat.com>
 
        Import the following patches from the GCC mainline:

diff --git a/include/dis-asm.h b/include/dis-asm.h
index ebc2604..f82149b 100644 (file)
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -319,7 +319,7 @@ extern int print_insn_rl78_g10              (bfd_vma, disassemble_info *);
 extern int print_insn_rl78_g13         (bfd_vma, disassemble_info *);
 extern int print_insn_rl78_g14         (bfd_vma, disassemble_info *);
 
-extern disassembler_ftype arc_get_disassembler (void *);
+extern disassembler_ftype arc_get_disassembler (bfd *);
 extern disassembler_ftype cris_get_disassembler (bfd *);
 extern disassembler_ftype rl78_get_disassembler (bfd *);
 

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 8e6bb44..5e4605d 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,12 @@
+2015-10-07  Cupertino Miranda  <cmiranda@synopsys.com>
+
+       * arc-reloc.def: Macro file with definition of all relocation
+       types.
+       * arc.h: Changed macros for the newly supported ARC cpus.  Altered
+       enum defining the supported relocations.
+       * common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
+       macro for EM_ARC_COMPACT2.
+
 2015-09-22  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        * common.h (DF_1_STUB, DF_1_PIE): Define.

diff --git a/include/elf/arc-reloc.def b/include/elf/arc-reloc.def
new file mode 100644 (file)
index 0000000..e2ff871
--- /dev/null
+++ b/include/elf/arc-reloc.def
@@ -0,0 +1,456 @@
+
+ARC_RELOC_HOWTO(ARC_NONE, 0, \
+                2, \
+                32, \
+                replace_none, \
+                bitfield, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_8, 1, \
+                0, \
+                8, \
+                replace_bits8, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_16, 2, \
+                1, \
+                16, \
+                replace_bits16, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_24, 3, \
+                2, \
+                24, \
+                replace_bits24, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_32, 4, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_N8, 8, \
+                0, \
+                8, \
+                replace_bits8, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_N16, 9, \
+                1, \
+                16, \
+                replace_bits16, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_N24, 10, \
+                2, \
+                24, \
+                replace_bits24, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_N32, 11, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_SDA, 12, \
+                2, \
+                9, \
+                replace_disp9, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF, 13, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( S - SECTSTART ) + A ))
+
+ARC_RELOC_HOWTO(ARC_S21H_PCREL, 14, \
+                2, \
+                20, \
+                replace_disp21h, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_S21W_PCREL, 15, \
+                2, \
+                19, \
+                replace_disp21w, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S25H_PCREL, 16, \
+                2, \
+                24, \
+                replace_disp25h, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_S25W_PCREL, 17, \
+                2, \
+                23, \
+                replace_disp25w, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SDA32, 18, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST, 19, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST1, 20, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST2, 21, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_LD, 22, \
+                1, \
+                9, \
+                replace_disp9s, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_LD1, 23, \
+                1, \
+                9, \
+                replace_disp9s, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_LD2, 24, \
+                1, \
+                9, \
+                replace_disp9s, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S13_PCREL, 25, \
+                1, \
+                11, \
+                replace_disp13s, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_W, 26, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( S + A ) & ( ~3 ) ))
+
+ARC_RELOC_HOWTO(ARC_32_ME, 27, \
+                2, \
+                32, \
+                replace_limm, \
+                signed, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_32_ME_S, 105, \
+                2, \
+                32, \
+                replace_limms, \
+                signed, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_N32_ME, 28, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_ME, 29, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( S - SECTSTART ) + A ))
+
+ARC_RELOC_HOWTO(ARC_SDA32_ME, 30, \
+                2, \
+                32, \
+                replace_limm, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_W_ME, 31, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(AC_SECTOFF_U8, 35, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( S + A ) - SECTSTART ))
+
+ARC_RELOC_HOWTO(AC_SECTOFF_U8_1, 36, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 1 ))
+
+ARC_RELOC_HOWTO(AC_SECTOFF_U8_2, 37, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 2 ))
+
+ARC_RELOC_HOWTO(AC_SECTFOFF_S9, 38, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( S + A ) - SECTSTART ))
+
+ARC_RELOC_HOWTO(AC_SECTFOFF_S9_1, 39, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 1 ))
+
+ARC_RELOC_HOWTO(AC_SECTFOFF_S9_2, 40, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_ME_1, 41, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_ME_2, 42, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_1, 43, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_2, 44, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_ST2, 48, \
+                1, \
+                9, \
+                replace_disp9s1, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_PC32, 50, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( S + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_GOT32, 59, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                ( G + A ))
+
+ARC_RELOC_HOWTO(ARC_GOTPC32, 51, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( ( GOT + G ) + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_PLT32, 52, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( L + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_COPY, 53, \
+                2, \
+                0, \
+                replace_none, \
+                signed, \
+                none)
+
+ARC_RELOC_HOWTO(ARC_GLOB_DAT, 54, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                S)
+
+ARC_RELOC_HOWTO(ARC_JMP_SLOT, 55, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                S)
+
+ARC_RELOC_HOWTO(ARC_RELATIVE, 56, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( B + A ))
+
+ARC_RELOC_HOWTO(ARC_GOTOFF, 57, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( S + A ) - GOT ))
+
+ARC_RELOC_HOWTO(ARC_GOTPC, 58, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( GOT + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_S21W_PCREL_PLT, 60, \
+                2, \
+                19, \
+                replace_disp21w, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S25H_PCREL_PLT, 61, \
+                2, \
+                24, \
+                replace_disp25h, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_TLS_DTPMOD, 66, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_DTPOFF, 67, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_TPOFF, 68, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_GD_GOT, 69, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_GD_LD, 70, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_GD_CALL, 71, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_IE_GOT, 72, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_DTPOFF_S9, 73, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_LE_S9, 74, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_LE_32, 75, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_S25W_PCREL_PLT, 76, \
+                2, \
+                23, \
+                replace_disp25w, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S21H_PCREL_PLT, 77, \
+                2, \
+                20, \
+                replace_disp21h, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 1 ))
+

diff --git a/include/elf/arc.h b/include/elf/arc.h
index 62398e1..707aeb4 100644 (file)
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -28,25 +28,41 @@
 
 /* Relocations.  */
 
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  RELOC_NUMBER(R_##TYPE, VALUE)
+
 START_RELOC_NUMBERS (elf_arc_reloc_type)
-  RELOC_NUMBER (R_ARC_NONE, 0)
-  RELOC_NUMBER (R_ARC_32, 1)
-  RELOC_NUMBER (R_ARC_B26, 2)
-  RELOC_NUMBER (R_ARC_B22_PCREL, 3)
+#include "arc-reloc.def"
 END_RELOC_NUMBERS (R_ARC_max)
 
+#undef ARC_RELOC_HOWTO
+
 /* Processor specific flags for the ELF header e_flags field.  */
 
 /* Four bit ARC machine type field.  */
+#define EF_ARC_MACH_MSK         0x000000ff
+#define EF_ARC_OSABI_MSK 0x00000f00
+#define EF_ARC_ALL_MSK  (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK)
+
+/* Four bit ARC machine type field.  */
 
 #define EF_ARC_MACH 0x0000000f
 
 /* Various CPU types.  */
+#define E_ARC_MACH_ARC600      0x00000002
+#define E_ARC_MACH_ARC601      0x00000004
+#define E_ARC_MACH_ARC700      0x00000003
 
-#define E_ARC_MACH_ARC5 0
-#define E_ARC_MACH_ARC6 1      
-#define E_ARC_MACH_ARC7 2
-#define E_ARC_MACH_ARC8 3
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARC_CPU_GENERIC      0x00000000
+#define EF_ARC_CPU_ARCV2EM      0x00000005
+#define EF_ARC_CPU_ARCV2HS      0x00000006
+
+/* ARC Linux specific ABIs.  */
+#define E_ARC_OSABI_ORIG       0x00000000   /* MUST be 0 for back-compat.  */
+#define E_ARC_OSABI_V2         0x00000200
+#define E_ARC_OSABI_V3         0x00000300
+#define E_ARC_OSABI_CURRENT    E_ARC_OSABI_V3
 
 /* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.  */
 

diff --git a/include/elf/common.h b/include/elf/common.h
index fbf1f3c..bb15b7d 100644 (file)
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -194,7 +194,7 @@
 #define EM_MN10200      90     /* Matsushita MN10200 */
 #define EM_PJ           91     /* picoJava */
 #define EM_OR1K                 92     /* OpenRISC 1000 32-bit embedded processor */
-#define EM_ARC_A5       93     /* ARC Cores Tangent-A5 */
+#define EM_ARC_COMPACT  93     /* ARC International ARCompact processor */
 #define EM_XTENSA       94     /* Tensilica Xtensa Architecture */
 #define EM_VIDEOCORE    95     /* Alphamosaic VideoCore processor */
 #define EM_TMM_GPP      96     /* Thompson Multimedia General Purpose Processor */
@@ -295,6 +295,7 @@
 #define EM_MICROBLAZE  189     /* Xilinx MicroBlaze 32-bit RISC soft processor core */
 #define EM_CUDA                190     /* NVIDIA CUDA architecture */
 #define EM_TILEGX      191     /* Tilera TILE-Gx multicore architecture family */
+#define EM_ARC_COMPACT2 195    /* Synopsys ARCompact V2 */
 #define EM_RL78                197     /* Renesas RL78 family.  */
 #define EM_78K0R       199     /* Renesas 78K0R.  */
 #define EM_INTEL205    205     /* Reserved by Intel */

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index a7e9895..63fe454 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+            Cupertino Miranda  <cmiranda@synopsys.com>
+
+        * arc-func.h: New file.
+        * arc.h: Likewise.
+
 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 
        * aarch64.h (aarch64_zero_register_p): Move the declaration

diff --git a/include/opcode/arc-func.h b/include/opcode/arc-func.h
new file mode 100644 (file)
index 0000000..faffcb5
--- /dev/null
+++ b/include/opcode/arc-func.h
@@ -0,0 +1,236 @@
+/* Replace functions for the ARC relocs.
+   Copyright 2015
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+   the GNU Binutils.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* mask  = 00000000000000000000000000000000.  */
+#ifndef REPLACE_none
+#define REPLACE_none
+ATTRIBUTE_UNUSED static unsigned
+replace_none (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+
+  return insn;
+}
+
+#endif /* REPLACE_none */
+
+/* mask  = 11111111.  */
+#ifndef REPLACE_bits8
+#define REPLACE_bits8
+ATTRIBUTE_UNUSED static unsigned
+replace_bits8 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x00ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_bits8 */
+
+/* mask  = 1111111111111111.  */
+#ifndef REPLACE_bits16
+#define REPLACE_bits16
+ATTRIBUTE_UNUSED static unsigned
+replace_bits16 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_bits16 */
+
+/* mask  = 111111111111111111111111.  */
+#ifndef REPLACE_bits24
+#define REPLACE_bits24
+ATTRIBUTE_UNUSED static unsigned
+replace_bits24 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_bits24 */
+
+/* mask  = 11111111111111111111111111111111.  */
+#ifndef REPLACE_word32
+#define REPLACE_word32
+ATTRIBUTE_UNUSED static unsigned
+replace_word32 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_word32 */
+
+/* mask  = 0000000000000000000000000000000011111111111111111111111111111111.  */
+#ifndef REPLACE_limm
+#define REPLACE_limm
+ATTRIBUTE_UNUSED static unsigned
+replace_limm (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_limm */
+
+/* mask  = 000000000000000011111111111111111111111111111111.  */
+#ifndef REPLACE_limms
+#define REPLACE_limms
+ATTRIBUTE_UNUSED static unsigned
+replace_limms (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_limms */
+
+/* mask  = 00000111111111102222222222000000.  */
+#ifndef REPLACE_disp21h
+#define REPLACE_disp21h
+ATTRIBUTE_UNUSED static unsigned
+replace_disp21h (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x03ff) << 17;
+  insn |= ((value >> 10) & 0x03ff) << 6;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp21h */
+
+/* mask  = 00000111111111002222222222000000.  */
+#ifndef REPLACE_disp21w
+#define REPLACE_disp21w
+ATTRIBUTE_UNUSED static unsigned
+replace_disp21w (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 18;
+  insn |= ((value >> 9) & 0x03ff) << 6;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp21w */
+
+/* mask  = 00000111111111102222222222003333.  */
+#ifndef REPLACE_disp25h
+#define REPLACE_disp25h
+ATTRIBUTE_UNUSED static unsigned
+replace_disp25h (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x03ff) << 17;
+  insn |= ((value >> 10) & 0x03ff) << 6;
+  insn |= ((value >> 20) & 0x000f) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp25h */
+
+/* mask  = 00000111111111002222222222003333.  */
+#ifndef REPLACE_disp25w
+#define REPLACE_disp25w
+ATTRIBUTE_UNUSED static unsigned
+replace_disp25w (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 18;
+  insn |= ((value >> 9) & 0x03ff) << 6;
+  insn |= ((value >> 19) & 0x000f) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp25w */
+
+/* mask  = 00000000000000000000000111111111.  */
+#ifndef REPLACE_disp9
+#define REPLACE_disp9
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9 */
+
+/* mask  = 00000000111111112000000000000000.  */
+#ifndef REPLACE_disp9ls
+#define REPLACE_disp9ls
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9ls (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x00ff) << 16;
+  insn |= ((value >> 8) & 0x0001) << 15;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9ls */
+
+/* mask  = 0000000111111111.  */
+#ifndef REPLACE_disp9s
+#define REPLACE_disp9s
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9s */
+
+/* mask  = 0000011111111111.  */
+#ifndef REPLACE_disp13s
+#define REPLACE_disp13s
+ATTRIBUTE_UNUSED static unsigned
+replace_disp13s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x07ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp13s */
+
+/* mask  = 0000022222200111.  */
+#ifndef REPLACE_disp9s1
+#define REPLACE_disp9s1
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9s1 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x0007) << 0;
+  insn |= ((value >> 3) & 0x003f) << 5;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9s1 */

diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 907e4fb..3dbc541 100644 (file)
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -1,6 +1,7 @@
 /* Opcode table for the ARC.
-   Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+   Copyright 1994-2015 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
    the GNU Binutils.
@@ -12,7 +13,7 @@
 
    GAS/GDB is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.        See the
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
@@ -20,302 +21,393 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-/* List of the various cpu types.
-   The tables currently use bit masks to say whether the instruction or
-   whatever is supported by a particular cpu.  This lets us have one entry
-   apply to several cpus.
+#ifndef OPCODE_ARC_H
+#define OPCODE_ARC_H
+
+#define MAX_INSN_ARGS       6
+#define MAX_INSN_FLGS       3
+
+/* Instruction Class.  */
+typedef enum
+  {
+    ARITH,
+    AUXREG,
+    BRANCH,
+    CONTROL,
+    DSP,
+    FLOAT,
+    INVALID,
+    JUMP,
+    KERNEL,
+    LOGICAL,
+    MEMORY,
+  } insn_class_t;
+
+/* Instruction Subclass.  */
+typedef enum
+  {
+    NONE,
+    CVT,
+    BTSCN,
+    CD1,
+    CD2,
+    DIV,
+    DP,
+    MPY1E,
+    MPY6E,
+    MPY7E,
+    MPY8E,
+    MPY9E,
+    SHFT1,
+    SHFT2,
+    SWAP,
+    SP
+  } insn_subclass_t;
+
+/* Flags class.  */
+typedef enum
+  {
+    FNONE,
+    CND,  /* Conditional flags.  */
+    WBM,  /* Write-back modes.  */
+    FLG,  /* F Flag.  */
+    SBP,  /* Static branch prediction.  */
+    DLY,  /* Delay slot.  */
+    DIF,  /* Bypass caches.  */
+    SGX,  /* Sign extend modes.  */
+    SZM   /* Data size modes.  */
+  } flag_class_t;
+
+/* The opcode table is an array of struct arc_opcode.  */
+struct arc_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned mask;
+
+  /* One bit flags for the opcode.  These are primarily used to
+     indicate specific processors and environments support the
+     instructions.  The defined values are listed below.  */
+  unsigned cpu;
+
+  /* The instruction class.  This is used by gdb.  */
+  insn_class_t class;
+
+  /* The instruction subclass.  */
+  insn_subclass_t subclass;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[MAX_INSN_ARGS + 1];
+
+  /* An array of flag codes.  Each code is an index into the flag
+     table.  They appear in the order which the flags must appear in
+     assembly code, and are terminated by a zero.  */
+  unsigned char flags[MAX_INSN_FLGS + 1];
+};
 
-   The `base' cpu must be 0. The cpu type is treated independently of
-   endianness. The complete `mach' number includes endianness.
-   These values are internal to opcodes/bfd/binutils/gas.  */
-#define ARC_MACH_5 0
-#define ARC_MACH_6 1
-#define ARC_MACH_7 2
-#define ARC_MACH_8 4
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct arc_opcode arc_opcodes[];
+extern const unsigned arc_num_opcodes;
+
+/* CPU Availability.  */
+#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
+#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
+#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
+#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
+
+/* CPU extensions.  */
+#define ARC_EA       0x0001
+#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
+#define ARC_LLOCK    0x0002
+#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
+#define ARC_MPY      0x0004
+#define ARC_MULT     0x0004
+
+/* Floating point support.  */
+#define ARC_DPFP     0x0010
+#define ARC_SPFP     0x0020
+#define ARC_FPU      0x0030
+
+/* NORM & SWAP.  */
+#define ARC_SWAP     0x0100
+#define ARC_NORM     0x0200
+#define ARC_BSCAN    0x0200
+
+/* A7 specific.  */
+#define ARC_UIX      0x1000
+#define ARC_TSTAMP   0x1000
+
+/* A6 specific.  */
+#define ARC_VBFDW    0x1000
+#define ARC_BARREL   0x1000
+#define ARC_DSPA     0x1000
+
+/* EM specific.  */
+#define ARC_SHIFT    0x1000
+
+/* V2 specific.  */
+#define ARC_INTR     0x1000
+#define ARC_DIV      0x1000
+
+/* V1 specific.  */
+#define ARC_XMAC     0x1000
+#define ARC_CRC      0x1000
+
+/* Base architecture -- all cpus.  */
+#define ARC_OPCODE_BASE                                \
+  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
+   | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+
+/* A macro to check for short instructions.  */
+#define ARC_SHORT(mask)                                \
+  (((mask) & 0xFFFF0000) ? 0 : 1)
+
+/* The operands table is an array of struct arc_operand.  */
+struct arc_operand
+{
+  /* The number of bits in the operand.  */
+  unsigned int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  unsigned int shift;
+
+  /* The default relocation type for this operand.  */
+  signed int default_reloc;
+
+  /* One bit syntax flags.  */
+  unsigned int flags;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+        i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.         It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).         If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+        op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+        if ((o->flags & ARC_OPERAND_SIGNED) != 0
+            && (op & (1 << (o->bits - 1))) != 0)
+          op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.         It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     TRUE if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  int (*extract) (unsigned instruction, bfd_boolean *invalid);
+};
 
-/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
-#define ARC_MACH_BIG 16
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the arc_opcodes table.  */
+extern const struct arc_operand arc_operands[];
+extern const unsigned arc_num_operands;
+extern const unsigned arc_Toperand;
+extern const unsigned arc_NToperand;
 
-/* Mask of number of bits necessary to record cpu type.  */
-#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
+/* Values defined for the flags field of a struct arc_operand.  */
 
-/* Mask of number of bits necessary to record cpu type + endianness.  */
-#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
+/* This operand does not actually exist in the assembler input.  This
+   is used to support extended mnemonics, for which two operands fields
+   are identical.  The assembler should call the insert function with
+   any op value.  The disassembler should call the extract function,
+   ignore the return value, and check the value placed in the invalid
+   argument.  */
+#define ARC_OPERAND_FAKE       0x0001
 
-/* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
+/* This operand names an integer register.  */
+#define ARC_OPERAND_IR         0x0002
 
-typedef unsigned int arc_insn;
+/* This operand takes signed values.  */
+#define ARC_OPERAND_SIGNED     0x0004
 
-struct arc_opcode {
-  char *syntax;              /* syntax of insn  */
-  unsigned long mask, value; /* recognize insn if (op&mask) == value  */
-  int flags;                 /* various flag bits  */
+/* This operand takes unsigned values.  This exists primarily so that
+   a flags value of 0 can be treated as end-of-arguments.  */
+#define ARC_OPERAND_UNSIGNED   0x0008
 
-/* Values for `flags'.  */
+/* This operand takes long immediate values.  */
+#define ARC_OPERAND_LIMM       0x0010
 
-/* Return CPU number, given flag bits.  */
-#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* This operand is identical like the previous one.  */
+#define ARC_OPERAND_DUPLICATE   0x0020
 
-/* Return MACH number, given flag bits.  */
-#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
+/* This operand is PC relative.  Used for internal relocs.  */
+#define ARC_OPERAND_PCREL       0x0040
 
-/* First opcode flag bit available after machine mask.  */
-#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
+/* This operand is truncated.  The truncation is done accordingly to
+   operand alignment attribute.  */
+#define ARC_OPERAND_TRUNCATE    0x0080
 
-/* This insn is a conditional branch.  */
-#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
-#define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
-#define SYNTAX_LENGTH          (SYNTAX_3OP                 )
-#define SYNTAX_2OP             (SYNTAX_3OP             << 1)
-#define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
-#define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
-#define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
+/* This operand is 16bit aligned.  */
+#define ARC_OPERAND_ALIGNED16   0x0100
 
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
+/* This operand is 32bit aligned.  */
+#define ARC_OPERAND_ALIGNED32   0x0200
 
-/* These values are used to optimize assembly and disassembly.  Each insn
-   is on a list of related insns (same first letter for assembly, same
-   insn code for disassembly).  */
+/* This operand can be ignored by matching process if it is not
+   present.  */
+#define ARC_OPERAND_IGNORE      0x0400
 
-  struct arc_opcode *next_asm; /* Next instr to try during assembly.  */
-  struct arc_opcode *next_dis; /* Next instr to try during disassembly.  */
+/* Don't check the range when matching.         */
+#define ARC_OPERAND_NCHK       0x0800
 
-/* Macros to create the hash values for the lists.  */
-#define ARC_HASH_OPCODE(string) \
-  ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
-#define ARC_HASH_ICODE(insn) \
-  ((unsigned int) (insn) >> 27)
+/* Mark the braket possition.  */
+#define ARC_OPERAND_BRAKET      0x1000
 
- /* Macros to access `next_asm', `next_dis' so users needn't care about the
-    underlying mechanism.  */
-#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
-#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
-};
+/* Mask for selecting the type for typecheck purposes.  */
+#define ARC_OPERAND_TYPECHECK_MASK             \
+  (ARC_OPERAND_IR |                            \
+   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED |     \
+   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 
-/* this is an "insert at front" linked list per Metaware spec
-   that new definitions override older ones.  */
-extern struct arc_opcode *arc_ext_opcodes;
+/* The flags structure.  */
+struct arc_flag_operand
+{
+  /* The flag name.  */
+  const char *name;
 
-struct arc_operand_value {
-  char *name;          /* eg: "eq"  */
-  short value;         /* eg: 1  */
-  unsigned char type;  /* index into `arc_operands'  */
-  unsigned char flags; /* various flag bits  */
+  /* The flag code.  */
+  unsigned code;
 
-/* Values for `flags'.  */
+  /* The number of bits in the operand.  */
+  unsigned int bits;
 
-/* Return CPU number, given flag bits.  */
-#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
-/* Return MACH number, given flag bits.  */
-#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
-};
+  /* How far the operand is left shifted in the instruction.  */
+  unsigned int shift;
 
-struct arc_ext_operand_value {
-  struct arc_ext_operand_value *next;
-  struct arc_operand_value operand;
+  /* Available for disassembler.  */
+  unsigned char favail;
 };
 
-extern struct arc_ext_operand_value *arc_ext_operands;
+/* The flag operands table.  */
+extern const struct arc_flag_operand arc_flag_operands[];
+extern const unsigned arc_num_flag_operands;
 
-struct arc_operand {
-/* One of the insn format chars.  */
-  unsigned char fmt;
+/* The flag's class structure.  */
+struct arc_flag_class
+{
+  /* Flag class.  */
+  flag_class_t class;
 
-/* The number of bits in the operand (may be unused for a modifier).  */
-  unsigned char bits;
+  /* List of valid flags (codes).  */
+  unsigned flags[256];
+};
 
-/* How far the operand is left shifted in the instruction, or
-   the modifier's flag bit (may be unused for a modifier.  */
-  unsigned char shift;
+extern const struct arc_flag_class arc_flag_classes[];
 
-/* Various flag bits.  */
-  int flags;
+/* Structure for special cases.  */
+struct arc_flag_special
+{
+  /* Name of special case instruction.  */
+  const char *name;
 
-/* Values for `flags'.  */
+  /* List of flags applicable for special case instruction.  */
+  unsigned flags[32];
+};
 
-/* This operand is a suffix to the opcode.  */
-#define ARC_OPERAND_SUFFIX 1
+extern const struct arc_flag_special arc_flag_special_cases[];
+extern const unsigned arc_num_flag_special;
+
+/* Relocation equivalence structure.  */
+struct arc_reloc_equiv_tab
+{
+  const char * name;      /* String to lookup.  */
+  const char * mnemonic;   /* Extra matching condition.  */
+  unsigned     flagcode;   /* Extra matching condition.  */
+  signed int   oldreloc;   /* Old relocation.  */
+  signed int   newreloc;   /* New relocation.  */
+};
 
-/* This operand is a relative branch displacement.  The disassembler
-   prints these symbolically if possible.  */
-#define ARC_OPERAND_RELATIVE_BRANCH 2
+extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
+extern const unsigned arc_num_equiv_tab;
 
-/* This operand is an absolute branch address.  The disassembler
-   prints these symbolically if possible.  */
-#define ARC_OPERAND_ABSOLUTE_BRANCH 4
+/* Structure for operand operations for pseudo/alias instructions.  */
+struct arc_operand_operation
+{
+  /* The index for operand from operand array.  */
+  unsigned operand_idx;
 
-/* This operand is an address.  The disassembler
-   prints these symbolically if possible.  */
-#define ARC_OPERAND_ADDRESS 8
+  /* Defines if it needs the operand inserted by the assembler or
+     whether this operand comes from the pseudo instruction's
+     operands.  */
+  unsigned char needs_insert;
 
-/* This operand is a long immediate value.  */
-#define ARC_OPERAND_LIMM 0x10
+  /* Count we have to add to the operand.  Use negative number to
+     subtract from the operand.  Also use this number to add to 0 if
+     the operand needs to be inserted (i.e. needs_insert == 1).  */
+  int count;
 
-/* This operand takes signed values.  */
-#define ARC_OPERAND_SIGNED 0x20
-
-/* This operand takes signed values, but also accepts a full positive
-   range of values.  That is, if bits is 16, it takes any value from
-   -0x8000 to 0xffff.  */
-#define ARC_OPERAND_SIGNOPT 0x40
-
-/* This operand should be regarded as a negative number for the
-   purposes of overflow checking (i.e., the normal most negative
-   number is disallowed and one more than the normal most positive
-   number is allowed).  This flag will only be set for a signed
-   operand.  */
-#define ARC_OPERAND_NEGATIVE 0x80
-
-/* This operand doesn't really exist.  The program uses these operands
-   in special ways.  */
-#define ARC_OPERAND_FAKE 0x100
-
-/* separate flags operand for j and jl instructions  */
-#define ARC_OPERAND_JUMPFLAGS 0x200
-
-/* allow warnings and errors to be issued after call to insert_xxxxxx  */
-#define ARC_OPERAND_WARN  0x400
-#define ARC_OPERAND_ERROR 0x800
-
-/* this is a load operand */
-#define ARC_OPERAND_LOAD  0x8000
-
-/* this is a store operand */
-#define ARC_OPERAND_STORE 0x10000
-
-/* Modifier values.  */
-/* A dot is required before a suffix.  Eg: .le  */
-#define ARC_MOD_DOT 0x1000
-
-/* A normal register is allowed (not used, but here for completeness).  */
-#define ARC_MOD_REG 0x2000
-
-/* An auxiliary register name is expected.  */
-#define ARC_MOD_AUXREG 0x4000
-
-/* Sum of all ARC_MOD_XXX bits.  */
-#define ARC_MOD_BITS 0x7000
-
-/* Non-zero if the operand type is really a modifier.  */
-#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
-
-/* enforce read/write only register restrictions  */
-#define ARC_REGISTER_READONLY    0x01
-#define ARC_REGISTER_WRITEONLY   0x02
-#define ARC_REGISTER_NOSHORT_CUT 0x04
-
-/* Insertion function.  This is used by the assembler.  To insert an
-   operand value into an instruction, check this field.
-
-   If it is NULL, execute
-   i |= (p & ((1 << o->bits) - 1)) << o->shift;
-   (I is the instruction which we are filling in, O is a pointer to
-   this structure, and OP is the opcode value; this assumes twos
-   complement arithmetic).
-   
-   If this field is not NULL, then simply call it with the
-   instruction and the operand value.  It will return the new value
-   of the instruction.  If the ERRMSG argument is not NULL, then if
-   the operand value is illegal, *ERRMSG will be set to a warning
-   string (the operand will be inserted in any case).  If the
-   operand value is legal, *ERRMSG will be unchanged.
-
-   REG is non-NULL when inserting a register value.  */
-
-  arc_insn (*insert)
-    (arc_insn insn, const struct arc_operand *operand, int mods,
-     const struct arc_operand_value *reg, long value, const char **errmsg);
-
-/* Extraction function.  This is used by the disassembler.  To
-   extract this operand type from an instruction, check this field.
-   
-   If it is NULL, compute
-     op = ((i) >> o->shift) & ((1 << o->bits) - 1);
-     if ((o->flags & ARC_OPERAND_SIGNED) != 0
-          && (op & (1 << (o->bits - 1))) != 0)
-       op -= 1 << o->bits;
-   (I is the instruction, O is a pointer to this structure, and OP
-   is the result; this assumes twos complement arithmetic).
-   
-   If this field is not NULL, then simply call it with the
-   instruction value.  It will return the value of the operand.  If
-   the INVALID argument is not NULL, *INVALID will be set to
-   non-zero if this operand type can not actually be extracted from
-   this operand (i.e., the instruction does not match).  If the
-   operand is valid, *INVALID will not be changed.
-
-   INSN is a pointer to an array of two `arc_insn's.  The first element is
-   the insn, the second is the limm if present.
-
-   Operands that have a printable form like registers and suffixes have
-   their struct arc_operand_value pointer stored in OPVAL.  */
-
-  long (*extract)
-    (arc_insn *insn, const struct arc_operand *operand, int mods,
-     const struct arc_operand_value **opval, int *invalid);
+  /* Index of the operand to swap with.  To be done AFTER applying
+     inc_count.  */
+  unsigned swap_operand_idx;
 };
 
-/* Bits that say what version of cpu we have. These should be passed to
-   arc_init_opcode_tables. At present, all there is is the cpu type.  */
+/* Structure for pseudo/alias instructions.  */
+struct arc_pseudo_insn
+{
+  /* Mnemonic for pseudo/alias insn.  */
+  const char *mnemonic_p;
 
-/* CPU number, given value passed to `arc_init_opcode_tables'.  */
-#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
-/* MACH number, given value passed to `arc_init_opcode_tables'.  */
-#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
+  /* Mnemonic for real instruction.  */
+  const char *mnemonic_r;
 
-/* Special register values:  */
-#define ARC_REG_SHIMM_UPDATE 61
-#define ARC_REG_SHIMM 63
-#define ARC_REG_LIMM 62
+  /* Flag that will have to be added (if any).  */
+  const char *flag_r;
 
-/* Non-zero if REG is a constant marker.  */
-#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
+  /* Amount of operands.  */
+  unsigned operand_cnt;
 
-/* Positions and masks of various fields:  */
-#define ARC_SHIFT_REGA 21
-#define ARC_SHIFT_REGB 15
-#define ARC_SHIFT_REGC 9
-#define ARC_MASK_REG 63
+  /* Array of operand operations.  */
+  struct arc_operand_operation operand[6];
+};
 
-/* Delay slot types.  */
-#define ARC_DELAY_NONE 0   /* no delay slot */
-#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
-#define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
+extern const struct arc_pseudo_insn arc_pseudo_insns[];
+extern const unsigned arc_num_pseudo_insn;
 
-/* Non-zero if X will fit in a signed 9 bit field.  */
-#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
+/* Structure for AUXILIARY registers.  */
+struct arc_aux_reg
+{
+  /* Register address.  */
+  int address;
 
-extern const struct arc_operand arc_operands[];
-extern const int arc_operand_count;
-extern struct arc_opcode arc_opcodes[];
-extern const int arc_opcodes_count;
-extern const struct arc_operand_value arc_suffixes[];
-extern const int arc_suffixes_count;
-extern const struct arc_operand_value arc_reg_names[];
-extern const int arc_reg_names_count;
-extern unsigned char arc_operand_map[];
-
-/* Utility fns in arc-opc.c.  */
-int arc_get_opcode_mach (int, int);
-
-/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
-void arc_opcode_init_tables (int);
-void arc_opcode_init_insert (void);
-void arc_opcode_init_extract (void);
-const struct arc_opcode *arc_opcode_lookup_asm (const char *);
-const struct arc_opcode *arc_opcode_lookup_dis (unsigned int);
-int arc_opcode_limm_p (long *);
-const struct arc_operand_value *arc_opcode_lookup_suffix
-  (const struct arc_operand *type, int value);
-int arc_opcode_supported (const struct arc_opcode *);
-int arc_opval_supported (const struct arc_operand_value *);
-int arc_limm_fixup_adjust (arc_insn);
-int arc_insn_is_j (arc_insn);
-int arc_insn_not_jl (arc_insn);
-int arc_operand_type (int);
-struct arc_operand_value *get_ext_suffix (char *);
-int arc_get_noshortcut_flag (void);
+ /* Register name.  */
+  const char *name;
+
+  /* Size of the string.  */
+  size_t length;
+};
+
+extern const struct arc_aux_reg arc_aux_regs[];
+extern const unsigned arc_num_aux_regs;
+
+#endif /* OPCODE_ARC_H */

diff --git a/ld/ChangeLog b/ld/ChangeLog
index b857a62..7f8ef59 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,25 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+           Cupertino Miranda  <cmiranda@synopsys.com>
+
+       * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
+       * emulparams/arcebelf_prof.sh: New file
+       * emulparams/arcebelf.sh: Likewise.
+       * emulparams/arceblinux_prof.sh: Likewise.
+       * emulparams/arceblinux.sh: Likewise.
+       * emulparams/arcelf_prof.sh: Likewise.
+       * emulparams/arcelf.sh: Likewise.
+       * emulparams/arclinux_prof.sh: Likewise.
+       * emulparams/arclinux.sh: Likewise.
+       * emulparams/arcv2elfx.sh: Likewise.
+       * emulparams/arcv2elf.sh: Likewise.
+       * emultempl/arclinux.em: Likewise.
+       * scripttempl/arclinux.sc: Likewise.
+       * scripttempl/elfarc.sc: Likewise.
+       * scripttempl/elfarcv2.sc: Likewise
+       * Makefile.am: Add new ARC emulations.
+       * Makefile.in: Regenerate.
+       * NEWS: Mention the new feature.
+
 2015-10-04  H.J. Lu  <hongjiu.lu@intel.com>
 
        * configure.tgt (targ_extra_emuls): Add elf_iamcu for Solaris2/x86.

diff --git a/ld/Makefile.am b/ld/Makefile.am
index df88d6a..3f9546b 100644 (file)
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -156,7 +156,12 @@ ALL_EMULATION_SOURCES = \
        eaixrs6.c \
        ealpha.c \
        ealphavms.c \
+       earcv2elf.c \
+       earcv2elfx.c \
        earcelf.c \
+       earcelf_prof.c \
+       earclinux.c \
+       earclinux_prof.c \
        earm_epoc_pe.c \
        earm_wince_pe.c \
        earmaoutb.c \
@@ -692,8 +697,26 @@ ealphavms.c: $(srcdir)/emulparams/alphavms.sh \
   $(srcdir)/emultempl/vms.em $(srcdir)/scripttempl/alphavms.sc \
   ${GEN_DEPENDS}
 
+earcv2elf.c: $(srcdir)/emulparams/arcv2elf.sh \
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarcv2.sc ${GEN_DEPENDS}
+
+earcv2elfx.c: $(srcdir)/emulparams/arcv2elfx.sh \
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarcv2.sc ${GEN_DEPENDS}
+
 earcelf.c: $(srcdir)/emulparams/arcelf.sh \
-  $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarc.sc ${GEN_DEPENDS}
+
+earcelf_prof.c: $(srcdir)/emulparams/arcelf_prof.sh \
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarc.sc ${GEN_DEPENDS}
+
+#for linux on arc
+earclinux.c: $(srcdir)/emulparams/arclinux.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/arclinux.em \
+  $(srcdir)/scripttempl/arclinux.sc ${GEN_DEPENDS}
+
+earclinux_prof.c: $(srcdir)/emulparams/arclinux_prof.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/arclinux.em \
+  $(srcdir)/scripttempl/arclinux.sc ${GEN_DEPENDS}
 
 earm_epoc_pe.c: $(srcdir)/emulparams/arm_epoc_pe.sh \
   $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/epocpe.sc ${GEN_DEPENDS}

diff --git a/ld/Makefile.in b/ld/Makefile.in
index a29690b..9237ff0 100644 (file)
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -486,7 +486,12 @@ ALL_EMULATION_SOURCES = \
        eaixrs6.c \
        ealpha.c \
        ealphavms.c \
+       earcv2elf.c \
+       earcv2elfx.c \
        earcelf.c \
+       earcelf_prof.c \
+       earclinux.c \
+       earclinux_prof.c \
        earm_epoc_pe.c \
        earm_wince_pe.c \
        earmaoutb.c \
@@ -1104,6 +1109,11 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealpha.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealphavms.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf_prof.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_prof.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcv2elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcv2elfx.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earm_epoc_pe.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earm_wince_pe.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmaoutb.Po@am__quote@
@@ -2191,8 +2201,26 @@ ealphavms.c: $(srcdir)/emulparams/alphavms.sh \
   $(srcdir)/emultempl/vms.em $(srcdir)/scripttempl/alphavms.sc \
   ${GEN_DEPENDS}
 
+earcv2elf.c: $(srcdir)/emulparams/arcv2elf.sh \
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarcv2.sc ${GEN_DEPENDS}
+
+earcv2elfx.c: $(srcdir)/emulparams/arcv2elfx.sh \
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarcv2.sc ${GEN_DEPENDS}
+
 earcelf.c: $(srcdir)/emulparams/arcelf.sh \
-  $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarc.sc ${GEN_DEPENDS}
+
+earcelf_prof.c: $(srcdir)/emulparams/arcelf_prof.sh \
+  $(ELF_DEPS) $(srcdir)/scripttempl/elfarc.sc ${GEN_DEPENDS}
+
+#for linux on arc
+earclinux.c: $(srcdir)/emulparams/arclinux.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/arclinux.em \
+  $(srcdir)/scripttempl/arclinux.sc ${GEN_DEPENDS}
+
+earclinux_prof.c: $(srcdir)/emulparams/arclinux_prof.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/arclinux.em \
+  $(srcdir)/scripttempl/arclinux.sc ${GEN_DEPENDS}
 
 earm_epoc_pe.c: $(srcdir)/emulparams/arm_epoc_pe.sh \
   $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/epocpe.sc ${GEN_DEPENDS}

diff --git a/ld/NEWS b/ld/NEWS
index 864384b..e5dd1a5 100644 (file)
--- a/ld/NEWS
+++ b/ld/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the ARC EM/HS, and ARC600/700 architectures.
+
 * Experimental support for linker garbage collection (--gc-sections)
   has been enabled for COFF and PE based targets.
 

diff --git a/ld/configure.tgt b/ld/configure.tgt
index dd30cc7..197f13e 100644 (file)
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -72,7 +72,11 @@ alpha*-*-netbsd*)    targ_emul=elf64alpha_nbsd ;;
 alpha*-*-openbsd*)     targ_emul=elf64alpha ;;
 alpha*-*-*vms*)                targ_emul=alphavms
                        ;;
-arc-*-elf*)            targ_emul=arcelf
+arc*-*-elf*)           targ_emul=arcelf
+                       targ_extra_emuls="arcelf_prof arclinux arclinux_prof arcv2elf arcv2elfx"
+                       ;;
+arc*-*-linux-uclibc*)  targ_emul=arclinux
+                       targ_extra_emuls="arclinux_prof arcelf arcelf_prof arcv2elf arcv2elfx"
                        ;;
 arm-epoc-pe)           targ_emul=arm_epoc_pe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;;
 arm*-*-cegcc*)         targ_emul=arm_wince_pe ; targ_extra_ofiles="deffilep.o pe-dll.o"

diff --git a/ld/emulparams/arcebelf.sh b/ld/emulparams/arcebelf.sh
new file mode 100644 (file)
index 0000000..994605e
--- /dev/null
+++ b/ld/emulparams/arcebelf.sh
@@ -0,0 +1,15 @@
+SCRIPT_NAME=elfarc
+TEMPLATE_NAME=elf32
+OUTPUT_FORMAT="elf32-bigarc"
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+# leave room for vector table, 32 vectors * 8 bytes
+TEXT_START_ADDR=0x100
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+#NONPAGED_TEXT_START_ADDR=0x0
+ARCH=arc
+MACHINE=
+ENTRY=__start
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"
+EMBEDDED=yes

diff --git a/ld/emulparams/arcebelf_prof.sh b/ld/emulparams/arcebelf_prof.sh
new file mode 100644 (file)
index 0000000..1bd0531
--- /dev/null
+++ b/ld/emulparams/arcebelf_prof.sh
@@ -0,0 +1,21 @@
+SCRIPT_NAME=elfarc
+TEMPLATE_NAME=elf32
+OUTPUT_FORMAT="elf32-bigarc"
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+# leave room for vector table, 32 vectors * 8 bytes
+TEXT_START_ADDR=0x100
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+#NONPAGED_TEXT_START_ADDR=0x0
+ARCH=arc
+MACHINE=
+ENTRY=__start
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_READONLY_SECTIONS="
+  .__arc_profile_desc ${RELOCATING-0} : { *(.__arc_profile_desc) }
+  .__arc_profile_forward ${RELOCATING-0} : { *(.__arc_profile_forward) }
+"
+OTHER_BSS_SECTIONS="
+  .__arc_profile_counters ${RELOCATING-0} : { *(.__arc_profile_counters) }
+"
+EMBEDDED=yes

diff --git a/ld/emulparams/arceblinux.sh b/ld/emulparams/arceblinux.sh
new file mode 100644 (file)
index 0000000..54fd7a9
--- /dev/null
+++ b/ld/emulparams/arceblinux.sh
@@ -0,0 +1,17 @@
+SCRIPT_NAME=arclinux
+OUTPUT_FORMAT="elf32-bigarc"
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+TEXT_START_ADDR=0x10000
+MAXPAGESIZE=0x2000
+COMMONPAGESIZE=0x2000
+NONPAGED_TEXT_START_ADDR=0x10000
+ARCH=arc
+MACHINE=
+ENTRY=__start
+TEMPLATE_NAME=arclinux
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=arclinux
+GENERATE_SHLIB_SCRIPT=yes
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"

diff --git a/ld/emulparams/arceblinux_prof.sh b/ld/emulparams/arceblinux_prof.sh
new file mode 100644 (file)
index 0000000..3b1ccdd
--- /dev/null
+++ b/ld/emulparams/arceblinux_prof.sh
@@ -0,0 +1,23 @@
+SCRIPT_NAME=arclinux
+OUTPUT_FORMAT="elf32-bigarc"
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+TEXT_START_ADDR=0x10000
+MAXPAGESIZE=0x2000
+COMMONPAGESIZE=0x2000
+NONPAGED_TEXT_START_ADDR=0x10000
+ARCH=arc
+MACHINE=
+ENTRY=__start
+TEMPLATE_NAME=arclinux
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=arclinux
+GENERATE_SHLIB_SCRIPT=yes
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_READONLY_SECTIONS="
+  .__arc_profile_desc ${RELOCATING-0} : { *(.__arc_profile_desc) }
+  .__arc_profile_forward ${RELOCATING-0} : { *(.__arc_profile_forward) }
+"
+OTHER_BSS_SECTIONS="
+  .__arc_profile_counters ${RELOCATING-0} : { *(.__arc_profile_counters) }
+"

diff --git a/ld/emulparams/arcelf.sh b/ld/emulparams/arcelf.sh
index cd334d6..14a3033 100644 (file)
--- a/ld/emulparams/arcelf.sh
+++ b/ld/emulparams/arcelf.sh
@@ -1,12 +1,19 @@
-SCRIPT_NAME=elf
-TEMPLATE_NAME=generic
-EXTRA_EM_FILE=genelf
-OUTPUT_FORMAT="elf32-littlearc"
+SCRIPT_NAME=elfarc
+TEMPLATE_NAME=elf32
+if [ "x${ARC_ENDIAN}" = "xbig" ]; then
+  OUTPUT_FORMAT="elf32-bigarc"
+else
+  OUTPUT_FORMAT="elf32-littlearc"
+fi
 LITTLE_OUTPUT_FORMAT="elf32-littlearc"
 BIG_OUTPUT_FORMAT="elf32-bigarc"
-NO_RELA_RELOCS=yes
-TEXT_START_ADDR=0x0
+# leave room for vector table, 32 vectors * 8 bytes
+TEXT_START_ADDR=0x100
 MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+#NONPAGED_TEXT_START_ADDR=0x0
 ARCH=arc
 MACHINE=
-ENTRY=start
+ENTRY=__start
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"
+EMBEDDED=yes

diff --git a/ld/emulparams/arcelf_prof.sh b/ld/emulparams/arcelf_prof.sh
new file mode 100644 (file)
index 0000000..0202002
--- /dev/null
+++ b/ld/emulparams/arcelf_prof.sh
@@ -0,0 +1,25 @@
+SCRIPT_NAME=elfarc
+TEMPLATE_NAME=elf32
+if [ "x${ARC_ENDIAN}" = "xbig" ]; then
+  OUTPUT_FORMAT="elf32-bigarc"
+else
+  OUTPUT_FORMAT="elf32-littlearc"
+fi
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+# leave room for vector table, 32 vectors * 8 bytes
+TEXT_START_ADDR=0x100
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+#NONPAGED_TEXT_START_ADDR=0x0
+ARCH=arc
+MACHINE=
+ENTRY=__start
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_READONLY_SECTIONS="
+  .__arc_profile_desc ${RELOCATING-0} : { *(.__arc_profile_desc) }
+  .__arc_profile_forward ${RELOCATING-0} : { *(.__arc_profile_forward) }
+"
+OTHER_BSS_SECTIONS="
+  .__arc_profile_counters ${RELOCATING-0} : { *(.__arc_profile_counters) }
+"
+EMBEDDED=yes

diff --git a/ld/emulparams/arclinux.sh b/ld/emulparams/arclinux.sh
new file mode 100644 (file)
index 0000000..452a272
--- /dev/null
+++ b/ld/emulparams/arclinux.sh
@@ -0,0 +1,21 @@
+SCRIPT_NAME=arclinux
+if [ "x${ARC_ENDIAN}" = "xbig" ]; then
+  OUTPUT_FORMAT="elf32-bigarc"
+else
+  OUTPUT_FORMAT="elf32-littlearc"
+fi
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+TEXT_START_ADDR=0x10000
+MAXPAGESIZE=0x2000
+COMMONPAGESIZE=0x2000
+NONPAGED_TEXT_START_ADDR=0x10000
+ARCH=arc
+MACHINE=
+ENTRY=__start
+TEMPLATE_NAME=arclinux
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=arclinux
+GENERATE_SHLIB_SCRIPT=yes
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"

diff --git a/ld/emulparams/arclinux_prof.sh b/ld/emulparams/arclinux_prof.sh
new file mode 100644 (file)
index 0000000..fed098b
--- /dev/null
+++ b/ld/emulparams/arclinux_prof.sh
@@ -0,0 +1,27 @@
+SCRIPT_NAME=arclinux
+if [ "x${ARC_ENDIAN}" = "xbig" ]; then
+  OUTPUT_FORMAT="elf32-bigarc"
+else
+  OUTPUT_FORMAT="elf32-littlearc"
+fi
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+TEXT_START_ADDR=0x10000
+MAXPAGESIZE=0x2000
+COMMONPAGESIZE=0x2000
+NONPAGED_TEXT_START_ADDR=0x10000
+ARCH=arc
+MACHINE=
+ENTRY=__start
+TEMPLATE_NAME=arclinux
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=arclinux
+GENERATE_SHLIB_SCRIPT=yes
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_READONLY_SECTIONS="
+  .__arc_profile_desc ${RELOCATING-0} : { *(.__arc_profile_desc) }
+  .__arc_profile_forward ${RELOCATING-0} : { *(.__arc_profile_forward) }
+"
+OTHER_BSS_SECTIONS="
+  .__arc_profile_counters ${RELOCATING-0} : { *(.__arc_profile_counters) }
+"

diff --git a/ld/emulparams/arcv2elf.sh b/ld/emulparams/arcv2elf.sh
new file mode 100644 (file)
index 0000000..2793ea3
--- /dev/null
+++ b/ld/emulparams/arcv2elf.sh
@@ -0,0 +1,25 @@
+MACHINE=
+SCRIPT_NAME=elfarcv2
+if [ "x${ARC_ENDIAN}" = "xbig" ]; then
+  OUTPUT_FORMAT="elf32-bigarc"
+else
+  OUTPUT_FORMAT="elf32-littlearc"
+fi
+ICCM_SIZE=2M
+RAM_START_ADDR=0x80000000
+RAM_SIZE=2M
+STARTUP_MEMORY=ICCM
+TEXT_MEMORY=ICCM
+DATA_MEMORY=DCCM
+SDATA_MEMORY=DCCM
+ARCH=arc
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+EMBEDDED=yes
+GENERIC_BOARD=no
+TEMPLATE_NAME=elf32
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+TEXT_START_ADDR=0x100
+ENTRY=__start
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"

diff --git a/ld/emulparams/arcv2elfx.sh b/ld/emulparams/arcv2elfx.sh
new file mode 100644 (file)
index 0000000..9999d8d
--- /dev/null
+++ b/ld/emulparams/arcv2elfx.sh
@@ -0,0 +1,22 @@
+MACHINE=
+SCRIPT_NAME=elfarcv2
+if [ "x${ARC_ENDIAN}" = "xbig" ]; then
+  OUTPUT_FORMAT="elf32-bigarc"
+else
+  OUTPUT_FORMAT="elf32-littlearc"
+fi
+STARTUP_MEMORY=startup
+TEXT_MEMORY=text
+DATA_MEMORY=data
+SDATA_MEMORY=sdata
+ARCH=arc
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+GENERIC_BOARD=yes
+TEMPLATE_NAME=elf32
+LITTLE_OUTPUT_FORMAT="elf32-littlearc"
+BIG_OUTPUT_FORMAT="elf32-bigarc"
+TEXT_START_ADDR=0x100
+ENTRY=__start
+SDATA_START_SYMBOLS='__SDATA_BEGIN__ = .;'
+OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"
+EMBEDDED=yes

diff --git a/ld/emultempl/arclinux.em b/ld/emultempl/arclinux.em
new file mode 100644 (file)
index 0000000..61a071b
--- /dev/null
+++ b/ld/emultempl/arclinux.em
@@ -0,0 +1,52 @@
+# This shell script emits a C file. -*- C -*-
+# Copyright (C) 2007 Free Software Foundation, Inc.
+#
+# Copyright 2008-2012 Synopsys Inc.
+#
+# This file is part of GLD, the Gnu Linker.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# This file is sourced from elf32.em, and defines extra arc-linux
+# specific routines.
+#
+cat >>e${EMULATION_NAME}.c <<EOF
+extern char * init_str;
+extern char * fini_str;
+EOF
+
+PARSE_AND_LIST_PROLOGUE='
+#define OPTION_INIT 300+1
+#define OPTION_FINI (OPTION_INIT+1)
+'
+PARSE_AND_LIST_LONGOPTS='
+  /* PE options */
+  { "init", required_argument, NULL, OPTION_INIT },
+  { "fini", required_argument, NULL, OPTION_FINI },
+'
+
+# FIXME: Should set PARSE_AND_LIST_OPTIONS to provide a short description
+# of the options.
+
+PARSE_AND_LIST_ARGS_CASES='
+    case OPTION_FINI:
+      fini_str = optarg;
+      break;
+
+    case OPTION_INIT:
+      init_str = optarg;
+      break;
+'

diff --git a/ld/scripttempl/arclinux.sc b/ld/scripttempl/arclinux.sc
new file mode 100644 (file)
index 0000000..9d43ca3
--- /dev/null
+++ b/ld/scripttempl/arclinux.sc
@@ -0,0 +1,439 @@
+#
+# Unusual variables checked by this code:
+#      NOP - four byte opcode for no-op (defaults to 0)
+#      NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
+#              empty.
+#      DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
+#      INITIAL_READONLY_SECTIONS - at start of text segment
+#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
+#              (e.g., .PARISC.milli)
+#      OTHER_TEXT_SECTIONS - these get put in .text when relocating
+#      OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
+#              (e.g., .PARISC.global)
+#      OTHER_BSS_SECTIONS - other than .bss .sbss ...
+#      OTHER_SECTIONS - at the end
+#      EXECUTABLE_SYMBOLS - symbols that must be defined for an
+#              executable (e.g., _DYNAMIC_LINK)
+#      TEXT_START_SYMBOLS - symbols that appear at the start of the
+#              .text section.
+#      DATA_START_SYMBOLS - symbols that appear at the start of the
+#              .data section.
+#      OTHER_GOT_SYMBOLS - symbols defined just before .got.
+#      OTHER_GOT_SECTIONS - sections just after .got.
+#      OTHER_SDATA_SECTIONS - sections just after .sdata.
+#      OTHER_BSS_SYMBOLS - symbols that appear at the start of the
+#              .bss section besides __bss_start.
+#      DATA_PLT - .plt should be in data segment, not text segment.
+#      BSS_PLT - .plt should be in bss segment
+#      TEXT_DYNAMIC - .dynamic in text segment, not data segment.
+#      EMBEDDED - whether this is for an embedded system. 
+#      SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
+#              start address of shared library.
+#      INPUT_FILES - INPUT command of files to always include
+#      WRITABLE_RODATA - if set, the .rodata section should be writable
+#      INIT_START, INIT_END -  statements just before and just after
+#      combination of .init sections.
+#      FINI_START, FINI_END - statements just before and just after
+#      combination of .fini sections.
+#      STACK_ADDR - start of a .stack section.
+#      OTHER_END_SYMBOLS - symbols to place right at the end of the script.
+#
+# When adding sections, do note that the names of some sections are used
+# when specifying the start address of the next.
+#
+
+#  Many sections come in three flavours.  There is the 'real' section,
+#  like ".data".  Then there are the per-procedure or per-variable
+#  sections, generated by -ffunction-sections and -fdata-sections in GCC,
+#  and useful for --gc-sections, which for a variable "foo" might be
+#  ".data.foo".  Then there are the linkonce sections, for which the linker
+#  eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
+#  The exact correspondences are:
+#
+#  Section     Linkonce section
+#  .text       .gnu.linkonce.t.foo
+#  .rodata     .gnu.linkonce.r.foo
+#  .data       .gnu.linkonce.d.foo
+#  .bss                .gnu.linkonce.b.foo
+#  .sdata      .gnu.linkonce.s.foo
+#  .sbss       .gnu.linkonce.sb.foo
+#  .sdata2     .gnu.linkonce.s2.foo
+#  .sbss2      .gnu.linkonce.sb2.foo
+#  .debug_info .gnu.linkonce.wi.foo
+#  .tdata      .gnu.linkonce.td.foo
+#  .tbss       .gnu.linkonce.tb.foo
+#
+#  Each of these can also have corresponding .rel.* and .rela.* sections.
+
+test -z "$ENTRY" && ENTRY=start
+test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+# If we request a big endian toolchain, give a big endian linker
+test "${ARC_ENDIAN}" == "big" && OUTPUT_FORMAT=${BIG_OUTPUT_FORMAT}
+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
+test -z "${ELFSIZE}" && ELFSIZE=32
+test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
+test "$LD_FLAG" = "N" && DATA_ADDR=.
+test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
+test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
+DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
+DATA_SEGMENT_END=""
+if test -n "${COMMONPAGESIZE}"; then
+  DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) & (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})"
+  DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);"
+fi
+INTERP=".interp       ${RELOCATING-0} : { *(.interp) }"
+PLT=".plt          ${RELOCATING-0} : { *(.plt) }"
+test -z "$GOT" && GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) }"
+DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
+RODATA=".rodata       ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
+STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
+if test -z "${NO_SMALL_DATA}"; then
+  SBSS=".sbss         ${RELOCATING-0} :
+  {
+    ${RELOCATING+PROVIDE (__sbss_start = .);}
+    ${RELOCATING+PROVIDE (___sbss_start = .);}
+    *(.dynsbss)
+    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
+    *(.scommon)
+    ${RELOCATING+PROVIDE (__sbss_end = .);}
+    ${RELOCATING+PROVIDE (___sbss_end = .);}
+  }"
+  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }"
+  SDATA="/* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata        ${RELOCATING-0} : 
+  {
+    ${RELOCATING+${SDATA_START_SYMBOLS}}
+    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
+  }"
+  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }"
+  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }
+  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
+  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }
+  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }"
+  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }
+  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }"
+  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }
+  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }"
+fi
+CTOR=".ctors        ${CONSTRUCTING-0} : 
+  {
+    ${CONSTRUCTING+${CTOR_START}}
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+
+    KEEP (*crtbegin*.o(.ctors))
+
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ${CONSTRUCTING+${CTOR_END}}
+  }"
+DTOR=".dtors        ${CONSTRUCTING-0} :
+  {
+    ${CONSTRUCTING+${DTOR_START}}
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ${CONSTRUCTING+${DTOR_END}}
+  }"
+STACK="  .stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
+  {
+    ${RELOCATING+_stack = .;}
+    *(.stack)
+  }"
+
+# if this is for an embedded system, don't add SIZEOF_HEADERS.
+if [ -z "$EMBEDDED" ]; then
+   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
+else
+   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
+fi
+
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
+             "${LITTLE_OUTPUT_FORMAT}")
+OUTPUT_ARCH(${OUTPUT_ARCH})
+${RELOCATING+ENTRY(${ENTRY})}
+
+${RELOCATING+${LIB_SEARCH_DIRS}}
+${RELOCATING+/* Do we need any of these for elf?
+   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
+${RELOCATING+${EXECUTABLE_SYMBOLS}}
+${RELOCATING+${INPUT_FILES}}
+${RELOCATING- /* For some reason, the Solaris linker makes bad executables
+  if gld -r is used and the intermediate file has sections starting
+  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
+  bug.  But for now assigning the zero vmas works.  */}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
+  ${CREATE_SHLIB-${INTERP}}
+  ${INITIAL_READONLY_SECTIONS}
+  ${TEXT_DYNAMIC+${DYNAMIC}}
+  .hash         ${RELOCATING-0} : { *(.hash) }
+  .dynsym       ${RELOCATING-0} : { *(.dynsym) }
+  .dynstr       ${RELOCATING-0} : { *(.dynstr) }
+  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }
+  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }
+  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }
+
+EOF
+if [ "x$COMBRELOC" = x ]; then
+  COMBRELOCCAT=cat
+else
+  COMBRELOCCAT="cat > $COMBRELOC"
+fi
+eval $COMBRELOCCAT <<EOF
+  .rel.init     ${RELOCATING-0} : { *(.rel.init) }
+  .rela.init    ${RELOCATING-0} : { *(.rela.init) }
+  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }
+  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }
+  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }
+  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }
+  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }
+  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }
+  ${OTHER_READONLY_RELOC_SECTIONS}
+  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
+  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
+  .rel.tdata   ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
+  .rela.tdata  ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }
+  .rel.tbss    ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }
+  .rela.tbss   ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }
+  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }
+  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }
+  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }
+  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }
+  .rel.got      ${RELOCATING-0} : { *(.rel.got) }
+  .rela.got     ${RELOCATING-0} : { *(.rela.got) }
+  ${OTHER_GOT_RELOC_SECTIONS}
+  ${REL_SDATA}
+  ${REL_SBSS}
+  ${REL_SDATA2}
+  ${REL_SBSS2}
+  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }
+  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }
+EOF
+if [ -n "$COMBRELOC" ]; then
+cat <<EOF
+  .rel.dyn      ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC
+cat <<EOF
+    }
+  .rela.dyn     ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC
+cat <<EOF
+    }
+EOF
+fi
+cat <<EOF
+  .rel.plt      ${RELOCATING-0} : { *(.rel.plt) }
+  .rela.plt     ${RELOCATING-0} : { *(.rela.plt) }
+  ${OTHER_PLT_RELOC_SECTIONS}
+
+  .init         ${RELOCATING-0} : 
+  { 
+    ${RELOCATING+${INIT_START}}
+    KEEP (*(.init))
+    ${RELOCATING+${INIT_END}}
+  } =${NOP-0}
+
+  ${DATA_PLT-${BSS_PLT-${PLT}}}
+  .text         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${TEXT_START_SYMBOLS}}
+    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
+  } =${NOP-0}
+  .text.init ${RELOCATING-0} :
+  {
+    *(.text.init)
+  } =${NOP-0}
+  .fini         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${FINI_START}}
+    KEEP (*(.fini))
+    ${RELOCATING+${FINI_END}}
+  } =${NOP-0}
+  ${RELOCATING+PROVIDE (__etext = .);}
+  ${RELOCATING+PROVIDE (_etext = .);}
+  ${RELOCATING+PROVIDE (etext = .);}
+  ${WRITABLE_RODATA-${RODATA}}
+  .rodata1      ${RELOCATING-0} : { *(.rodata1) }
+  ${CREATE_SHLIB-${SDATA2}}
+  ${CREATE_SHLIB-${SBSS2}}
+  ${OTHER_READONLY_SECTIONS}
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = .);}}
+  .preinit_array   ${RELOCATING-0} : { *(.preinit_array) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
+
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
+  .init_array   ${RELOCATING-0} : { *(.init_array) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
+
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
+  .fini_array   ${RELOCATING-0} : { *(.fini_array) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
+
+  .data         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${DATA_START_SYMBOLS}}
+    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
+    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
+  }
+  .data.init  ${RELOCATING-0} :
+  {
+    *(.data.init)
+  }
+  .data1        ${RELOCATING-0} : { *(.data1) }
+  /* TLS local dynamic uses .tdata as a reference point.  */
+  ${RELOCATING+${CREATE_SHLIB+PROVIDE_HIDDEN (.tdata = .);}}
+  .tdata       ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
+  .tbss                ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
+  .eh_frame     ${RELOCATING-0} : { KEEP (*(.eh_frame)) }
+  .gcc_except_table ${RELOCATING-0} : { *(.gcc_except_table) }
+  ${WRITABLE_RODATA+${RODATA}}
+  ${OTHER_READWRITE_SECTIONS}
+  ${TEXT_DYNAMIC-${DYNAMIC}}
+  ${RELOCATING+${CTOR}}
+  ${RELOCATING+${DTOR}}
+  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }
+  ${DATA_PLT+${PLT}}
+  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
+  ${GOT}
+  ${OTHER_GOT_SECTIONS}
+  ${CREATE_SHLIB+${SDATA2}}
+  ${CREATE_SHLIB+${SBSS2}}
+  ${SDATA}
+  ${OTHER_SDATA_SECTIONS}
+  ${RELOCATING+_edata = .;}
+  ${RELOCATING+PROVIDE (edata = .);}
+  ${RELOCATING+__bss_start = .;}
+  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
+  ${SBSS}
+  ${BSS_PLT+${PLT}}
+  .bss          ${RELOCATING-0} :
+  {
+   *(.dynbss)
+   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  }
+  ${OTHER_BSS_SECTIONS}
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+_end = .;}
+  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
+  ${RELOCATING+PROVIDE (end = .);}
+  ${RELOCATING+${DATA_SEGMENT_END}}
+
+  /* We want to be able to set a default stack / heap size in a dejagnu
+     board description file, but override it for selected test cases.
+     The options appear in the wrong order to do this with a single symbol -
+     ldflags comes after flags injected with per-file stanzas, and thus
+     the setting from ldflags prevails.  */
+  .heap ${RELOCATING-0} :
+  {
+        ${RELOCATING+ __start_heap = . ; }
+        ${RELOCATING+ . = . + (DEFINED(__HEAP_SIZE) ? __HEAP_SIZE : (DEFINED(__DEFAULT_HEAP_SIZE) ? __DEFAULT_HEAP_SIZE : 20k))  ; }
+        ${RELOCATING+ __end_heap = . ; }
+  }
+
+  ${RELOCATING+. = ALIGN(0x8);}
+  .stack ${RELOCATING-0} :
+  {
+        ${RELOCATING+ __stack = . ; }
+        ${RELOCATING+ . = . + (DEFINED(__STACK_SIZE) ? __STACK_SIZE : (DEFINED(__DEFAULT_STACK_SIZE) ? __DEFAULT_STACK_SIZE : 64k))  ; }
+        ${RELOCATING+ __stack_top = . ; }
+  }
+
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+
+  .comment       0 : { *(.comment) }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  /* ARC Extension Sections */
+  .arcextmap     0 : { *(.gnu.linkonce.arcextmap.*) }
+
+  ${STACK_ADDR+${STACK}}
+  ${OTHER_SECTIONS}
+  ${RELOCATING+${OTHER_END_SYMBOLS}}
+  ${RELOCATING+${STACKNOTE}}
+}
+EOF

diff --git a/ld/scripttempl/elf32msp430.sc b/ld/scripttempl/elf32msp430.sc
index 65105e5..6fb7b3a 100644 (file)
--- a/ld/scripttempl/elf32msp430.sc
+++ b/ld/scripttempl/elf32msp430.sc
@@ -279,18 +279,23 @@ SECTIONS
     *(.either.bss.* .either.bss)
     *(COMMON)
     ${RELOCATING+ PROVIDE (__bss_end = .) ; }
-    ${RELOCATING+ _end = . ;  }
   } ${RELOCATING+ > data}
 
   .noinit ${RELOCATING+ SIZEOF(.bss) + ADDR(.bss)} :
   {
     ${RELOCATING+ PROVIDE (__noinit_start = .) ; }
     *(.noinit)
-    *(COMMON)
     ${RELOCATING+ PROVIDE (__noinit_end = .) ; }
-    ${RELOCATING+ _end = . ;  }
   } ${RELOCATING+ > data}
 
+  .persistent ${RELOCATING+ SIZEOF(.noinit) + ADDR(.noinit)} :
+  {
+    ${RELOCATING+ PROVIDE (__persistent_start = .) ; }
+    *(.persistent)
+    ${RELOCATING+ PROVIDE (__persistent_end = .) ; }
+  } ${RELOCATING+ > data}
+
+  ${RELOCATING+ _end = . ;  }
   ${HEAP_SECTION_MSP430}
 
   /* Stabs for profiling information*/

diff --git a/ld/scripttempl/elf32msp430_3.sc b/ld/scripttempl/elf32msp430_3.sc
index b5b4ec9..55ae74c 100644 (file)
--- a/ld/scripttempl/elf32msp430_3.sc
+++ b/ld/scripttempl/elf32msp430_3.sc
@@ -154,7 +154,6 @@ SECTIONS
     *(.bss)
     *(COMMON)
     ${RELOCATING+ PROVIDE (__bss_end = .) ; }
-    ${RELOCATING+ _end = . ;  }
   } ${RELOCATING+ > data}
 
   .noinit ${RELOCATING+ SIZEOF(.bss) + ADDR(.bss)} :
@@ -163,9 +162,17 @@ SECTIONS
     *(.noinit)
     *(COMMON)
     ${RELOCATING+ PROVIDE (__noinit_end = .) ; }
-    ${RELOCATING+ _end = . ;  }
   } ${RELOCATING+ > data}
 
+  .persistent ${RELOCATING+ SIZEOF(.noinit) + ADDR(.noinit)} :
+  {
+    ${RELOCATING+ PROVIDE (__persistent_start = .) ; }
+    *(.persistent)
+    ${RELOCATING+ PROVIDE (__persistent_end = .) ; }
+  } ${RELOCATING+ > data}
+
+  ${RELOCATING+ _end = . ;}
+
   .vectors ${RELOCATING-0}:
   {
     ${RELOCATING+ PROVIDE (__vectors_start = .) ; }

diff --git a/ld/scripttempl/elfarc.sc b/ld/scripttempl/elfarc.sc
new file mode 100644 (file)
index 0000000..9d1e139
--- /dev/null
+++ b/ld/scripttempl/elfarc.sc
@@ -0,0 +1,441 @@
+#
+# Unusual variables checked by this code:
+#      NOP - four byte opcode for no-op (defaults to 0)
+#      NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
+#              empty.
+#      DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
+#      INITIAL_READONLY_SECTIONS - at start of text segment
+#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
+#              (e.g., .PARISC.milli)
+#      OTHER_TEXT_SECTIONS - these get put in .text when relocating
+#      OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
+#              (e.g., .PARISC.global)
+#      OTHER_BSS_SECTIONS - other than .bss .sbss ...
+#      OTHER_SECTIONS - at the end
+#      EXECUTABLE_SYMBOLS - symbols that must be defined for an
+#              executable (e.g., _DYNAMIC_LINK)
+#      TEXT_START_SYMBOLS - symbols that appear at the start of the
+#              .text section.
+#      DATA_START_SYMBOLS - symbols that appear at the start of the
+#              .data section.
+#      OTHER_GOT_SYMBOLS - symbols defined just before .got.
+#      OTHER_GOT_SECTIONS - sections just after .got.
+#      OTHER_SDATA_SECTIONS - sections just after .sdata.
+#      OTHER_BSS_SYMBOLS - symbols that appear at the start of the
+#              .bss section besides __bss_start.
+#      DATA_PLT - .plt should be in data segment, not text segment.
+#      BSS_PLT - .plt should be in bss segment
+#      TEXT_DYNAMIC - .dynamic in text segment, not data segment.
+#      EMBEDDED - whether this is for an embedded system. 
+#      SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
+#              start address of shared library.
+#      INPUT_FILES - INPUT command of files to always include
+#      WRITABLE_RODATA - if set, the .rodata section should be writable
+#      INIT_START, INIT_END -  statements just before and just after
+#      combination of .init sections.
+#      FINI_START, FINI_END - statements just before and just after
+#      combination of .fini sections.
+#      STACK_ADDR - start of a .stack section.
+#      OTHER_END_SYMBOLS - symbols to place right at the end of the script.
+#
+# When adding sections, do note that the names of some sections are used
+# when specifying the start address of the next.
+#
+
+#  Many sections come in three flavours.  There is the 'real' section,
+#  like ".data".  Then there are the per-procedure or per-variable
+#  sections, generated by -ffunction-sections and -fdata-sections in GCC,
+#  and useful for --gc-sections, which for a variable "foo" might be
+#  ".data.foo".  Then there are the linkonce sections, for which the linker
+#  eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
+#  The exact correspondences are:
+#
+#  Section     Linkonce section
+#  .text       .gnu.linkonce.t.foo
+#  .rodata     .gnu.linkonce.r.foo
+#  .data       .gnu.linkonce.d.foo
+#  .bss                .gnu.linkonce.b.foo
+#  .sdata      .gnu.linkonce.s.foo
+#  .sbss       .gnu.linkonce.sb.foo
+#  .sdata2     .gnu.linkonce.s2.foo
+#  .sbss2      .gnu.linkonce.sb2.foo
+#  .debug_info .gnu.linkonce.wi.foo
+#  .tdata      .gnu.linkonce.td.foo
+#  .tbss       .gnu.linkonce.tb.foo
+#
+#  Each of these can also have corresponding .rel.* and .rela.* sections.
+
+test -z "$ENTRY" && ENTRY=start
+test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+# If we request a big endian toolchain, give a big endian linker
+test "${ARC_ENDIAN}" == "big" && OUTPUT_FORMAT=${BIG_OUTPUT_FORMAT}
+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
+test -z "${ELFSIZE}" && ELFSIZE=32
+test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
+test "$LD_FLAG" = "N" && DATA_ADDR=.
+test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
+test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
+DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
+DATA_SEGMENT_END=""
+if test -n "${COMMONPAGESIZE}"; then
+  DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) & (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})"
+  DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);"
+fi
+INTERP=".interp       ${RELOCATING-0} : { *(.interp) }"
+PLT=".plt          ${RELOCATING-0} : { *(.plt) }"
+test -z "$GOT" && GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) }"
+DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
+RODATA=".rodata       ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
+STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
+if test -z "${NO_SMALL_DATA}"; then
+  SBSS=".sbss         ${RELOCATING-0} :
+  {
+    ${RELOCATING+PROVIDE (__sbss_start = .);}
+    ${RELOCATING+PROVIDE (___sbss_start = .);}
+    *(.dynsbss)
+    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
+    *(.scommon)
+    ${RELOCATING+PROVIDE (__sbss_end = .);}
+    ${RELOCATING+PROVIDE (___sbss_end = .);}
+  }"
+  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }"
+  SDATA="/* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata        ${RELOCATING-0} : 
+  {
+    ${RELOCATING+${SDATA_START_SYMBOLS}}
+    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
+  }"
+  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }"
+  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }
+  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
+  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }
+  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }"
+  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }
+  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }"
+  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }
+  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }"
+fi
+CTOR=".ctors        ${CONSTRUCTING-0} : 
+  {
+    ${CONSTRUCTING+${CTOR_START}}
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+
+    KEEP (*crtbegin*.o(.ctors))
+
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ${CONSTRUCTING+${CTOR_END}}
+  }"
+DTOR=".dtors        ${CONSTRUCTING-0} :
+  {
+    ${CONSTRUCTING+${DTOR_START}}
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ${CONSTRUCTING+${DTOR_END}}
+  }"
+STACK="  .stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
+  {
+    ${RELOCATING+_stack = .;}
+    *(.stack)
+  }"
+
+# if this is for an embedded system, don't add SIZEOF_HEADERS.
+if [ -z "$EMBEDDED" ]; then
+   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
+else
+   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
+fi
+
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
+             "${LITTLE_OUTPUT_FORMAT}")
+OUTPUT_ARCH(${OUTPUT_ARCH})
+${RELOCATING+ENTRY(${ENTRY})}
+
+${RELOCATING+${LIB_SEARCH_DIRS}}
+${RELOCATING+/* Do we need any of these for elf?
+   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
+${RELOCATING+${EXECUTABLE_SYMBOLS}}
+${RELOCATING+${INPUT_FILES}}
+${RELOCATING- /* For some reason, the Solaris linker makes bad executables
+  if gld -r is used and the intermediate file has sections starting
+  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
+  bug.  But for now assigning the zero vmas works.  */}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
+  ${CREATE_SHLIB-${INTERP}}
+  ${INITIAL_READONLY_SECTIONS}
+  ${TEXT_DYNAMIC+${DYNAMIC}}
+  .hash         ${RELOCATING-0} : { *(.hash) }
+  .dynsym       ${RELOCATING-0} : { *(.dynsym) }
+  .dynstr       ${RELOCATING-0} : { *(.dynstr) }
+  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }
+  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }
+  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }
+
+EOF
+if [ "x$COMBRELOC" = x ]; then
+  COMBRELOCCAT=cat
+else
+  COMBRELOCCAT="cat > $COMBRELOC"
+fi
+eval $COMBRELOCCAT <<EOF
+  .rel.init     ${RELOCATING-0} : { *(.rel.init) }
+  .rela.init    ${RELOCATING-0} : { *(.rela.init) }
+  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }
+  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }
+  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }
+  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }
+  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }
+  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }
+  ${OTHER_READONLY_RELOC_SECTIONS}
+  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
+  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
+  .rel.tdata   ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
+  .rela.tdata  ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }
+  .rel.tbss    ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }
+  .rela.tbss   ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }
+  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }
+  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }
+  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }
+  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }
+  .rel.got      ${RELOCATING-0} : { *(.rel.got) }
+  .rela.got     ${RELOCATING-0} : { *(.rela.got) }
+  ${OTHER_GOT_RELOC_SECTIONS}
+  ${REL_SDATA}
+  ${REL_SBSS}
+  ${REL_SDATA2}
+  ${REL_SBSS2}
+  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }
+  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }
+EOF
+if [ -n "$COMBRELOC" ]; then
+cat <<EOF
+  .rel.dyn      ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC
+cat <<EOF
+    }
+  .rela.dyn     ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC
+cat <<EOF
+    }
+EOF
+fi
+cat <<EOF
+  .rel.plt      ${RELOCATING-0} : { *(.rel.plt) }
+  .rela.plt     ${RELOCATING-0} : { *(.rela.plt) }
+  ${OTHER_PLT_RELOC_SECTIONS}
+
+  .init         ${RELOCATING-0} : 
+  { 
+    ${RELOCATING+${INIT_START}}
+    KEEP (*(.init))
+    ${RELOCATING+${INIT_END}}
+  } =${NOP-0}
+
+  ${DATA_PLT-${BSS_PLT-${PLT}}}
+  .text         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${TEXT_START_SYMBOLS}}
+    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
+  } =${NOP-0}
+  .text.init ${RELOCATING-0} :
+  {
+    *(.text.init)
+  } =${NOP-0}
+  .fini         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${FINI_START}}
+    KEEP (*(.fini))
+    ${RELOCATING+${FINI_END}}
+  } =${NOP-0}
+  ${RELOCATING+PROVIDE (__etext = .);}
+  ${RELOCATING+PROVIDE (_etext = .);}
+  ${RELOCATING+PROVIDE (etext = .);}
+  ${WRITABLE_RODATA-${RODATA}}
+  .rodata1      ${RELOCATING-0} : { *(.rodata1) }
+  ${CREATE_SHLIB-${SDATA2}}
+  ${CREATE_SHLIB-${SBSS2}}
+  ${OTHER_READONLY_SECTIONS}
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+
+  /* Exception handling  */
+  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
+
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = .);}}
+  .preinit_array   ${RELOCATING-0} : { *(.preinit_array) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
+
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
+  .init_array   ${RELOCATING-0} : { *(.init_array) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
+
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
+  .fini_array   ${RELOCATING-0} : { *(.fini_array) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
+
+  .data         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${DATA_START_SYMBOLS}}
+    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
+    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
+  }
+  .data.init  ${RELOCATING-0} :
+  {
+    *(.data.init)
+  }
+  .data1        ${RELOCATING-0} : { *(.data1) }
+  .tdata       ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
+  .tbss                ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
+  .eh_frame     ${RELOCATING-0} : { KEEP (*(.eh_frame)) }
+  .gcc_except_table ${RELOCATING-0} : { *(.gcc_except_table) }
+  ${WRITABLE_RODATA+${RODATA}}
+  ${OTHER_READWRITE_SECTIONS}
+  ${TEXT_DYNAMIC-${DYNAMIC}}
+  ${RELOCATING+${CTOR}}
+  ${RELOCATING+${DTOR}}
+  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }
+  ${DATA_PLT+${PLT}}
+  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
+  ${GOT}
+  ${OTHER_GOT_SECTIONS}
+  ${CREATE_SHLIB+${SDATA2}}
+  ${CREATE_SHLIB+${SBSS2}}
+  ${SDATA}
+  ${OTHER_SDATA_SECTIONS}
+  ${RELOCATING+_edata = .;}
+  ${RELOCATING+PROVIDE (edata = .);}
+  ${RELOCATING+__bss_start = .;}
+  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
+  ${SBSS}
+  ${BSS_PLT+${PLT}}
+  .bss          ${RELOCATING-0} :
+  {
+   *(.dynbss)
+   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  }
+  ${OTHER_BSS_SECTIONS}
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+_end = .;}
+  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
+  ${RELOCATING+PROVIDE (end = .);}
+  ${RELOCATING+${DATA_SEGMENT_END}}
+
+  /* We want to be able to set a default stack / heap size in a dejagnu
+     board description file, but override it for selected test cases.
+     The options appear in the wrong order to do this with a single symbol -
+     ldflags comes after flags injected with per-file stanzas, and thus
+     the setting from ldflags prevails.  */
+  .heap ${RELOCATING-0} :
+  {
+        ${RELOCATING+ __start_heap = . ; }
+        ${RELOCATING+ . = . + (DEFINED(__HEAP_SIZE) ? __HEAP_SIZE : (DEFINED(__DEFAULT_HEAP_SIZE) ? __DEFAULT_HEAP_SIZE : 20k))  ; }
+        ${RELOCATING+ __end_heap = . ; }
+  }
+
+  ${RELOCATING+. = ALIGN(0x8);}
+  .stack ${RELOCATING-0} :
+  {
+        ${RELOCATING+ __stack = . ; }
+        ${RELOCATING+ . = . + (DEFINED(__STACK_SIZE) ? __STACK_SIZE : (DEFINED(__DEFAULT_STACK_SIZE) ? __DEFAULT_STACK_SIZE : 64k))  ; }
+        ${RELOCATING+ __stack_top = . ; }
+  }
+
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+
+  .comment       0 : { *(.comment) }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  /* ARC Extension Sections */
+  .arcextmap     0 : { *(.gnu.linkonce.arcextmap.*) }
+
+  ${STACK_ADDR+${STACK}}
+  ${OTHER_SECTIONS}
+  ${RELOCATING+${OTHER_END_SYMBOLS}}
+  ${RELOCATING+${STACKNOTE}}
+}
+EOF

diff --git a/ld/scripttempl/elfarcv2.sc b/ld/scripttempl/elfarcv2.sc
new file mode 100644 (file)
index 0000000..0232d81
--- /dev/null
+++ b/ld/scripttempl/elfarcv2.sc
@@ -0,0 +1,314 @@
+#
+# Unusual variables checked by this code:
+#      NOP - four byte opcode for no-op (defaults to 0)
+#      NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
+#              empty.
+#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
+#              (e.g., .PARISC.milli)
+# When adding sections, do note that the names of some sections are used
+# when specifying the start address of the next.
+#
+test -z "$ENTRY" && ENTRY=start
+test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+# If we request a big endian toolchain, give a big endian linker
+test -z "$GOT" && GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) } ${RELOCATING+ > ${DATA_MEMORY}}"
+test "${ARC_ENDIAN}" == "big" && OUTPUT_FORMAT=${BIG_OUTPUT_FORMAT}
+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
+test -z "${ELFSIZE}" && ELFSIZE=32
+test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
+test "$LD_FLAG" = "N" && DATA_ADDR=.
+
+CTOR=".ctors        ${CONSTRUCTING-0} : 
+  {
+    ${CONSTRUCTING+${CTOR_START}}
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+
+    KEEP (*crtbegin*.o(.ctors))
+
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ${CONSTRUCTING+${CTOR_END}}
+  } ${RELOCATING+ > ${DATA_MEMORY}}"
+DTOR=".dtors        ${CONSTRUCTING-0} :
+  {
+    ${CONSTRUCTING+${DTOR_START}}
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ${CONSTRUCTING+${DTOR_END}}
+  } ${RELOCATING+ > ${DATA_MEMORY}}"
+
+if test -z "${NO_SMALL_DATA}"; then
+  SBSS=".sbss         ${RELOCATING-0} :
+  {
+    ${RELOCATING+PROVIDE (__sbss_start = .);}
+    ${RELOCATING+PROVIDE (___sbss_start = .);}
+    *(.dynsbss)
+    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
+    *(.scommon)
+    ${RELOCATING+PROVIDE (__sbss_end = .);}
+    ${RELOCATING+PROVIDE (___sbss_end = .);}
+  } ${RELOCATING+ > ${SDATA_MEMORY}}"
+  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) } ${RELOCATING+ > ${SDATA_MEMORY}}"
+  SDATA="/* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata        ${RELOCATING-0} :
+  {
+    ${RELOCATING+${SDATA_START_SYMBOLS}}
+    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
+
+    ${RELOCATING+_edata  =  .;}
+    ${RELOCATING+PROVIDE (edata = .);}
+  } ${RELOCATING+ > ${SDATA_MEMORY}}"
+  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) } ${RELOCATING+ > ${SDATA_MEMORY}}"
+  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }
+  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
+  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }
+  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }"
+  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }
+  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }"
+  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }
+  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }"
+fi
+
+#
+# We provide two emulations: a fixed on that defines some memory banks
+# and a configurable one that includes a user provided memory definition.
+#
+case $GENERIC_BOARD in
+  yes|1|YES)
+       MEMORY_DEF="
+/* Get memory banks definition from some user configuration file.
+   This file must be located in some linker directory (search path
+   with -L<dir>). See fixed memory banks emulation script.  */
+INCLUDE memory.x;
+"
+       ;;
+  *)
+MEMORY_DEF="
+/* Fixed definition of the available memory banks.
+   See generic emulation script for a user defined configuration.  */
+MEMORY
+{
+    ICCM : ORIGIN = 0x00000000, LENGTH = ${ICCM_SIZE}
+    DCCM : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}
+}
+
+/* Setup the stack on the top of the data memory bank.  */
+PROVIDE (__stack_top = (${RAM_START_ADDR} + ${RAM_SIZE} - 1) & -4);
+PROVIDE (__end_heap = ${RAM_START_ADDR} + ${RAM_SIZE} - 1);
+"
+       ;;
+esac
+
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}", "${LITTLE_OUTPUT_FORMAT}")
+OUTPUT_ARCH(${OUTPUT_ARCH})
+${RELOCATING+ENTRY(${ENTRY})}
+
+${RELOCATING+${LIB_SEARCH_DIRS}}
+${RELOCATING+${EXECUTABLE_SYMBOLS}}
+${RELOCATING+${MEMORY_DEF}}
+
+SECTIONS
+{
+  .ivt 0x00 :
+  {
+   KEEP (*(.ivt));
+  } ${RELOCATING+ > ${STARTUP_MEMORY}}
+
+  .startup 0x100:
+  {
+    KEEP (*crt0.o(.text.__startup))
+  } ${RELOCATING+ > ${STARTUP_MEMORY}}
+
+  /* Read-only sections, merged into text segment: */
+  ${TEXT_DYNAMIC+${DYNAMIC}}
+  .hash        ${RELOCATING-0} : { *(.hash)            }
+  .dynsym      ${RELOCATING-0} : { *(.dynsym)          }
+  .dynstr      ${RELOCATING-0} : { *(.dynstr)          }
+  .gnu.version ${RELOCATING-0} : { *(.gnu.version)     }
+  .gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) }
+  .gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) }
+
+  .rel.init     ${RELOCATING-0} : { *(.rel.init) }
+  .rela.init    ${RELOCATING-0} : { *(.rela.init) }
+  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }
+  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }
+  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }
+  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }
+  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }
+  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }
+  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
+  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
+  .rel.tdata   ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
+  .rela.tdata  ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }
+  .rel.tbss    ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }
+  .rela.tbss   ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }
+  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }
+  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }
+  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }
+  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }
+  .rel.got      ${RELOCATING-0} : { *(.rel.got) }
+  .rela.got     ${RELOCATING-0} : { *(.rela.got) }
+  ${REL_SDATA}
+  ${REL_SBSS}
+  ${REL_SDATA2}
+  ${REL_SBSS2}
+  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }
+  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }
+
+  .jcr : { KEEP (*(.jcr)) } ${RELOCATING+> ${TEXT_MEMORY}}
+  .eh_frame : { KEEP (*(.eh_frame)) } ${RELOCATING+> ${TEXT_MEMORY}}
+  .gcc_except_table : { *(.gcc_except_table) *(.gcc_except_table.*) } ${RELOCATING+> ${TEXT_MEMORY}}
+  .plt : { *(.plt) } ${RELOCATING+> ${TEXT_MEMORY}}
+
+  .rodata ${RELOCATING-0} :
+  {
+    *(.rodata) ${RELOCATING+*(.rodata.*)} ${RELOCATING+*(.gnu.linkonce.r.*)}
+  } ${RELOCATING+> ${TEXT_MEMORY}}
+
+  .rodata1      ${RELOCATING-0} : { *(.rodata1) } ${RELOCATING+> ${TEXT_MEMORY}}
+
+  .init         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${INIT_START}}
+    KEEP (*(.init))
+    ${RELOCATING+${INIT_END}}
+  } ${RELOCATING+ > ${TEXT_MEMORY}}  =${NOP-0}
+
+  .text         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${TEXT_START_SYMBOLS}}
+
+    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+
+    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
+
+  } ${RELOCATING+ > ${TEXT_MEMORY}} =${NOP-0}
+
+  .fini         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${FINI_START}}
+    KEEP (*(.fini))
+    ${RELOCATING+${FINI_END}}
+
+    ${RELOCATING+PROVIDE (__etext = .);}
+    ${RELOCATING+PROVIDE (_etext = .);}
+    ${RELOCATING+PROVIDE (etext = .);}
+  } ${RELOCATING+ > ${TEXT_MEMORY}} =${NOP-0}
+
+  ${RELOCATING+${OTHER_READONLY_SECTIONS}}
+
+  /* Start of the data section image in ROM.  */
+  ${RELOCATING+__data_image = .;}
+  ${RELOCATING+PROVIDE (__data_image = .);}
+
+  .data        ${RELOCATING-0} :
+  {
+    ${RELOCATING+ PROVIDE (__data_start = .) ; }
+    /* --gc-sections will delete empty .data. This leads to wrong start
+       addresses for subsequent sections because -Tdata= from the command
+       line will have no effect, see PR13697.  Thus, keep .data  */
+    KEEP (*(.data))
+    ${RELOCATING+${DATA_START_SYMBOLS}}
+    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
+    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
+
+  } ${RELOCATING+ > ${DATA_MEMORY}}
+
+  ${GOT}
+  ${RELOCATING+${CTOR}}
+  ${RELOCATING+${DTOR}}
+
+  ${RELOCATING+${SDATA}}
+  ${RELOCATING+${SDATA2}}
+  ${RELOCATING+${SBSS}}
+  ${RELOCATING+${SBSS2}}
+  .bss          ${RELOCATING-0} :
+  {
+   *(.dynbss)
+   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+   ${RELOCATING+_end = .;}
+   ${RELOCATING+PROVIDE (end = .);}
+  } ${RELOCATING+ > ${DATA_MEMORY}}
+
+  /* Global data not cleared after reset.  */
+  .noinit ${RELOCATING-0}:
+  {
+    *(.noinit*)
+    ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+    ${RELOCATING+ PROVIDE (__start_heap = .) ; }
+  } ${RELOCATING+ > ${DATA_MEMORY}}
+
+
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+
+  .comment       0 : { *(.comment) }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+
+  /* DWARF 3 */
+  .debug_pubtypes 0 : { *(.debug_pubtypes) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+
+  /* DWARF Extension.  */
+  .debug_macro    0 : { *(.debug_macro) }
+
+  /* ARC Extension Sections */
+  .arcextmap     0 : { *(.gnu.linkonce.arcextmap.*) }
+}
+EOF

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 490aa50..95a58b8 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * ld-elf/linkonce1.d: Skip extra relocs before .debug_frame.
+
 2015-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/18914

diff --git a/ld/testsuite/ld-elf/linkonce1.d b/ld/testsuite/ld-elf/linkonce1.d
index c0e331f..e4f9a70 100644 (file)
--- a/ld/testsuite/ld-elf/linkonce1.d
+++ b/ld/testsuite/ld-elf/linkonce1.d
@@ -4,7 +4,7 @@
 #objdump: -r
 
 .*:     file format .*
-
+#...
 RELOCATION RECORDS FOR \[.debug_frame\]:
 OFFSET[        ]+TYPE[         ]+VALUE[        ]*
 .*(NONE|unused|UNUSED).*\*ABS\*

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 124ead7..c9c576f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
+
+       * arc-dis.c: Revamped file for ARC support
+       * arc-dis.h: Likewise.
+       * arc-ext.c: Likewise.
+       * arc-ext.h: Likewise.
+       * arc-opc.c: Likewise.
+       * arc-fxi.h: New file.
+       * arc-regs.h: Likewise.
+       * arc-tbl.h: Likewise.
+
 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 
        * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change

diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 617511b..516fc22 100644 (file)
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1,6 +1,7 @@
 /* Instruction printing code for the ARC.
    Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
    This file is part of libopcodes.
 
@@ -20,1207 +21,539 @@
    MA 02110-1301, USA.  */
 
 #include "sysdep.h"
-#include "libiberty.h"
+#include <stdio.h>
+#include <assert.h>
 #include "dis-asm.h"
 #include "opcode/arc.h"
-#include "elf-bfd.h"
-#include "elf/arc.h"
-#include "opintl.h"
-
-#include <stdarg.h>
 #include "arc-dis.h"
 #include "arc-ext.h"
 
-#ifndef dbg
-#define dbg (0)
-#endif
 
-/* Classification of the opcodes for the decoder to print
-   the instructions.  */
+/* Globals variables.  */
 
-typedef enum
+static const char * const regnames[64] =
 {
-  CLASS_A4_ARITH,
-  CLASS_A4_OP3_GENERAL,
-  CLASS_A4_FLAG,
-  /* All branches other than JC.  */
-  CLASS_A4_BRANCH,
-  CLASS_A4_JC ,
-  /* All loads other than immediate
-     indexed loads.  */
-  CLASS_A4_LD0,
-  CLASS_A4_LD1,
-  CLASS_A4_ST,
-  CLASS_A4_SR,
-  /* All single operand instructions.  */
-  CLASS_A4_OP3_SUBOPC3F,
-  CLASS_A4_LR
-} a4_decoding_class;
-
-#define BIT(word,n)    ((word) & (1 << n))
-#define BITS(word,s,e)  (((word) >> s) & ((1 << (e + 1 - s)) - 1))
+  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+  "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
+
+  "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
+  "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
+  "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
+  "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
+};
+
+/* Macros section.  */
+
+#ifdef DEBUG
+# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
+#else
+# define pr_debug(fmt, args...)
+#endif
+
+#define ARRANGE_ENDIAN(info, buf)                                      \
+  (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf))   \
+   : bfd_getb32 (buf))
+
+#define BITS(word,s,e)  (((word) << (sizeof (word) * 8 - 1 - e)) >>    \
+                        (s + (sizeof (word) * 8 - 1 - e)))
 #define OPCODE(word)   (BITS ((word), 27, 31))
 #define FIELDA(word)   (BITS ((word), 21, 26))
 #define FIELDB(word)   (BITS ((word), 15, 20))
 #define FIELDC(word)   (BITS ((word),  9, 14))
 
-/* FIELD D is signed.  */
-#define FIELDD(word)   ((BITS ((word), 0, 8) ^ 0x100) - 0x100)
-
-#define PUT_NEXT_WORD_IN(a)                                            \
-  do                                                                   \
-    {                                                                  \
-      if (is_limm == 1 && !NEXT_WORD (1))                              \
-        mwerror (state, _("Illegal limm reference in last instruction!\n")); \
-      a = state->words[1];                                             \
-    }                                                                  \
-  while (0)
-
-#define CHECK_FLAG_COND_NULLIFY()                              \
-  do                                                           \
-    {                                                          \
-      if (is_shimm == 0)                                       \
-        {                                                      \
-          flag = BIT (state->words[0], 8);                     \
-          state->nullifyMode = BITS (state->words[0], 5, 6);   \
-          cond = BITS (state->words[0], 0, 4);                 \
-        }                                                      \
-    }                                                          \
-  while (0)
-
-#define CHECK_COND()                           \
-  do                                           \
-    {                                          \
-      if (is_shimm == 0)                       \
-        cond = BITS (state->words[0], 0, 4);   \
-    }                                          \
-  while (0)
-
-#define CHECK_FIELD(field)                     \
-  do                                           \
-    {                                          \
-      if (field == 62)                         \
-        {                                      \
-          is_limm++;                           \
-         field##isReg = 0;                     \
-         PUT_NEXT_WORD_IN (field);             \
-         limm_value = field;                   \
-       }                                       \
-      else if (field > 60)                     \
-        {                                      \
-         field##isReg = 0;                     \
-         is_shimm++;                           \
-         flag = (field == 61);                 \
-         field = FIELDD (state->words[0]);     \
-       }                                       \
-    }                                          \
-  while (0)
-
-#define CHECK_FIELD_A()                                \
-  do                                           \
-    {                                          \
-      fieldA = FIELDA (state->words[0]);       \
-      if (fieldA > 60)                         \
-        {                                      \
-         fieldAisReg = 0;                      \
-         fieldA = 0;                           \
-       }                                       \
-    }                                          \
-  while (0)
-
-#define CHECK_FIELD_B()                                \
-  do                                           \
-    {                                          \
-      fieldB = FIELDB (state->words[0]);       \
-      CHECK_FIELD (fieldB);                    \
-    }                                          \
-  while (0)
-
-#define CHECK_FIELD_C()                                \
-  do                                           \
-    {                                          \
-      fieldC = FIELDC (state->words[0]);       \
-      CHECK_FIELD (fieldC);                    \
-    }                                          \
-  while (0)
-
-#define IS_SMALL(x)                 (((field##x) < 256) && ((field##x) > -257))
-#define IS_REG(x)                    (field##x##isReg)
-#define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT (x, "[","]","","")
-#define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT (x, "",",[","",",[")
-#define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT (x, ",","]",",","]")
-#define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT (x, "","]","","]")
-#define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT (x, ",","",",","")
-#define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT (x, "",",","",",")
-#define WRITE_FORMAT_x(x)            WRITE_FORMAT (x, "","","","")
-#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString,            \
-                                    (IS_REG (x) ? cb1"%r"ca1 :         \
-                                     usesAuxReg ? cb"%a"ca :           \
-                                     IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
-#define WRITE_FORMAT_RB()      strcat (formatString, "]")
-#define WRITE_COMMENT(str)     (state->comm[state->commNum++] = (str))
-#define WRITE_NOP_COMMENT()    if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
-
-#define NEXT_WORD(x)   (offset += 4, state->words[x])
-
-#define add_target(x)  (state->targets[state->tcnt++] = (x))
-
-static char comment_prefix[] = "\t; ";
-
-static const char *
-core_reg_name (struct arcDisState * state, int val)
-{
-  if (state->coreRegName)
-    return (*state->coreRegName)(state->_this, val);
-  return 0;
-}
+#define OPCODE_AC(word)   (BITS ((word), 11, 15))
 
-static const char *
-aux_reg_name (struct arcDisState * state, int val)
-{
-  if (state->auxRegName)
-    return (*state->auxRegName)(state->_this, val);
-  return 0;
-}
+/* Functions implementation.  */
 
-static const char *
-cond_code_name (struct arcDisState * state, int val)
+static bfd_vma
+bfd_getm32 (unsigned int data)
 {
-  if (state->condCodeName)
-    return (*state->condCodeName)(state->_this, val);
-  return 0;
-}
+  bfd_vma value = 0;
 
-static const char *
-instruction_name (struct arcDisState * state,
-                 int    op1,
-                 int    op2,
-                 int *  flags)
-{
-  if (state->instName)
-    return (*state->instName)(state->_this, op1, op2, flags);
-  return 0;
-}
-
-static void
-mwerror (struct arcDisState * state, const char * msg)
-{
-  if (state->err != 0)
-    (*state->err)(state->_this, (msg));
+  value = ((data & 0xff00) | (data & 0xff)) << 16;
+  value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
+  return value;
 }
 
-static const char *
-post_address (struct arcDisState * state, int addr)
+static int
+special_flag_p (const char *opname,
+               const char *flgname)
 {
-  static char id[3 * ARRAY_SIZE (state->addresses)];
-  int j, i = state->acnt;
+  const struct arc_flag_special *flg_spec;
+  size_t len;
+  unsigned i, j, flgidx;
 
-  if (i < ((int) ARRAY_SIZE (state->addresses)))
+  for (i = 0; i < arc_num_flag_special; i++)
     {
-      state->addresses[i] = addr;
-      ++state->acnt;
-      j = i*3;
-      id[j+0] = '@';
-      id[j+1] = '0'+i;
-      id[j+2] = 0;
-
-      return id + j;
-    }
-  return "";
-}
-
-static void
-arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
-{
-  char *bp;
-  const char *p;
-  int size, leading_zero, regMap[2];
-  va_list ap;
-
-  va_start (ap, format);
-
-  bp = buf;
-  *bp = 0;
-  p = format;
-  regMap[0] = 0;
-  regMap[1] = 0;
-
-  while (1)
-    switch (*p++)
-      {
-      case 0:
-       goto DOCOMM; /* (return)  */
-      default:
-       *bp++ = p[-1];
-       break;
-      case '%':
-       size = 0;
-       leading_zero = 0;
-      RETRY: ;
-       switch (*p++)
-         {
-         case '0':
-         case '1':
-         case '2':
-         case '3':
-         case '4':
-         case '5':
-         case '6':
-         case '7':
-         case '8':
-         case '9':
-           {
-             /* size.  */
-             size = p[-1] - '0';
-             if (size == 0)
-               leading_zero = 1; /* e.g. %08x  */
-             while (*p >= '0' && *p <= '9')
-               {
-                 size = size * 10 + *p - '0';
-                 p++;
-               }
-             goto RETRY;
-           }
-#define inc_bp() bp = bp + strlen (bp)
-
-         case 'h':
-           {
-             unsigned u = va_arg (ap, int);
-
-             /* Hex.  We can change the format to 0x%08x in
-                one place, here, if we wish.
-                We add underscores for easy reading.  */
-             if (u > 65536)
-               sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
-             else
-               sprintf (bp, "0x%x", u);
-             inc_bp ();
-           }
-           break;
-         case 'X': case 'x':
-           {
-             int val = va_arg (ap, int);
-
-             if (size != 0)
-               if (leading_zero)
-                 sprintf (bp, "%0*x", size, val);
-               else
-                 sprintf (bp, "%*x", size, val);
-             else
-               sprintf (bp, "%x", val);
-             inc_bp ();
-           }
-           break;
-         case 'd':
-           {
-             int val = va_arg (ap, int);
+      flg_spec = &arc_flag_special_cases[i];
+      len = strlen (flg_spec->name);
 
-             if (size != 0)
-               sprintf (bp, "%*d", size, val);
-             else
-               sprintf (bp, "%d", val);
-             inc_bp ();
-           }
-           break;
-         case 'r':
-           {
-             /* Register.  */
-             int val = va_arg (ap, int);
-
-#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
-  regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
+      if (strncmp (opname, flg_spec->name, len) != 0)
+       continue;
 
-             switch (val)
-               {
-                 REG2NAME (26, "gp");
-                 REG2NAME (27, "fp");
-                 REG2NAME (28, "sp");
-                 REG2NAME (29, "ilink1");
-                 REG2NAME (30, "ilink2");
-                 REG2NAME (31, "blink");
-                 REG2NAME (60, "lp_count");
-               default:
-                 {
-                   const char * ext;
-
-                   ext = core_reg_name (state, val);
-                   if (ext)
-                     sprintf (bp, "%s", ext);
-                   else
-                     sprintf (bp,"r%d",val);
-                 }
-                 break;
-               }
-             inc_bp ();
-           } break;
-
-         case 'a':
-           {
-             /* Aux Register.  */
-             int val = va_arg (ap, int);
-
-#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
-
-             switch (val)
-               {
-                 AUXREG2NAME (0x0, "status");
-                 AUXREG2NAME (0x1, "semaphore");
-                 AUXREG2NAME (0x2, "lp_start");
-                 AUXREG2NAME (0x3, "lp_end");
-                 AUXREG2NAME (0x4, "identity");
-                 AUXREG2NAME (0x5, "debug");
-               default:
-                 {
-                   const char *ext;
-
-                   ext = aux_reg_name (state, val);
-                   if (ext)
-                     sprintf (bp, "%s", ext);
-                   else
-                     arc_sprintf (state, bp, "%h", val);
-                 }
-                 break;
-               }
-             inc_bp ();
-           }
-           break;
-
-         case 's':
-           {
-             sprintf (bp, "%s", va_arg (ap, char *));
-             inc_bp ();
-           }
-           break;
-
-         default:
-           fprintf (stderr, "?? format %c\n", p[-1]);
-           break;
-         }
-      }
-
- DOCOMM: *bp = 0;
-  va_end (ap);
-}
-
-static void
-write_comments_(struct arcDisState * state,
-               int shimm,
-               int is_limm,
-               long limm_value)
-{
-  if (state->commentBuffer != 0)
-    {
-      int i;
-
-      if (is_limm)
+      /* Found potential special case instruction.  */
+      for (j=0;; ++j)
        {
-         const char *name = post_address (state, limm_value + shimm);
+         flgidx = flg_spec->flags[j];
+         if (flgidx == 0)
+           break; /* End of the array.  */
 
-         if (*name != 0)
-           WRITE_COMMENT (name);
-       }
-      for (i = 0; i < state->commNum; i++)
-       {
-         if (i == 0)
-           strcpy (state->commentBuffer, comment_prefix);
-         else
-           strcat (state->commentBuffer, ", ");
-         strcat (state->commentBuffer, state->comm[i]);
+         if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
+           return 1;
        }
     }
+  return 0;
 }
 
-#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
-#define write_comments()   write_comments2 (0)
-
-static const char *condName[] =
-{
-  /* 0..15.  */
-  ""   , "z"  , "nz" , "p"  , "n"  , "c"  , "nc" , "v"  ,
-  "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
-};
+/* Disassemble ARC instructions.  */
 
-static void
-write_instr_name_(struct arcDisState * state,
-                 const char * instrName,
-                 int cond,
-                 int condCodeIsPartOfName,
-                 int flag,
-                 int signExtend,
-                 int addrWriteBack,
-                 int directMem)
+static int
+print_insn_arc (bfd_vma memaddr,
+               struct disassemble_info *info)
 {
-  strcpy (state->instrBuffer, instrName);
+  bfd_byte buffer[4];
+  unsigned int lowbyte, highbyte;
+  int status;
+  unsigned int i;
+  int insnLen = 0;
+  unsigned insn[2], isa_mask;
+  const unsigned char *opidx;
+  const unsigned char *flgidx;
+  const struct arc_opcode *opcode;
+  const char *instrName;
+  int flags;
+  bfd_boolean need_comma;
+  bfd_boolean open_braket;
 
-  if (cond > 0)
-    {
-      const char *cc = 0;
 
-      if (!condCodeIsPartOfName)
-       strcat (state->instrBuffer, ".");
+  lowbyte  = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
+  highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
 
-      if (cond < 16)
-       cc = condName[cond];
-      else
-       cc = cond_code_name (state, cond);
+  switch (info->mach)
+    {
+    case bfd_mach_arc_arc700:
+      isa_mask = ARC_OPCODE_ARC700;
+      break;
 
-      if (!cc)
-       cc = "???";
+    case bfd_mach_arc_arc600:
+      isa_mask = ARC_OPCODE_ARC600;
+      break;
 
-      strcat (state->instrBuffer, cc);
+    case bfd_mach_arc_arcv2:
+    default:
+      isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
+      break;
     }
 
-  if (flag)
-    strcat (state->instrBuffer, ".f");
-
-  switch (state->nullifyMode)
+  /* Read the insn into a host word.  */
+  status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+  if (status != 0)
     {
-    case BR_exec_always:
-      strcat (state->instrBuffer, ".d");
-      break;
-    case BR_exec_when_jump:
-      strcat (state->instrBuffer, ".jd");
-      break;
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
     }
 
-  if (signExtend)
-    strcat (state->instrBuffer, ".x");
-
-  if (addrWriteBack)
-    strcat (state->instrBuffer, ".a");
-
-  if (directMem)
-    strcat (state->instrBuffer, ".di");
-}
-
-#define write_instr_name()                                             \
-  do                                                                   \
-    {                                                                  \
-      write_instr_name_(state, instrName,cond, condCodeIsPartOfName,   \
-                       flag, signExtend, addrWriteBack, directMem);    \
-      formatString[0] = '\0';                                          \
-    }                                                                  \
-  while (0)
-
-enum
-{
-  op_LD0 = 0, op_LD1 = 1, op_ST  = 2, op_3   = 3,
-  op_BC  = 4, op_BLC = 5, op_LPC = 6, op_JC  = 7,
-  op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
-  op_AND = 12, op_OR  = 13, op_BIC = 14, op_XOR = 15
-};
-
-extern disassemble_info tm_print_insn_info;
-
-static int
-dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
-{
-  int condCodeIsPartOfName = 0;
-  a4_decoding_class decodingClass;
-  const char * instrName;
-  int repeatsOp = 0;
-  int fieldAisReg = 1;
-  int fieldBisReg = 1;
-  int fieldCisReg = 1;
-  int fieldA;
-  int fieldB;
-  int fieldC = 0;
-  int flag = 0;
-  int cond = 0;
-  int is_shimm = 0;
-  int is_limm = 0;
-  long limm_value = 0;
-  int signExtend = 0;
-  int addrWriteBack = 0;
-  int directMem = 0;
-  int is_linked = 0;
-  int offset = 0;
-  int usesAuxReg = 0;
-  int flags;
-  int ignoreFirstOpd;
-  char formatString[60];
-
-  state->instructionLen = 4;
-  state->nullifyMode = BR_exec_when_no_jump;
-  state->opWidth = 12;
-  state->isBranch = 0;
-
-  state->_mem_load = 0;
-  state->_ea_present = 0;
-  state->_load_len = 0;
-  state->ea_reg1 = no_reg;
-  state->ea_reg2 = no_reg;
-  state->_offset = 0;
-
-  if (! NEXT_WORD (0))
-    return 0;
-
-  state->_opcode = OPCODE (state->words[0]);
-  instrName = 0;
-  decodingClass = CLASS_A4_ARITH; /* default!  */
-  repeatsOp = 0;
-  condCodeIsPartOfName=0;
-  state->commNum = 0;
-  state->tcnt = 0;
-  state->acnt = 0;
-  state->flow = noflow;
-  ignoreFirstOpd = 0;
-
-  if (state->commentBuffer)
-    state->commentBuffer[0] = '\0';
-
-  switch (state->_opcode)
+  if (info->section
+      && !(info->section->flags & SEC_CODE))
     {
-    case op_LD0:
-      switch (BITS (state->words[0],1,2))
+      /* Sort of data section, just print a 32 bit number.  */
+      insnLen = 4;
+      status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
+      if (status != 0)
        {
-       case 0:
-         instrName = "ld";
-         state->_load_len = 4;
-         break;
-       case 1:
-         instrName = "ldb";
-         state->_load_len = 1;
-         break;
-       case 2:
-         instrName = "ldw";
-         state->_load_len = 2;
-         break;
-       default:
-         instrName = "??? (0[3])";
-         state->flow = invalid_instr;
-         break;
+         (*info->memory_error_func) (status, memaddr + 2, info);
+         return -1;
        }
-      decodingClass = CLASS_A4_LD0;
-      break;
+      insn[0] = ARRANGE_ENDIAN (info, buffer);
+      (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
+      return insnLen;
+    }
 
-    case op_LD1:
-      if (BIT (state->words[0],13))
-       {
-         instrName = "lr";
-         decodingClass = CLASS_A4_LR;
-       }
-      else
+  if ((((buffer[lowbyte] & 0xf8) > 0x38)
+       && ((buffer[lowbyte] & 0xf8) != 0x48))
+      || ((info->mach == bfd_mach_arc_arcv2)
+         && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly.  */
+      )
+    {
+      /* This is a short instruction.  */
+      insnLen = 2;
+      insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
+    }
+  else
+    {
+      insnLen = 4;
+
+      /* This is a long instruction: Read the remaning 2 bytes.  */
+      status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
+      if (status != 0)
        {
-         switch (BITS (state->words[0], 10, 11))
-           {
-           case 0:
-             instrName = "ld";
-             state->_load_len = 4;
-             break;
-           case 1:
-             instrName = "ldb";
-             state->_load_len = 1;
-             break;
-           case 2:
-             instrName = "ldw";
-             state->_load_len = 2;
-             break;
-           default:
-             instrName = "??? (1[3])";
-             state->flow = invalid_instr;
-             break;
-           }
-         decodingClass = CLASS_A4_LD1;
+         (*info->memory_error_func) (status, memaddr + 2, info);
+         return -1;
        }
-      break;
+      insn[0] = ARRANGE_ENDIAN (info, buffer);
+    }
+
+  /* This variable may be set by the instruction decoder.  It suggests
+     the number of bytes objdump should display on a single line.  If
+     the instruction decoder sets this, it should always set it to
+     the same value in order to get reasonable looking output.  */
+  info->bytes_per_line  = 8;
+
+  /* The next two variables control the way objdump displays the raw data.
+     For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the
+     output will look like this:
+     00:   00000000 00000000
+     with the chunks displayed according to "display_endian".  */
+  info->bytes_per_chunk = 2;
+  info->display_endian  = info->endian;
+
+  /* Set some defaults for the insn info.  */
+  info->insn_info_valid    = 1;
+  info->branch_delay_insns = 0;
+  info->data_size         = 0;
+  info->insn_type         = dis_nonbranch;
+  info->target            = 0;
+  info->target2                   = 0;
+
+  /* FIXME to be moved in dissasemble_init_for_target.  */
+  info->disassembler_needs_relocs = TRUE;
+
+  /* Find the first match in the opcode table.  */
+  for (i = 0; i < arc_num_opcodes; i++)
+    {
+      bfd_boolean invalid = FALSE;
+
+      opcode = &arc_opcodes[i];
 
-    case op_ST:
-      if (BIT (state->words[0], 25))
+      if (ARC_SHORT (opcode->mask) && (insnLen == 2))
        {
-         instrName = "sr";
-         decodingClass = CLASS_A4_SR;
+         if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
+           continue;
        }
-      else
+      else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
        {
-         switch (BITS (state->words[0], 22, 23))
-           {
-           case 0:
-             instrName = "st";
-             break;
-           case 1:
-             instrName = "stb";
-             break;
-           case 2:
-             instrName = "stw";
-             break;
-           default:
-             instrName = "??? (2[3])";
-             state->flow = invalid_instr;
-             break;
-           }
-         decodingClass = CLASS_A4_ST;
+         if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
+           continue;
        }
-      break;
+      else
+       continue;
+
+      if ((insn[0] ^ opcode->opcode) & opcode->mask)
+       continue;
 
-    case op_3:
-      decodingClass = CLASS_A4_OP3_GENERAL;  /* default for opcode 3...  */
-      switch (FIELDC (state->words[0]))
+      if (!(opcode->cpu & isa_mask))
+       continue;
+
+      /* Possible candidate, check the operands.  */
+      for (opidx = opcode->operands; *opidx; opidx++)
        {
-       case  0:
-         instrName = "flag";
-         decodingClass = CLASS_A4_FLAG;
-         break;
-       case  1:
-         instrName = "asr";
-         break;
-       case  2:
-         instrName = "lsr";
-         break;
-       case  3:
-         instrName = "ror";
-         break;
-       case  4:
-         instrName = "rrc";
-         break;
-       case  5:
-         instrName = "sexb";
-         break;
-       case  6:
-         instrName = "sexw";
-         break;
-       case  7:
-         instrName = "extb";
-         break;
-       case  8:
-         instrName = "extw";
-         break;
-       case  0x3f:
-         {
-           decodingClass = CLASS_A4_OP3_SUBOPC3F;
-           switch (FIELDD (state->words[0]))
-             {
-             case 0:
-               instrName = "brk";
-               break;
-             case 1:
-               instrName = "sleep";
-               break;
-             case 2:
-               instrName = "swi";
-               break;
-             default:
-               instrName = "???";
-               state->flow=invalid_instr;
-               break;
-             }
-         }
-         break;
-
-         /* ARC Extension Library Instructions
-            NOTE: We assume that extension codes are these instrs.  */
-       default:
-         instrName = instruction_name (state,
-                                       state->_opcode,
-                                       FIELDC (state->words[0]),
-                                       &flags);
-         if (!instrName)
+         int value;
+         const struct arc_operand *operand = &arc_operands[*opidx];
+
+         if (operand->flags & ARC_OPERAND_FAKE)
+           continue;
+
+         if (operand->extract)
+           value = (*operand->extract) (insn[0], &invalid);
+         else
+           value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+
+         /* Check for LIMM indicator.  If it is there, then make sure
+            we pick the right format.  */
+         if (operand->flags & ARC_OPERAND_IR
+             && !(operand->flags & ARC_OPERAND_LIMM))
            {
-             instrName = "???";
-             state->flow = invalid_instr;
+             if ((value == 0x3E && insnLen == 4)
+                 || (value == 0x1E && insnLen == 2))
+               {
+                 invalid = TRUE;
+                 break;
+               }
            }
-         if (flags & IGNORE_FIRST_OPD)
-           ignoreFirstOpd = 1;
-         break;
        }
-      break;
 
-    case op_BC:
-      instrName = "b";
-    case op_BLC:
-      if (!instrName)
-       instrName = "bl";
-    case op_LPC:
-      if (!instrName)
-       instrName = "lp";
-    case op_JC:
-      if (!instrName)
+      /* Check the flags.  */
+      for (flgidx = opcode->flags; *flgidx; flgidx++)
        {
-         if (BITS (state->words[0],9,9))
+         /* Get a valid flag class.  */
+         const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+         const unsigned *flgopridx;
+         int foundA = 0, foundB = 0;
+
+         for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
            {
-             instrName = "jl";
-             is_linked = 1;
+             const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
+             unsigned int value;
+
+             value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
+             if (value == flg_operand->code)
+               foundA = 1;
+             if (value)
+               foundB = 1;
            }
-         else
+         if (!foundA && foundB)
            {
-             instrName = "j";
-             is_linked = 0;
+             invalid = TRUE;
+             break;
            }
        }
-      condCodeIsPartOfName = 1;
-      decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
-      state->isBranch = 1;
-      break;
 
-    case op_ADD:
-    case op_ADC:
-    case op_AND:
-      repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
+      if (invalid)
+       continue;
 
-      switch (state->_opcode)
-       {
-       case op_ADD:
-         instrName = (repeatsOp ? "asl" : "add");
-         break;
-       case op_ADC:
-         instrName = (repeatsOp ? "rlc" : "adc");
-         break;
-       case op_AND:
-         instrName = (repeatsOp ? "mov" : "and");
-         break;
-       }
-      break;
+      /* The instruction is valid.  */
+      goto found;
+    }
 
-    case op_SUB: instrName = "sub";
-      break;
-    case op_SBC: instrName = "sbc";
-      break;
-    case op_OR:  instrName = "or";
-      break;
-    case op_BIC: instrName = "bic";
-      break;
+  /* No instruction found.  Try the extenssions.  */
+  instrName = arcExtMap_instName (OPCODE (insn[0]), insn[0], &flags);
+  if (instrName)
+    {
+      opcode = &arc_opcodes[0];
+      (*info->fprintf_func) (info->stream, "%s", instrName);
+      goto print_flags;
+    }
 
-    case op_XOR:
-      if (state->words[0] == 0x7fffffff)
-       {
-         /* NOP encoded as xor -1, -1, -1.   */
-         instrName = "nop";
-         decodingClass = CLASS_A4_OP3_SUBOPC3F;
-       }
+  if (insnLen == 2)
+    (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
+  else
+    (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
+
+  info->insn_type = dis_noninsn;
+  return insnLen;
+
+ found:
+  /* Print the mnemonic.  */
+  (*info->fprintf_func) (info->stream, "%s", opcode->name);
+
+  /* Preselect the insn class.  */
+  switch (opcode->class)
+    {
+    case BRANCH:
+    case JUMP:
+      if (!strncmp (opcode->name, "bl", 2)
+         || !strncmp (opcode->name, "jl", 2))
+       info->insn_type = dis_jsr;
       else
-       instrName = "xor";
+       info->insn_type = dis_branch;
+      break;
+    case MEMORY:
+      info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
       break;
-
     default:
-      instrName = instruction_name (state,state->_opcode,0,&flags);
-      /* if (instrName) printf("FLAGS=0x%x\n", flags);  */
-      if (!instrName)
-       {
-         instrName = "???";
-         state->flow=invalid_instr;
-       }
-      if (flags & IGNORE_FIRST_OPD)
-       ignoreFirstOpd = 1;
+      info->insn_type = dis_nonbranch;
       break;
     }
 
-  fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now.  */
-  flag = cond = is_shimm = is_limm = 0;
-  state->nullifyMode = BR_exec_when_no_jump;   /* 0  */
-  signExtend = addrWriteBack = directMem = 0;
-  usesAuxReg = 0;
+  pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
 
-  switch (decodingClass)
+ print_flags:
+  /* Now extract and print the flags.  */
+  for (flgidx = opcode->flags; *flgidx; flgidx++)
     {
-    case CLASS_A4_ARITH:
-      CHECK_FIELD_A ();
-      CHECK_FIELD_B ();
-      if (!repeatsOp)
-       CHECK_FIELD_C ();
-      CHECK_FLAG_COND_NULLIFY ();
-
-      write_instr_name ();
-      if (!ignoreFirstOpd)
-       {
-         WRITE_FORMAT_x (A);
-         WRITE_FORMAT_COMMA_x (B);
-         if (!repeatsOp)
-           WRITE_FORMAT_COMMA_x (C);
-         WRITE_NOP_COMMENT ();
-         arc_sprintf (state, state->operandBuffer, formatString,
-                     fieldA, fieldB, fieldC);
-       }
-      else
-       {
-         WRITE_FORMAT_x (B);
-         if (!repeatsOp)
-           WRITE_FORMAT_COMMA_x (C);
-         arc_sprintf (state, state->operandBuffer, formatString,
-                     fieldB, fieldC);
-       }
-      write_comments ();
-      break;
-
-    case CLASS_A4_OP3_GENERAL:
-      CHECK_FIELD_A ();
-      CHECK_FIELD_B ();
-      CHECK_FLAG_COND_NULLIFY ();
+      /* Get a valid flag class.  */
+      const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+      const unsigned *flgopridx;
 
-      write_instr_name ();
-      if (!ignoreFirstOpd)
-       {
-         WRITE_FORMAT_x (A);
-         WRITE_FORMAT_COMMA_x (B);
-         WRITE_NOP_COMMENT ();
-         arc_sprintf (state, state->operandBuffer, formatString,
-                     fieldA, fieldB);
-       }
-      else
+      for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
        {
-         WRITE_FORMAT_x (B);
-         arc_sprintf (state, state->operandBuffer, formatString, fieldB);
-       }
-      write_comments ();
-      break;
+         const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
+         unsigned int value;
 
-    case CLASS_A4_FLAG:
-      CHECK_FIELD_B ();
-      CHECK_FLAG_COND_NULLIFY ();
-      flag = 0; /* This is the FLAG instruction -- it's redundant.  */
-
-      write_instr_name ();
-      WRITE_FORMAT_x (B);
-      arc_sprintf (state, state->operandBuffer, formatString, fieldB);
-      write_comments ();
-      break;
+         if (!flg_operand->favail)
+           continue;
 
-    case CLASS_A4_BRANCH:
-      fieldA = BITS (state->words[0],7,26) << 2;
-      fieldA = (fieldA << 10) >> 10; /* Make it signed.  */
-      fieldA += addr + 4;
-      CHECK_FLAG_COND_NULLIFY ();
-      flag = 0;
+         value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
+         if (value == flg_operand->code)
+           {
+              /* FIXME!: print correctly nt/t flag.  */
+             if (!special_flag_p (opcode->name, flg_operand->name))
+               (*info->fprintf_func) (info->stream, ".");
+             else if (info->insn_type == dis_dref)
+               {
+                 switch (flg_operand->name[0])
+                   {
+                   case 'b':
+                     info->data_size = 1;
+                     break;
+                   case 'h':
+                   case 'w':
+                     info->data_size = 2;
+                     break;
+                   default:
+                     info->data_size = 4;
+                     break;
+                   }
+               }
+             (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
+           }
 
-      write_instr_name ();
-      /* This address could be a label we know. Convert it.  */
-      if (state->_opcode != op_LPC /* LP  */)
-       {
-         add_target (fieldA); /* For debugger.  */
-         state->flow = state->_opcode == op_BLC /* BL  */
-           ? direct_call
-           : direct_jump;
-         /* indirect calls are achieved by "lr blink,[status];
-            lr dest<- func addr; j [dest]"  */
+         if (flg_operand->name[0] == 'd'
+             && flg_operand->name[1] == 0)
+           info->branch_delay_insns = 1;
        }
+    }
 
-      strcat (formatString, "%s"); /* Address/label name.  */
-      arc_sprintf (state, state->operandBuffer, formatString,
-                 post_address (state, fieldA));
-      write_comments ();
-      break;
+  if (opcode->operands[0] != 0)
+    (*info->fprintf_func) (info->stream, "\t");
 
-    case CLASS_A4_JC:
-      /* For op_JC -- jump to address specified.
-        Also covers jump and link--bit 9 of the instr. word
-        selects whether linked, thus "is_linked" is set above.  */
-      fieldA = 0;
-      CHECK_FIELD_B ();
-      CHECK_FLAG_COND_NULLIFY ();
+  need_comma = FALSE;
+  open_braket = FALSE;
 
-      if (!fieldBisReg)
-       {
-         fieldAisReg = 0;
-         fieldA = (fieldB >> 25) & 0x7F; /* Flags.  */
-         fieldB = (fieldB & 0xFFFFFF) << 2;
-         state->flow = is_linked ? direct_call : direct_jump;
-         add_target (fieldB);
-         /* Screwy JLcc requires .jd mode to execute correctly
-            but we pretend it is .nd (no delay slot).  */
-         if (is_linked && state->nullifyMode == BR_exec_when_jump)
-           state->nullifyMode = BR_exec_when_no_jump;
-       }
-      else
-       {
-         state->flow = is_linked ? indirect_call : indirect_jump;
-         /* We should also treat this as indirect call if NOT linked
-            but the preceding instruction was a "lr blink,[status]"
-            and we have a delay slot with "add blink,blink,2".
-            For now we can't detect such.  */
-         state->register_for_indirect_jump = fieldB;
-       }
+  /* Now extract and print the operands.  */
+  for (opidx = opcode->operands; *opidx; opidx++)
+    {
+      const struct arc_operand *operand = &arc_operands[*opidx];
+      int value;
 
-      write_instr_name ();
-      strcat (formatString,
-             IS_REG (B) ? "[%r]" : "%s"); /* Address/label name.  */
-      if (fieldA != 0)
+      if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
        {
-         fieldAisReg = 0;
-         WRITE_FORMAT_COMMA_x (A);
+         (*info->fprintf_func) (info->stream, "]");
+         open_braket = FALSE;
+         continue;
        }
-      if (IS_REG (B))
-       arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
-      else
-       arc_sprintf (state, state->operandBuffer, formatString,
-                   post_address (state, fieldB), fieldA);
-      write_comments ();
-      break;
-
-    case CLASS_A4_LD0:
-      /* LD instruction.
-        B and C can be regs, or one (both?) can be limm.  */
-      CHECK_FIELD_A ();
-      CHECK_FIELD_B ();
-      CHECK_FIELD_C ();
-      if (dbg)
-       printf ("5:b reg %d %d c reg %d %d  \n",
-               fieldBisReg,fieldB,fieldCisReg,fieldC);
-      state->_offset = 0;
-      state->_ea_present = 1;
-      if (fieldBisReg)
-       state->ea_reg1 = fieldB;
-      else
-       state->_offset += fieldB;
-      if (fieldCisReg)
-       state->ea_reg2 = fieldC;
-      else
-       state->_offset += fieldC;
-      state->_mem_load = 1;
-
-      directMem     = BIT (state->words[0], 5);
-      addrWriteBack = BIT (state->words[0], 3);
-      signExtend    = BIT (state->words[0], 0);
-
-      write_instr_name ();
-      WRITE_FORMAT_x_COMMA_LB(A);
-      if (fieldBisReg || fieldB != 0)
-       WRITE_FORMAT_x_COMMA (B);
-      else
-       fieldB = fieldC;
 
-      WRITE_FORMAT_x_RB (C);
-      arc_sprintf (state, state->operandBuffer, formatString,
-                 fieldA, fieldB, fieldC);
-      write_comments ();
-      break;
+      /* Only take input from real operands.  */
+      if ((operand->flags & ARC_OPERAND_FAKE)
+         && !(operand->flags & ARC_OPERAND_BRAKET))
+       continue;
 
-    case CLASS_A4_LD1:
-      /* LD instruction.  */
-      CHECK_FIELD_B ();
-      CHECK_FIELD_A ();
-      fieldC = FIELDD (state->words[0]);
-
-      if (dbg)
-       printf ("6:b reg %d %d c 0x%x  \n",
-               fieldBisReg, fieldB, fieldC);
-      state->_ea_present = 1;
-      state->_offset = fieldC;
-      state->_mem_load = 1;
-      if (fieldBisReg)
-       state->ea_reg1 = fieldB;
-      /* Field B is either a shimm (same as fieldC) or limm (different!)
-        Say ea is not present, so only one of us will do the name lookup.  */
+      if (operand->extract)
+       value = (*operand->extract) (insn[0], (int *) NULL);
       else
-       state->_offset += fieldB, state->_ea_present = 0;
-
-      directMem     = BIT (state->words[0],14);
-      addrWriteBack = BIT (state->words[0],12);
-      signExtend    = BIT (state->words[0],9);
-
-      write_instr_name ();
-      WRITE_FORMAT_x_COMMA_LB (A);
-      if (!fieldBisReg)
        {
-         fieldB = state->_offset;
-         WRITE_FORMAT_x_RB (B);
-       }
-      else
-       {
-         WRITE_FORMAT_x (B);
-         if (fieldC != 0 && !BIT (state->words[0],13))
+         if (operand->flags & ARC_OPERAND_ALIGNED32)
            {
-             fieldCisReg = 0;
-             WRITE_FORMAT_COMMA_x_RB (C);
+             value = (insn[0] >> operand->shift)
+               & ((1 << (operand->bits - 2)) - 1);
+             value = value << 2;
            }
          else
-           WRITE_FORMAT_RB ();
+           {
+             value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+           }
+         if (operand->flags & ARC_OPERAND_SIGNED)
+           {
+             int signbit = 1 << (operand->bits - 1);
+             value = (value ^ signbit) - signbit;
+           }
        }
-      arc_sprintf (state, state->operandBuffer, formatString,
-                 fieldA, fieldB, fieldC);
-      write_comments ();
-      break;
 
-    case CLASS_A4_ST:
-      /* ST instruction.  */
-      CHECK_FIELD_B();
-      CHECK_FIELD_C();
-      fieldA = FIELDD(state->words[0]); /* shimm  */
-
-      /* [B,A offset]  */
-      if (dbg) printf("7:b reg %d %x off %x\n",
-                     fieldBisReg,fieldB,fieldA);
-      state->_ea_present = 1;
-      state->_offset = fieldA;
-      if (fieldBisReg)
-       state->ea_reg1 = fieldB;
-      /* Field B is either a shimm (same as fieldA) or limm (different!)
-        Say ea is not present, so only one of us will do the name lookup.
-        (for is_limm we do the name translation here).  */
-      else
-       state->_offset += fieldB, state->_ea_present = 0;
+      if (operand->flags & ARC_OPERAND_IGNORE
+         && (operand->flags & ARC_OPERAND_IR
+             && value == -1))
+       continue;
 
-      directMem     = BIT (state->words[0], 26);
-      addrWriteBack = BIT (state->words[0], 24);
+      if (need_comma)
+       (*info->fprintf_func) (info->stream, ",");
 
-      write_instr_name ();
-      WRITE_FORMAT_x_COMMA_LB(C);
-
-      if (!fieldBisReg)
+      if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
        {
-         fieldB = state->_offset;
-         WRITE_FORMAT_x_RB (B);
+         (*info->fprintf_func) (info->stream, "[");
+         open_braket = TRUE;
+         need_comma = FALSE;
+         continue;
        }
-      else
+
+      /* Read the limm operand, if required.  */
+      if (operand->flags & ARC_OPERAND_LIMM
+         && !(operand->flags & ARC_OPERAND_DUPLICATE))
        {
-         WRITE_FORMAT_x (B);
-         if (fieldBisReg && fieldA != 0)
+         status = (*info->read_memory_func) (memaddr + insnLen, buffer,
+                                             4, info);
+         if (status != 0)
            {
-             fieldAisReg = 0;
-             WRITE_FORMAT_COMMA_x_RB(A);
+             (*info->memory_error_func) (status, memaddr + insnLen, info);
+             return -1;
            }
-         else
-           WRITE_FORMAT_RB();
+         insn[1] = ARRANGE_ENDIAN (info, buffer);
        }
-      arc_sprintf (state, state->operandBuffer, formatString,
-                 fieldC, fieldB, fieldA);
-      write_comments2 (fieldA);
-      break;
-
-    case CLASS_A4_SR:
-      /* SR instruction  */
-      CHECK_FIELD_B();
-      CHECK_FIELD_C();
-
-      write_instr_name ();
-      WRITE_FORMAT_x_COMMA_LB(C);
-      /* Try to print B as an aux reg if it is not a core reg.  */
-      usesAuxReg = 1;
-      WRITE_FORMAT_x (B);
-      WRITE_FORMAT_RB ();
-      arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
-      write_comments ();
-      break;
 
-    case CLASS_A4_OP3_SUBOPC3F:
-      write_instr_name ();
-      state->operandBuffer[0] = '\0';
-      break;
-
-    case CLASS_A4_LR:
-      /* LR instruction */
-      CHECK_FIELD_A ();
-      CHECK_FIELD_B ();
-
-      write_instr_name ();
-      WRITE_FORMAT_x_COMMA_LB (A);
-      /* Try to print B as an aux reg if it is not a core reg. */
-      usesAuxReg = 1;
-      WRITE_FORMAT_x (B);
-      WRITE_FORMAT_RB ();
-      arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
-      write_comments ();
-      break;
+      /* Print the operand as directed by the flags.  */
+      if (operand->flags & ARC_OPERAND_IR)
+       {
+         assert (value >=0 && value < 64);
+         (*info->fprintf_func) (info->stream, "%s", regnames[value]);
+         if (operand->flags & ARC_OPERAND_TRUNCATE)
+           (*info->fprintf_func) (info->stream, "%s", regnames[value+1]);
+       }
+      else if (operand->flags & ARC_OPERAND_LIMM)
+       {
+         (*info->fprintf_func) (info->stream, "%#x", insn[1]);
+         if (info->insn_type == dis_branch
+             || info->insn_type == dis_jsr)
+           info->target = (bfd_vma) insn[1];
+       }
+      else if (operand->flags & ARC_OPERAND_PCREL)
+       {
+          /* PCL relative.  */
+         if (info->flags & INSN_HAS_RELOC)
+           memaddr = 0;
+         (*info->print_address_func) ((memaddr & ~3) + value, info);
 
-    default:
-      mwerror (state, "Bad decoding class in ARC disassembler");
-      break;
+         info->target = (bfd_vma) (memaddr & ~3) + value;
+       }
+      else if (operand->flags & ARC_OPERAND_SIGNED)
+       (*info->fprintf_func) (info->stream, "%d", value);
+      else
+       if (operand->flags & ARC_OPERAND_TRUNCATE
+           && !(operand->flags & ARC_OPERAND_ALIGNED32)
+           && !(operand->flags & ARC_OPERAND_ALIGNED16)
+           && value > 0 && value <= 14)
+         (*info->fprintf_func) (info->stream, "r13-%s",
+                                regnames[13 + value - 1]);
+       else
+         (*info->fprintf_func) (info->stream, "%#x", value);
+
+      need_comma = TRUE;
+
+      /* Adjust insn len.  */
+      if (operand->flags & ARC_OPERAND_LIMM
+         && !(operand->flags & ARC_OPERAND_DUPLICATE))
+       insnLen += 4;
     }
 
-  state->_cond = cond;
-  return state->instructionLen = offset;
-}
-
-
-/* Returns the name the user specified core extension register.  */
-
-static const char *
-_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
-{
-  return arcExtMap_coreRegName (regval);
+  return insnLen;
 }
 
-/* Returns the name the user specified AUX extension register.  */
 
-static const char *
-_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
-{
-  return arcExtMap_auxRegName(regval);
-}
-
-/* Returns the name the user specified condition code name.  */
-
-static const char *
-_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
+disassembler_ftype
+arc_get_disassembler (bfd *abfd)
 {
-  return arcExtMap_condCodeName(regval);
-}
+  /* Read the extenssion insns and registers, if any.  */
+  build_ARC_extmap (abfd);
+  dump_ARC_extmap ();
 
-/* Returns the name the user specified extension instruction.  */
-
-static const char *
-_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
-{
-  return arcExtMap_instName(majop, minop, flags);
+  return print_insn_arc;
 }
 
-/* Decode an instruction returning the size of the instruction
-   in bytes or zero if unrecognized.  */
+/* Disassemble ARC instructions.  Used by debugger.  */
 
-static int
-decodeInstr (bfd_vma            address, /* Address of this instruction.  */
-            disassemble_info * info)
+struct arcDisState
+arcAnalyzeInstr (bfd_vma memaddr,
+                struct disassemble_info *info)
 {
-  int status;
-  bfd_byte buffer[4];
-  struct arcDisState s;                /* ARC Disassembler state.  */
-  void *stream = info->stream;         /* Output stream.  */
-  fprintf_ftype func = info->fprintf_func;
-
-  memset (&s, 0, sizeof(struct arcDisState));
-
-  /* read first instruction  */
-  status = (*info->read_memory_func) (address, buffer, 4, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, address, info);
-      return 0;
-    }
-  if (info->endian == BFD_ENDIAN_LITTLE)
-    s.words[0] = bfd_getl32(buffer);
-  else
-    s.words[0] = bfd_getb32(buffer);
-  /* Always read second word in case of limm.  */
-
-  /* We ignore the result since last insn may not have a limm.  */
-  status = (*info->read_memory_func) (address + 4, buffer, 4, info);
-  if (info->endian == BFD_ENDIAN_LITTLE)
-    s.words[1] = bfd_getl32(buffer);
-  else
-    s.words[1] = bfd_getb32(buffer);
-
-  s._this = &s;
-  s.coreRegName = _coreRegName;
-  s.auxRegName = _auxRegName;
-  s.condCodeName = _condCodeName;
-  s.instName = _instName;
-
-  /* Disassemble.  */
-  dsmOneArcInst (address, & s);
-
-  /* Display the disassembly instruction.  */
-  (*func) (stream, "%08lx ", s.words[0]);
-  (*func) (stream, "    ");
-  (*func) (stream, "%-10s ", s.instrBuffer);
-
-  if (__TRANSLATION_REQUIRED (s))
-    {
-      bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
-
-      (*info->print_address_func) ((bfd_vma) addr, info);
-      (*func) (stream, "\n");
-    }
-  else
-    (*func) (stream, "%s",s.operandBuffer);
+  struct arcDisState ret;
+  memset (&ret, 0, sizeof (struct arcDisState));
+
+  ret.instructionLen = print_insn_arc (memaddr, info);
+
+#if 0
+  ret.words[0] = insn[0];
+  ret.words[1] = insn[1];
+  ret._this = &ret;
+  ret.coreRegName = _coreRegName;
+  ret.auxRegName = _auxRegName;
+  ret.condCodeName = _condCodeName;
+  ret.instName = _instName;
+#endif
 
-  return s.instructionLen;
+  return ret;
 }
 
-/* Return the print_insn function to use.
-   Side effect: load (possibly empty) extension section  */
-
-disassembler_ftype
-arc_get_disassembler (void *ptr)
-{
-  if (ptr)
-    build_ARC_extmap ((struct bfd *) ptr);
-  return decodeInstr;
-}
+/* Local variables:
+   eval: (c-set-style "gnu")
+   indent-tabs-mode: t
+   End:  */

diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h
index dc73322..bcb88e5 100644 (file)
--- a/opcodes/arc-dis.h
+++ b/opcodes/arc-dis.h
@@ -1,6 +1,7 @@
 /* Disassembler structures definitions for the ARC.
    Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
    This file is part of libopcodes.
 
@@ -21,11 +22,15 @@
 #ifndef ARCDIS_H
 #define ARCDIS_H
 
-enum
+enum ARC_Debugger_OperandType
 {
-  BR_exec_when_no_jump,
-  BR_exec_always,
-  BR_exec_when_jump
+    ARC_UNDEFINED,
+    ARC_LIMM,
+    ARC_SHIMM,
+    ARC_REGISTER,
+    ARCOMPACT_REGISTER /* Valid only for the
+                         registers allowed in
+                         16 bit mode.  */
 };
 
 enum Flow
@@ -38,7 +43,13 @@ enum Flow
   invalid_instr
 };
 
-enum { no_reg = 99 };
+enum NullifyMode
+{
+  BR_exec_when_no_jump,
+  BR_exec_always,
+  BR_exec_when_jump
+};
+
 enum { allOperandsSize = 256 };
 
 struct arcDisState
@@ -53,10 +64,21 @@ struct arcDisState
 
   unsigned char* instruction;
   unsigned index;
-  const char *comm[6]; /* instr name, cond, NOP, 3 operands  */
+  const char *comm[6]; /* Instr name, cond, NOP, 3 operands.  */
+
+  union
+  {
+    unsigned int registerNum;
+    unsigned int shortimm;
+    unsigned int longimm;
+  } source_operand;
+  enum ARC_Debugger_OperandType sourceType;
+
   int opWidth;
   int targets[4];
-  int addresses[4];
+  /* START ARC LOCAL.  */
+  unsigned int addresses[4];
+  /* END ARC LOCAL.  */
   /* Set as a side-effect of calling the disassembler.
      Used only by the debugger.  */
   enum Flow flow;
@@ -68,15 +90,16 @@ struct arcDisState
   char instrBuffer[40];
   char operandBuffer[allOperandsSize];
   char _ea_present;
+  char _addrWriteBack; /* Address writeback.  */
   char _mem_load;
   char _load_len;
-  char nullifyMode;
+  enum NullifyMode nullifyMode;
   unsigned char commNum;
   unsigned char isBranch;
   unsigned char tcnt;
   unsigned char acnt;
 };
 
-#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
-
+struct arcDisState
+arcAnalyzeInstr (bfd_vma memaddr, struct disassemble_info *);
 #endif

diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index d2b3f12..3267fb5 100644 (file)
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -1,4 +1,4 @@
-/* ARC target-dependent stuff. Extension structure access functions
+/* ARC target-dependent stuff.  Extension structure access functions
    Copyright (C) 1995-2015 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
@@ -21,137 +21,88 @@
 #include "sysdep.h"
 #include <stdlib.h>
 #include <stdio.h>
+
 #include "bfd.h"
 #include "arc-ext.h"
+#include "elf/arc.h"
 #include "libiberty.h"
 
-/* Extension structure  */
-static struct arcExtMap arc_extension_map;
 
-/* Get the name of an extension instruction.  */
+/* This module provides support for extensions to the ARC processor
+   architecture.  */
 
-const char *
-arcExtMap_instName(int opcode, int minor, int *flags)
-{
-    if (opcode == 3)
-      {
-       /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi  */
-       if (minor < 0x09 || minor == 0x3f)
-         return 0;
-       else
-         opcode = 0x1f - 0x10 + minor - 0x09 + 1;
-      }
-    else
-      if (opcode < 0x10)
-       return 0;
-    else
-      opcode -= 0x10;
-    if (!arc_extension_map.instructions[opcode])
-      return 0;
-    *flags = arc_extension_map.instructions[opcode]->flags;
-    return arc_extension_map.instructions[opcode]->name;
-}
 
-/* Get the name of an extension core register.  */
+/* Local constants.  */
 
-const char *
-arcExtMap_coreRegName(int value)
-{
-  if (value < 32)
-    return 0;
-  return arc_extension_map.coreRegisters[value-32];
-}
+#define FIRST_EXTENSION_CORE_REGISTER   32
+#define LAST_EXTENSION_CORE_REGISTER    59
+#define FIRST_EXTENSION_CONDITION_CODE  0x10
+#define LAST_EXTENSION_CONDITION_CODE   0x1f
 
-/* Get the name of an extension condition code.  */
+#define NUM_EXT_CORE      \
+  (LAST_EXTENSION_CORE_REGISTER  - FIRST_EXTENSION_CORE_REGISTER  + 1)
+#define NUM_EXT_COND      \
+  (LAST_EXTENSION_CONDITION_CODE - FIRST_EXTENSION_CONDITION_CODE + 1)
+#define INST_HASH_BITS    6
+#define INST_HASH_SIZE    (1 << INST_HASH_BITS)
+#define INST_HASH_MASK    (INST_HASH_SIZE - 1)
 
-const char *
-arcExtMap_condCodeName(int value)
-{
-  if (value < 16)
-    return 0;
-  return arc_extension_map.condCodes[value-16];
-}
 
-/* Get the name of an extension aux register.  */
+/* Local types.  */
 
-const char *
-arcExtMap_auxRegName(long address)
-{
-  /* walk the list of aux reg names and find the name  */
-  struct ExtAuxRegister *r;
+/* These types define the information stored in the table.  */
 
-  for (r = arc_extension_map.auxRegisters; r; r = r->next) {
-    if (r->address == address)
-      return (const char *) r->name;
-  }
-  return 0;
-}
+struct ExtInstruction
+{
+  char                  major;
+  char                  minor;
+  char                  flags;
+  char*                         name;
+  struct ExtInstruction* next;
+};
+
+struct ExtAuxRegister
+{
+  long                  address;
+  char*                         name;
+  struct ExtAuxRegister* next;
+};
 
-/* Recursively free auxilliary register strcture pointers until
-   the list is empty.  */
+struct ExtCoreRegister
+{
+  short                    number;
+  enum ExtReadWrite rw;
+  char*                    name;
+};
 
-static void
-clean_aux_registers(struct ExtAuxRegister *r)
+struct arcExtMap
 {
-  if (r -> next)
-    {
-      clean_aux_registers( r->next);
-      free(r -> name);
-      free(r -> next);
-      r ->next = NULL;
-    }
-  else
-    free(r -> name);
-}
+  struct ExtAuxRegister* auxRegisters;
+  struct ExtInstruction* instructions[INST_HASH_SIZE];
+  struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
+  char*                         condCodes[NUM_EXT_COND];
+};
 
-/* Free memory that has been allocated for the extensions.  */
 
-static void
-cleanup_ext_map(void)
-{
-  struct ExtAuxRegister *r;
-  struct ExtInstruction *insn;
-  int i;
+/* Local data.  */
 
-  /* clean aux reg structure  */
-  r = arc_extension_map.auxRegisters;
-  if (r)
-    {
-      (clean_aux_registers(r));
-      free(r);
-    }
+/* Extension table.  */
+static struct arcExtMap arc_extension_map;
 
-  /* clean instructions  */
-  for (i = 0; i < NUM_EXT_INST; i++)
-    {
-      insn = arc_extension_map.instructions[i];
-      if (insn)
-       free(insn->name);
-    }
 
-  /* clean core reg struct  */
-  for (i = 0; i < NUM_EXT_CORE; i++)
-    {
-      if (arc_extension_map.coreRegisters[i])
-       free(arc_extension_map.coreRegisters[i]);
-    }
+/* Local macros.  */
 
-  for (i = 0; i < NUM_EXT_COND; i++) {
-    if (arc_extension_map.condCodes[i])
-      free(arc_extension_map.condCodes[i]);
-  }
+/* A hash function used to map instructions into the table.  */
+#define INST_HASH(MAJOR, MINOR)    ((((MAJOR) << 3) ^ (MINOR)) & INST_HASH_MASK)
 
-  memset(&arc_extension_map, 0, sizeof(struct arcExtMap));
-}
 
-int
-arcExtMap_add(void *base, unsigned long length)
-{
-  unsigned char *block = (unsigned char *) base;
-  unsigned char *p = (unsigned char *) block;
+/* Local functions.  */
 
-  /* Clean up and reset everything if needed.  */
-  cleanup_ext_map();
+static void
+create_map (unsigned char *block,
+           unsigned long length)
+{
+  unsigned char *p = block;
 
   while (p && p < (block + length))
     {
@@ -165,97 +116,384 @@ arcExtMap_add(void *base, unsigned long length)
         For core regs and condition codes:
           p[2]  = value
           p[3]+ = name
-        For aux regs:
+        For auxiliary regs:
           p[2..5] = value
           p[6]+   = name
-        (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5])  */
+            (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]).  */
 
+      /* The sequence of records is temrinated by an "empty"
+        record.  */
       if (p[0] == 0)
-       return -1;
+       break;
 
       switch (p[1])
        {
        case EXT_INSTRUCTION:
          {
-           char opcode = p[2];
-           char minor  = p[3];
-           char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
-           struct ExtInstruction * insn =
-             (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
-
-           if (opcode==3)
-             opcode = 0x1f - 0x10 + minor - 0x09 + 1;
-           else
-             opcode -= 0x10;
-           insn -> flags = (char) *(p+4);
-           strcpy (insn_name, (char *) (p+5));
-           insn -> name = insn_name;
-           arc_extension_map.instructions[(int) opcode] = insn;
+           struct ExtInstruction  *insn = XNEW (struct ExtInstruction);
+           int                     major = p[2];
+           int                     minor = p[3];
+           struct ExtInstruction **bucket =
+                  &arc_extension_map.instructions[INST_HASH (major, minor)];
+
+           insn->name  = xstrdup ((char *) (p + 5));
+           insn->major = major;
+           insn->minor = minor;
+           insn->flags = p[4];
+           insn->next  = *bucket;
+           *bucket = insn;
+           break;
          }
-         break;
 
        case EXT_CORE_REGISTER:
          {
-           char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
+           unsigned char number = p[2];
+           char*         name   = (char *) (p + 3);
+
+           arc_extension_map.
+             coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
+             = number;
+           arc_extension_map.
+             coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
+             = REG_READWRITE;
+           arc_extension_map.
+             coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
+             = xstrdup (name);
+           break;
+         }
 
-           strcpy(core_name, (char *) (p+3));
-           arc_extension_map.coreRegisters[p[2]-32] = core_name;
+       case EXT_LONG_CORE_REGISTER:
+         {
+           unsigned char     number = p[2];
+           char*             name   = (char *) (p + 7);
+           enum ExtReadWrite rw     = p[6];
+
+           arc_extension_map.
+             coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
+             = number;
+           arc_extension_map.
+             coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
+             = rw;
+           arc_extension_map.
+             coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
+             = xstrdup (name);
          }
-         break;
 
        case EXT_COND_CODE:
          {
-           char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
-           strcpy(cc_name, (char *) (p+3));
-           arc_extension_map.condCodes[p[2]-16] = cc_name;
+           char *cc_name = xstrdup ((char *) (p + 3));
+
+           arc_extension_map.
+             condCodes[p[2] - FIRST_EXTENSION_CONDITION_CODE]
+             = cc_name;
+           break;
          }
-         break;
 
        case EXT_AUX_REGISTER:
          {
-           /* trickier -- need to store linked list to these  */
-           struct ExtAuxRegister *newAuxRegister =
-             (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
-           char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
+           /* Trickier -- need to store linked list of these.  */
+           struct ExtAuxRegister *newAuxRegister
+             = XNEW (struct ExtAuxRegister);
+           char *aux_name = xstrdup ((char *) (p + 6));
 
-           strcpy (aux_name, (char *) (p+6));
            newAuxRegister->name = aux_name;
-           newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8  | p[5];
+           newAuxRegister->address = (p[2] << 24) | (p[3] << 16)
+             | (p[4] << 8) | p[5];
            newAuxRegister->next = arc_extension_map.auxRegisters;
            arc_extension_map.auxRegisters = newAuxRegister;
+           break;
          }
-         break;
 
        default:
-         return -1;
+         break;
+       }
+
+      p += p[0]; /* Move on to next record.  */
+    }
+}
+
+
+/* Free memory that has been allocated for the extensions.  */
+
+static void
+destroy_map (void)
+{
+  struct ExtAuxRegister *r;
+  unsigned int          i;
+
+  /* Free auxiliary registers.  */
+  r = arc_extension_map.auxRegisters;
+  while (r)
+    {
+      /* N.B. after r has been freed, r->next is invalid!  */
+      struct ExtAuxRegister* next = r->next;
+
+      free (r->name);
+      free (r);
+      r = next;
+    }
+
+  /* Free instructions.  */
+  for (i = 0; i < INST_HASH_SIZE; i++)
+    {
+      struct ExtInstruction *insn = arc_extension_map.instructions[i];
+
+      while (insn)
+       {
+         /* N.B. after insn has been freed, insn->next is invalid!  */
+         struct ExtInstruction *next = insn->next;
+
+         free (insn->name);
+         free (insn);
+         insn = next;
+       }
+    }
+
+  /* Free core registers.  */
+  for (i = 0; i < NUM_EXT_CORE; i++)
+    {
+      if (arc_extension_map.coreRegisters[i].name)
+       free (arc_extension_map.coreRegisters[i].name);
+    }
 
+  /* Free condition codes.  */
+  for (i = 0; i < NUM_EXT_COND; i++)
+    {
+      if (arc_extension_map.condCodes[i])
+       free (arc_extension_map.condCodes[i]);
+    }
+
+  memset (&arc_extension_map, 0, sizeof (arc_extension_map));
+}
+
+
+static const char *
+ExtReadWrite_image (enum ExtReadWrite val)
+{
+    switch (val)
+    {
+       case REG_INVALID  : return "INVALID";
+       case REG_READ     : return "RO";
+       case REG_WRITE    : return "WO";
+       case REG_READWRITE: return "R/W";
+       default           : return "???";
+    }
+}
+
+
+/* Externally visible functions.  */
+
+/* Get the name of an extension instruction.  */
+
+const char *
+arcExtMap_instName (int opcode,
+                   int insn,
+                   int *flags)
+{
+  /* Here the following tasks need to be done.  First of all, the
+     opcode stored in the Extension Map is the real opcode.  However,
+     the subopcode stored in the instruction to be disassembled is
+     mangled.  We pass (in minor opcode), the instruction word.  Here
+     we will un-mangle it and get the real subopcode which we can look
+     for in the Extension Map.  This function is used both for the
+     ARCTangent and the ARCompact, so we would also need some sort of
+     a way to distinguish between the two architectures.  This is
+     because the ARCTangent does not do any of this mangling so we
+     have no issues there.  */
+
+  /* If P[22:23] is 0 or 2 then un-mangle using iiiiiI.  If it is 1
+     then use iiiiIi.  Now, if P is 3 then check M[5:5] and if it is 0
+     then un-mangle using iiiiiI else iiiiii.  */
+
+  unsigned char minor;
+  struct ExtInstruction *temp;
+
+  /* 16-bit instructions.  */
+  if (0x08 <= opcode && opcode <= 0x0b)
+    {
+      unsigned char b, c, i;
+
+      b = (insn & 0x0700) >> 8;
+      c = (insn & 0x00e0) >> 5;
+      i = (insn & 0x001f);
+
+      if (i)
+       minor = i;
+      else
+       minor = (c == 0x07) ? b : c;
+    }
+  /* 32-bit instructions.  */
+  else
+    {
+      unsigned char I, A, B;
+
+      I = (insn & 0x003f0000) >> 16;
+      A = (insn & 0x0000003f);
+      B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9);
+
+      if (I != 0x2f)
+       {
+#ifndef UNMANGLED
+         switch (P)
+           {
+           case 3:
+             if (M)
+               {
+                 minor = I;
+                 break;
+               }
+           case 0:
+           case 2:
+             minor = (I >> 1) | ((I & 0x1) << 5);
+             break;
+           case 1:
+             minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4);
+           }
+#else
+         minor = I;
+#endif
+       }
+      else
+       {
+         if (A != 0x3f)
+           minor = A;
+         else
+           minor = B;
+       }
+    }
+
+  temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
+  while (temp)
+    {
+      if ((temp->major == opcode) && (temp->minor == minor))
+       {
+         *flags = temp->flags;
+         return temp->name;
        }
-      p += p[0]; /* move to next record  */
+      temp = temp->next;
     }
 
-  return 0;
+  return NULL;
 }
 
-/* Load hw extension descibed in .extArcMap ELF section.  */
+/* Get the name of an extension core register.  */
 
-void
-build_ARC_extmap (text_bfd)
-  bfd *text_bfd;
+const char *
+arcExtMap_coreRegName (int regnum)
+{
+  if (regnum < FIRST_EXTENSION_CORE_REGISTER
+      || regnum > LAST_EXTENSION_CONDITION_CODE)
+    return NULL;
+  return arc_extension_map.
+    coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
+}
+
+/* Get the access mode of an extension core register.  */
+
+enum ExtReadWrite
+arcExtMap_coreReadWrite (int regnum)
 {
-  char *arcExtMap;
-  bfd_size_type count;
-  asection *p;
+  if (regnum < FIRST_EXTENSION_CORE_REGISTER
+      || regnum > LAST_EXTENSION_CONDITION_CODE)
+    return REG_INVALID;
+  return arc_extension_map.
+    coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
+}
+
+/* Get the name of an extension condition code.  */
+
+const char *
+arcExtMap_condCodeName (int code)
+{
+  if (code < FIRST_EXTENSION_CONDITION_CODE
+      || code > LAST_EXTENSION_CONDITION_CODE)
+    return NULL;
+  return arc_extension_map.
+    condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
+}
+
+/* Get the name of an extension auxiliary register.  */
+
+const char *
+arcExtMap_auxRegName (long address)
+{
+  /* Walk the list of auxiliary register names and find the name.  */
+  struct ExtAuxRegister *r;
+
+  for (r = arc_extension_map.auxRegisters; r; r = r->next)
+    {
+      if (r->address == address)
+       return (const char *)r->name;
+    }
+  return NULL;
+}
+
+/* Load extensions described in .arcextmap and
+   .gnu.linkonce.arcextmap.* ELF section.  */
 
-  for (p = text_bfd->sections; p != NULL; p = p->next)
-    if (!strcmp (p->name, ".arcextmap"))
+void
+build_ARC_extmap (bfd *text_bfd)
+{
+  asection *sect;
+
+  /* The map is built each time gdb loads an executable file - so free
+     any existing map, as the map defined by the new file may differ
+     from the old.  */
+  destroy_map ();
+
+  for (sect = text_bfd->sections; sect != NULL; sect = sect->next)
+    if (!strncmp (sect->name,
+                 ".gnu.linkonce.arcextmap.",
+         sizeof (".gnu.linkonce.arcextmap.") - 1)
+       || !strcmp (sect->name,".arcextmap"))
       {
-        count = bfd_get_section_size (p);
-        arcExtMap = (char *) xmalloc (count);
-        if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
-          {
-            arcExtMap_add ((PTR) arcExtMap, count);
-            break;
-          }
-        free ((PTR) arcExtMap);
+       bfd_size_type  count  = bfd_get_section_size (sect);
+       unsigned char* buffer = xmalloc (count);
+
+       if (buffer)
+         {
+           if (bfd_get_section_contents (text_bfd, sect, buffer, 0, count))
+             create_map (buffer, count);
+           free (buffer);
+         }
       }
 }
+
+
+void
+dump_ARC_extmap (void)
+{
+    struct ExtAuxRegister *r;
+    int                           i;
+
+    r = arc_extension_map.auxRegisters;
+
+    while (r)
+    {
+       printf ("AUX : %s %ld\n", r->name, r->address);
+       r = r->next;
+    }
+
+    for (i = 0; i < INST_HASH_SIZE; i++)
+    {
+       struct ExtInstruction *insn;
+
+       for (insn = arc_extension_map.instructions[i];
+            insn != NULL; insn = insn->next)
+           printf ("INST: %d %d %x %s\n", insn->major, insn->minor,
+                   insn->flags, insn->name);
+    }
+
+    for (i = 0; i < NUM_EXT_CORE; i++)
+    {
+       struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
+
+       if (reg.name)
+           printf ("CORE: %s %d %s\n", reg.name, reg.number,
+                   ExtReadWrite_image (reg.rw));
+    }
+
+    for (i = 0; i < NUM_EXT_COND; i++)
+       if (arc_extension_map.condCodes[i])
+           printf ("COND: %s\n", arc_extension_map.condCodes[i]);
+}

diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
index 8a7d7c4..9eb46ae 100644 (file)
--- a/opcodes/arc-ext.h
+++ b/opcodes/arc-ext.h
@@ -1,4 +1,4 @@
-/* ARC target-dependent stuff. Extension data structures.
+/* ARC target-dependent stuff.  Extension data structures.
    Copyright (C) 1995-2015 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
@@ -18,46 +18,72 @@
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-#ifndef ARCEXT_H
-#define ARCEXT_H
+/*This header file defines a table of extensions to the ARC processor
+  architecture.  These extensions are read from the '.arcextmap' or
+  '.gnu.linkonce.arcextmap.<type>.<N>' sections in the ELF file which
+  is identified by the bfd parameter to the build_ARC_extmap function.
 
-enum {EXT_INSTRUCTION   = 0,
-      EXT_CORE_REGISTER = 1,
-      EXT_AUX_REGISTER  = 2,
-      EXT_COND_CODE     = 3};
+  These extensions may include:
+        core registers
+        auxiliary registers
+        instructions
+        condition codes
 
-enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
-enum {NUM_EXT_CORE = 59-32+1};
-enum {NUM_EXT_COND = 0x1f-0x10+1};
+  Once the table has been constructed, accessor functions may be used
+  to retrieve information from it.
 
-struct ExtInstruction
-{
-  char flags;
-  char *name;
-};
+  The build_ARC_extmap constructor function build_ARC_extmap may be
+  called as many times as required; it will re-initialize the table
+  each time.  */
+
+#ifndef ARC_EXTENSIONS_H
+#define ARC_EXTENSIONS_H
+
+#define IGNORE_FIRST_OPD 1
+
+/* Define this if we do not want to encode instructions based on the
+   ARCompact Programmer's Reference.  */
+#define UNMANGLED
 
-struct ExtAuxRegister
+
+/* This defines the kinds of extensions which may be read from the
+   ections in the executable files.  */
+enum ExtOperType
 {
-  long address;
-  char *name;
-  struct ExtAuxRegister *next;
+  EXT_INSTRUCTION           = 0,
+  EXT_CORE_REGISTER         = 1,
+  EXT_AUX_REGISTER          = 2,
+  EXT_COND_CODE                     = 3,
+  EXT_INSTRUCTION32         = 4,
+  EXT_AC_INSTRUCTION        = 4,
+  EXT_REMOVE_CORE_REG       = 5,
+  EXT_LONG_CORE_REGISTER     = 6,
+  EXT_AUX_REGISTER_EXTENDED  = 7,
+  EXT_INSTRUCTION32_EXTENDED = 8,
+  EXT_CORE_REGISTER_CLASS    = 9
 };
 
-struct arcExtMap
+
+enum ExtReadWrite
 {
-  struct ExtAuxRegister *auxRegisters;
-  struct ExtInstruction *instructions[NUM_EXT_INST];
-  char *coreRegisters[NUM_EXT_CORE];
-  char *condCodes[NUM_EXT_COND];
+  REG_INVALID,
+  REG_READ,
+  REG_WRITE,
+  REG_READWRITE
 };
 
-extern int arcExtMap_add(void*, unsigned long);
-extern const char *arcExtMap_coreRegName(int);
-extern const char *arcExtMap_auxRegName(long);
-extern const char *arcExtMap_condCodeName(int);
-extern const char *arcExtMap_instName(int, int, int*);
-extern void build_ARC_extmap(bfd *);
 
-#define IGNORE_FIRST_OPD 1
+/* Constructor function.  */
+extern void build_ARC_extmap (bfd *);
+
+/* Accessor functions.  */
+extern enum ExtReadWrite arcExtMap_coreReadWrite (int);
+extern const char * arcExtMap_coreRegName (int);
+extern const char * arcExtMap_auxRegName (long);
+extern const char * arcExtMap_condCodeName (int);
+extern const char * arcExtMap_instName (int, int, int *);
+
+/* Dump function (for debugging).  */
+extern void dump_ARC_extmap (void);
 
-#endif
+#endif /* ARC_EXTENSIONS_H */

diff --git a/opcodes/arc-fxi.h b/opcodes/arc-fxi.h
new file mode 100644 (file)
index 0000000..5f36982
--- /dev/null
+++ b/opcodes/arc-fxi.h
@@ -0,0 +1,1317 @@
+/* Insert/extract functions for the ARC opcodes.
+   Copyright 2015 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef INSERT_LIMM
+#define INSERT_LIMM
+/* mask = 00000000000000000000000000000000
+   insn = 00100bbb00101111FBBB111110001001.  */
+static unsigned
+insert_limm (unsigned insn ATTRIBUTE_UNUSED,
+            int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  return insn;
+}
+#endif /* INSERT_LIMM */
+
+#ifndef EXTRACT_LIMM
+#define EXTRACT_LIMM
+/* mask = 00000000000000000000000000000000.  */
+static ATTRIBUTE_UNUSED int
+extract_limm (unsigned insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  return value;
+}
+#endif /* EXTRACT_LIMM */
+
+#ifndef INSERT_UIMM6_20
+#define INSERT_UIMM6_20
+/* mask = 00000000000000000000111111000000
+   insn = 00100bbb01101111FBBBuuuuuu001001.  */
+static unsigned
+insert_uimm6_20 (unsigned insn ATTRIBUTE_UNUSED,
+                int value ATTRIBUTE_UNUSED,
+                const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x003f) << 6;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_20 */
+
+#ifndef EXTRACT_UIMM6_20
+#define EXTRACT_UIMM6_20
+/* mask = 00000000000000000000111111000000.  */
+static int
+extract_uimm6_20 (unsigned insn ATTRIBUTE_UNUSED,
+                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 6) & 0x003f) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_20 */
+
+#ifndef INSERT_SIMM12_20
+#define INSERT_SIMM12_20
+/* mask = 00000000000000000000111111222222
+   insn = 00110bbb10101000FBBBssssssSSSSSS.  */
+static unsigned
+insert_simm12_20 (unsigned insn ATTRIBUTE_UNUSED,
+                 int value ATTRIBUTE_UNUSED,
+                 const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x003f) << 6;
+  insn |= ((value >> 6) & 0x003f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM12_20 */
+
+#ifndef EXTRACT_SIMM12_20
+#define EXTRACT_SIMM12_20
+/* mask = 00000000000000000000111111222222.  */
+static int
+extract_simm12_20 (unsigned insn ATTRIBUTE_UNUSED,
+                  bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 6) & 0x003f) << 0;
+  value |= ((insn >> 0) & 0x003f) << 6;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (12 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM12_20 */
+
+#ifndef INSERT_SIMM3_5_S
+#define INSERT_SIMM3_5_S
+/* mask = 0000011100000000
+   insn = 01110ssshhh001HH.  */
+static ATTRIBUTE_UNUSED unsigned
+insert_simm3_5_s (unsigned insn ATTRIBUTE_UNUSED,
+                 int value ATTRIBUTE_UNUSED,
+                 const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x0007) << 8;
+
+  return insn;
+}
+#endif /* INSERT_SIMM3_5_S */
+
+#ifndef EXTRACT_SIMM3_5_S
+#define EXTRACT_SIMM3_5_S
+/* mask = 0000011100000000.  */
+static ATTRIBUTE_UNUSED int
+extract_simm3_5_s (unsigned insn ATTRIBUTE_UNUSED,
+                  bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 8) & 0x0007) << 0;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (3 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM3_5_S */
+
+#ifndef INSERT_LIMM_S
+#define INSERT_LIMM_S
+/* mask = 0000000000000000
+   insn = 01110sss11000111.  */
+static ATTRIBUTE_UNUSED unsigned
+insert_limm_s (unsigned insn ATTRIBUTE_UNUSED,
+              int value ATTRIBUTE_UNUSED,
+              const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  return insn;
+}
+#endif /* INSERT_LIMM_S */
+
+#ifndef EXTRACT_LIMM_S
+#define EXTRACT_LIMM_S
+/* mask = 0000000000000000.  */
+static ATTRIBUTE_UNUSED int
+extract_limm_s (unsigned insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  return value;
+}
+#endif /* EXTRACT_LIMM_S */
+
+#ifndef INSERT_UIMM7_A32_11_S
+#define INSERT_UIMM7_A32_11_S
+/* mask = 0000000000011111
+   insn = 11000bbb100uuuuu.  */
+static unsigned
+insert_uimm7_a32_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x001f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM7_A32_11_S */
+
+#ifndef EXTRACT_UIMM7_A32_11_S
+#define EXTRACT_UIMM7_A32_11_S
+/* mask = 0000000000011111.  */
+static int
+extract_uimm7_a32_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x001f) << 2;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM7_A32_11_S */
+
+#ifndef INSERT_UIMM7_9_S
+#define INSERT_UIMM7_9_S
+/* mask = 0000000001111111
+   insn = 11100bbb0uuuuuuu.  */
+static unsigned
+insert_uimm7_9_s (unsigned insn ATTRIBUTE_UNUSED,
+                 int value ATTRIBUTE_UNUSED,
+                 const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x007f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM7_9_S */
+
+#ifndef EXTRACT_UIMM7_9_S
+#define EXTRACT_UIMM7_9_S
+/* mask = 0000000001111111.  */
+static int
+extract_uimm7_9_s (unsigned insn ATTRIBUTE_UNUSED,
+                  bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x007f) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM7_9_S */
+
+#ifndef INSERT_UIMM3_13_S
+#define INSERT_UIMM3_13_S
+/* mask = 0000000000000111
+   insn = 01101bbbccc00uuu.  */
+static unsigned
+insert_uimm3_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x0007) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM3_13_S */
+
+#ifndef EXTRACT_UIMM3_13_S
+#define EXTRACT_UIMM3_13_S
+/* mask = 0000000000000111.  */
+static int
+extract_uimm3_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x0007) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM3_13_S */
+
+#ifndef INSERT_SIMM11_A32_7_S
+#define INSERT_SIMM11_A32_7_S
+/* mask = 0000000111111111
+   insn = 1100111sssssssss.  */
+static unsigned
+insert_simm11_a32_7_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x01ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM11_A32_7_S */
+
+#ifndef EXTRACT_SIMM11_A32_7_S
+#define EXTRACT_SIMM11_A32_7_S
+/* mask = 0000000111111111.  */
+static int
+extract_simm11_a32_7_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x01ff) << 2;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (11 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM11_A32_7_S */
+
+#ifndef INSERT_UIMM6_13_S
+#define INSERT_UIMM6_13_S
+/* mask = 0000000002220111
+   insn = 01001bbb0UUU1uuu.  */
+static unsigned
+insert_uimm6_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x0007) << 0;
+  insn |= ((value >> 3) & 0x0007) << 4;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_13_S */
+
+#ifndef EXTRACT_UIMM6_13_S
+#define EXTRACT_UIMM6_13_S
+/* mask = 0000000002220111.  */
+static int
+extract_uimm6_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x0007) << 0;
+  value |= ((insn >> 4) & 0x0007) << 3;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_13_S */
+
+#ifndef INSERT_UIMM5_11_S
+#define INSERT_UIMM5_11_S
+/* mask = 0000000000011111
+   insn = 10111bbb000uuuuu.  */
+static unsigned
+insert_uimm5_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x001f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM5_11_S */
+
+#ifndef EXTRACT_UIMM5_11_S
+#define EXTRACT_UIMM5_11_S
+/* mask = 0000000000011111.  */
+static int
+extract_uimm5_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x001f) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM5_11_S */
+
+#ifndef INSERT_SIMM9_A16_8
+#define INSERT_SIMM9_A16_8
+/* mask = 00000000111111102000000000000000
+   insn = 00001bbbsssssss1SBBBCCCCCCN01110.  */
+static unsigned
+insert_simm9_a16_8 (unsigned insn ATTRIBUTE_UNUSED,
+                   int value ATTRIBUTE_UNUSED,
+                   const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x007f) << 17;
+  insn |= ((value >> 8) & 0x0001) << 15;
+
+  return insn;
+}
+#endif /* INSERT_SIMM9_A16_8 */
+
+#ifndef EXTRACT_SIMM9_A16_8
+#define EXTRACT_SIMM9_A16_8
+/* mask = 00000000111111102000000000000000.  */
+static int
+extract_simm9_a16_8 (unsigned insn ATTRIBUTE_UNUSED,
+                    bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 17) & 0x007f) << 1;
+  value |= ((insn >> 15) & 0x0001) << 8;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (9 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM9_A16_8 */
+
+#ifndef INSERT_UIMM6_8
+#define INSERT_UIMM6_8
+/* mask = 00000000000000000000111111000000
+   insn = 00001bbbsssssss1SBBBuuuuuuN11110.  */
+static unsigned
+insert_uimm6_8 (unsigned insn ATTRIBUTE_UNUSED,
+               int value ATTRIBUTE_UNUSED,
+               const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x003f) << 6;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_8 */
+
+#ifndef EXTRACT_UIMM6_8
+#define EXTRACT_UIMM6_8
+/* mask = 00000000000000000000111111000000.  */
+static int
+extract_uimm6_8 (unsigned insn ATTRIBUTE_UNUSED,
+                bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 6) & 0x003f) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_8 */
+
+#ifndef INSERT_SIMM21_A16_5
+#define INSERT_SIMM21_A16_5
+/* mask = 00000111111111102222222222000000
+   insn = 00000ssssssssss0SSSSSSSSSSNQQQQQ.  */
+static unsigned
+insert_simm21_a16_5 (unsigned insn ATTRIBUTE_UNUSED,
+                    int value ATTRIBUTE_UNUSED,
+                    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x03ff) << 17;
+  insn |= ((value >> 11) & 0x03ff) << 6;
+
+  return insn;
+}
+#endif /* INSERT_SIMM21_A16_5 */
+
+#ifndef EXTRACT_SIMM21_A16_5
+#define EXTRACT_SIMM21_A16_5
+/* mask = 00000111111111102222222222000000.  */
+static int
+extract_simm21_a16_5 (unsigned insn ATTRIBUTE_UNUSED,
+                     bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 17) & 0x03ff) << 1;
+  value |= ((insn >> 6) & 0x03ff) << 11;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (21 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM21_A16_5 */
+
+#ifndef INSERT_SIMM25_A16_5
+#define INSERT_SIMM25_A16_5
+/* mask = 00000111111111102222222222003333
+   insn = 00000ssssssssss1SSSSSSSSSSNRtttt.  */
+static unsigned
+insert_simm25_a16_5 (unsigned insn ATTRIBUTE_UNUSED,
+                    int value ATTRIBUTE_UNUSED,
+                    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x03ff) << 17;
+  insn |= ((value >> 11) & 0x03ff) << 6;
+  insn |= ((value >> 21) & 0x000f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM25_A16_5 */
+
+#ifndef EXTRACT_SIMM25_A16_5
+#define EXTRACT_SIMM25_A16_5
+/* mask = 00000111111111102222222222003333.  */
+static int
+extract_simm25_a16_5 (unsigned insn ATTRIBUTE_UNUSED,
+                     bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 17) & 0x03ff) << 1;
+  value |= ((insn >> 6) & 0x03ff) << 11;
+  value |= ((insn >> 0) & 0x000f) << 21;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (25 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM25_A16_5 */
+
+#ifndef INSERT_SIMM10_A16_7_S
+#define INSERT_SIMM10_A16_7_S
+/* mask = 0000000111111111
+   insn = 1111001sssssssss.  */
+static unsigned
+insert_simm10_a16_7_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x01ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM10_A16_7_S */
+
+#ifndef EXTRACT_SIMM10_A16_7_S
+#define EXTRACT_SIMM10_A16_7_S
+/* mask = 0000000111111111.  */
+static int
+extract_simm10_a16_7_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x01ff) << 1;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (10 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM10_A16_7_S */
+
+#ifndef INSERT_SIMM7_A16_10_S
+#define INSERT_SIMM7_A16_10_S
+/* mask = 0000000000111111
+   insn = 1111011000ssssss.  */
+static unsigned
+insert_simm7_a16_10_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x003f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM7_A16_10_S */
+
+#ifndef EXTRACT_SIMM7_A16_10_S
+#define EXTRACT_SIMM7_A16_10_S
+/* mask = 0000000000111111.  */
+static int
+extract_simm7_a16_10_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x003f) << 1;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (7 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM7_A16_10_S */
+
+#ifndef INSERT_SIMM21_A32_5
+#define INSERT_SIMM21_A32_5
+/* mask = 00000111111111002222222222000000
+   insn = 00001sssssssss00SSSSSSSSSSNQQQQQ.  */
+static unsigned
+insert_simm21_a32_5 (unsigned insn ATTRIBUTE_UNUSED,
+                    int value ATTRIBUTE_UNUSED,
+                    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x01ff) << 18;
+  insn |= ((value >> 11) & 0x03ff) << 6;
+
+  return insn;
+}
+#endif /* INSERT_SIMM21_A32_5 */
+
+#ifndef EXTRACT_SIMM21_A32_5
+#define EXTRACT_SIMM21_A32_5
+/* mask = 00000111111111002222222222000000.  */
+static int
+extract_simm21_a32_5 (unsigned insn ATTRIBUTE_UNUSED,
+                     bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 18) & 0x01ff) << 2;
+  value |= ((insn >> 6) & 0x03ff) << 11;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (21 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM21_A32_5 */
+
+#ifndef INSERT_SIMM25_A32_5
+#define INSERT_SIMM25_A32_5
+/* mask = 00000111111111002222222222003333
+   insn = 00001sssssssss10SSSSSSSSSSNRtttt.  */
+static unsigned
+insert_simm25_a32_5 (unsigned insn ATTRIBUTE_UNUSED,
+                    int value ATTRIBUTE_UNUSED,
+                    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x01ff) << 18;
+  insn |= ((value >> 11) & 0x03ff) << 6;
+  insn |= ((value >> 21) & 0x000f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM25_A32_5 */
+
+#ifndef EXTRACT_SIMM25_A32_5
+#define EXTRACT_SIMM25_A32_5
+/* mask = 00000111111111002222222222003333.  */
+static int
+extract_simm25_a32_5 (unsigned insn ATTRIBUTE_UNUSED,
+                     bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 18) & 0x01ff) << 2;
+  value |= ((insn >> 6) & 0x03ff) << 11;
+  value |= ((insn >> 0) & 0x000f) << 21;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (25 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM25_A32_5 */
+
+#ifndef INSERT_SIMM13_A32_5_S
+#define INSERT_SIMM13_A32_5_S
+/* mask = 0000011111111111
+   insn = 11111sssssssssss.  */
+static unsigned
+insert_simm13_a32_5_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x07ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM13_A32_5_S */
+
+#ifndef EXTRACT_SIMM13_A32_5_S
+#define EXTRACT_SIMM13_A32_5_S
+/* mask = 0000011111111111.  */
+static int
+extract_simm13_a32_5_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x07ff) << 2;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (13 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM13_A32_5_S */
+
+#ifndef INSERT_SIMM8_A16_9_S
+#define INSERT_SIMM8_A16_9_S
+/* mask = 0000000001111111
+   insn = 11101bbb1sssssss.  */
+static unsigned
+insert_simm8_a16_9_s (unsigned insn ATTRIBUTE_UNUSED,
+                     int value ATTRIBUTE_UNUSED,
+                     const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x007f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM8_A16_9_S */
+
+#ifndef EXTRACT_SIMM8_A16_9_S
+#define EXTRACT_SIMM8_A16_9_S
+/* mask = 0000000001111111.  */
+static int
+extract_simm8_a16_9_s (unsigned insn ATTRIBUTE_UNUSED,
+                      bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x007f) << 1;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (8 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM8_A16_9_S */
+
+#ifndef INSERT_UIMM3_23
+#define INSERT_UIMM3_23
+/* mask = 00000000000000000000000111000000
+   insn = 00100011011011110001RRRuuu111111.  */
+static unsigned
+insert_uimm3_23 (unsigned insn ATTRIBUTE_UNUSED,
+                int value ATTRIBUTE_UNUSED,
+                const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x0007) << 6;
+
+  return insn;
+}
+#endif /* INSERT_UIMM3_23 */
+
+#ifndef EXTRACT_UIMM3_23
+#define EXTRACT_UIMM3_23
+/* mask = 00000000000000000000000111000000.  */
+static int
+extract_uimm3_23 (unsigned insn ATTRIBUTE_UNUSED,
+                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 6) & 0x0007) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM3_23 */
+
+#ifndef INSERT_UIMM10_6_S
+#define INSERT_UIMM10_6_S
+/* mask = 0000001111111111
+   insn = 010111uuuuuuuuuu.  */
+static unsigned
+insert_uimm10_6_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x03ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM10_6_S */
+
+#ifndef EXTRACT_UIMM10_6_S
+#define EXTRACT_UIMM10_6_S
+/* mask = 0000001111111111.  */
+static int
+extract_uimm10_6_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x03ff) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM10_6_S */
+
+#ifndef INSERT_UIMM6_11_S
+#define INSERT_UIMM6_11_S
+/* mask = 0000002200011110
+   insn = 110000UU111uuuu0.  */
+static unsigned
+insert_uimm6_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x000f) << 1;
+  insn |= ((value >> 4) & 0x0003) << 8;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_11_S */
+
+#ifndef EXTRACT_UIMM6_11_S
+#define EXTRACT_UIMM6_11_S
+/* mask = 0000002200011110.  */
+static int
+extract_uimm6_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 1) & 0x000f) << 0;
+  value |= ((insn >> 8) & 0x0003) << 4;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_11_S */
+
+#ifndef INSERT_SIMM9_8
+#define INSERT_SIMM9_8
+/* mask = 00000000111111112000000000000000
+   insn = 00010bbbssssssssSBBBDaaZZXAAAAAA.  */
+static unsigned
+insert_simm9_8 (unsigned insn ATTRIBUTE_UNUSED,
+               int value ATTRIBUTE_UNUSED,
+               const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x00ff) << 16;
+  insn |= ((value >> 8) & 0x0001) << 15;
+
+  return insn;
+}
+#endif /* INSERT_SIMM9_8 */
+
+#ifndef EXTRACT_SIMM9_8
+#define EXTRACT_SIMM9_8
+/* mask = 00000000111111112000000000000000.  */
+static int
+extract_simm9_8 (unsigned insn ATTRIBUTE_UNUSED,
+                bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 16) & 0x00ff) << 0;
+  value |= ((insn >> 15) & 0x0001) << 8;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (9 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM9_8 */
+
+#ifndef INSERT_UIMM10_A32_8_S
+#define INSERT_UIMM10_A32_8_S
+/* mask = 0000000011111111
+   insn = 11010bbbuuuuuuuu.  */
+static unsigned
+insert_uimm10_a32_8_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x00ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM10_A32_8_S */
+
+#ifndef EXTRACT_UIMM10_A32_8_S
+#define EXTRACT_UIMM10_A32_8_S
+/* mask = 0000000011111111.  */
+static int
+extract_uimm10_a32_8_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x00ff) << 2;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM10_A32_8_S */
+
+#ifndef INSERT_SIMM9_7_S
+#define INSERT_SIMM9_7_S
+/* mask = 0000000111111111
+   insn = 1100101sssssssss.  */
+static unsigned
+insert_simm9_7_s (unsigned insn ATTRIBUTE_UNUSED,
+                 int value ATTRIBUTE_UNUSED,
+                 const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x01ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM9_7_S */
+
+#ifndef EXTRACT_SIMM9_7_S
+#define EXTRACT_SIMM9_7_S
+/* mask = 0000000111111111.  */
+static int
+extract_simm9_7_s (unsigned insn ATTRIBUTE_UNUSED,
+                  bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x01ff) << 0;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (9 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM9_7_S */
+
+#ifndef INSERT_UIMM6_A16_11_S
+#define INSERT_UIMM6_A16_11_S
+/* mask = 0000000000011111
+   insn = 10010bbbcccuuuuu.  */
+static unsigned
+insert_uimm6_a16_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x001f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_A16_11_S */
+
+#ifndef EXTRACT_UIMM6_A16_11_S
+#define EXTRACT_UIMM6_A16_11_S
+/* mask = 0000000000011111.  */
+static int
+extract_uimm6_a16_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x001f) << 1;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_A16_11_S */
+
+#ifndef INSERT_UIMM5_A32_11_S
+#define INSERT_UIMM5_A32_11_S
+/* mask = 0000020000011000
+   insn = 01000U00hhhuu1HH.  */
+static unsigned
+insert_uimm5_a32_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x0003) << 3;
+  insn |= ((value >> 4) & 0x0001) << 10;
+
+  return insn;
+}
+#endif /* INSERT_UIMM5_A32_11_S */
+
+#ifndef EXTRACT_UIMM5_A32_11_S
+#define EXTRACT_UIMM5_A32_11_S
+/* mask = 0000020000011000.  */
+static int
+extract_uimm5_a32_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 3) & 0x0003) << 2;
+  value |= ((insn >> 10) & 0x0001) << 4;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM5_A32_11_S */
+
+#ifndef INSERT_SIMM11_A32_13_S
+#define INSERT_SIMM11_A32_13_S
+/* mask = 0000022222200111
+   insn = 01010SSSSSS00sss.  */
+static unsigned
+insert_simm11_a32_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                       int value ATTRIBUTE_UNUSED,
+                       const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x03)
+    *errmsg = _("Target address is not 32bit aligned.");
+
+  insn |= ((value >> 2) & 0x0007) << 0;
+  insn |= ((value >> 5) & 0x003f) << 5;
+
+  return insn;
+}
+#endif /* INSERT_SIMM11_A32_13_S */
+
+#ifndef EXTRACT_SIMM11_A32_13_S
+#define EXTRACT_SIMM11_A32_13_S
+/* mask = 0000022222200111.  */
+static int
+extract_simm11_a32_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                        bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 0) & 0x0007) << 2;
+  value |= ((insn >> 5) & 0x003f) << 5;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (11 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM11_A32_13_S */
+
+#ifndef INSERT_UIMM7_13_S
+#define INSERT_UIMM7_13_S
+/* mask = 0000000022220111
+   insn = 01010bbbUUUU1uuu.  */
+static unsigned
+insert_uimm7_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x0007) << 0;
+  insn |= ((value >> 3) & 0x000f) << 4;
+
+  return insn;
+}
+#endif /* INSERT_UIMM7_13_S */
+
+#ifndef EXTRACT_UIMM7_13_S
+#define EXTRACT_UIMM7_13_S
+/* mask = 0000000022220111.  */
+static int
+extract_uimm7_13_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x0007) << 0;
+  value |= ((insn >> 4) & 0x000f) << 3;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM7_13_S */
+
+#ifndef INSERT_UIMM6_A16_21
+#define INSERT_UIMM6_A16_21
+/* mask = 00000000000000000000011111000000
+   insn = 00101bbb01001100RBBBRuuuuuAAAAAA.  */
+static unsigned
+insert_uimm6_a16_21 (unsigned insn ATTRIBUTE_UNUSED,
+                    int value ATTRIBUTE_UNUSED,
+                    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x001f) << 6;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_A16_21 */
+
+#ifndef EXTRACT_UIMM6_A16_21
+#define EXTRACT_UIMM6_A16_21
+/* mask = 00000000000000000000011111000000.  */
+static int
+extract_uimm6_a16_21 (unsigned insn ATTRIBUTE_UNUSED,
+                     bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 6) & 0x001f) << 1;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_A16_21 */
+
+#ifndef INSERT_UIMM7_11_S
+#define INSERT_UIMM7_11_S
+/* mask = 0000022200011110
+   insn = 11000UUU110uuuu0.  */
+static unsigned
+insert_uimm7_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x000f) << 1;
+  insn |= ((value >> 4) & 0x0007) << 8;
+
+  return insn;
+}
+#endif /* INSERT_UIMM7_11_S */
+
+#ifndef EXTRACT_UIMM7_11_S
+#define EXTRACT_UIMM7_11_S
+/* mask = 0000022200011110.  */
+static int
+extract_uimm7_11_s (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 1) & 0x000f) << 0;
+  value |= ((insn >> 8) & 0x0007) << 4;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM7_11_S */
+
+#ifndef INSERT_UIMM7_A16_20
+#define INSERT_UIMM7_A16_20
+/* mask = 00000000000000000000111111000000
+   insn = 00100RRR111010000RRRuuuuuu1QQQQQ.  */
+static unsigned
+insert_uimm7_a16_20 (unsigned insn ATTRIBUTE_UNUSED,
+                    int value ATTRIBUTE_UNUSED,
+                    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x003f) << 6;
+
+  return insn;
+}
+#endif /* INSERT_UIMM7_A16_20 */
+
+#ifndef EXTRACT_UIMM7_A16_20
+#define EXTRACT_UIMM7_A16_20
+/* mask = 00000000000000000000111111000000.  */
+static int
+extract_uimm7_a16_20 (unsigned insn ATTRIBUTE_UNUSED,
+                     bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 6) & 0x003f) << 1;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM7_A16_20 */
+
+#ifndef INSERT_SIMM13_A16_20
+#define INSERT_SIMM13_A16_20
+/* mask = 00000000000000000000111111222222
+   insn = 00100RRR101010000RRRssssssSSSSSS.  */
+static unsigned
+insert_simm13_a16_20 (unsigned insn ATTRIBUTE_UNUSED,
+                     int value ATTRIBUTE_UNUSED,
+                     const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Target address is not 16bit aligned.");
+
+  insn |= ((value >> 1) & 0x003f) << 6;
+  insn |= ((value >> 7) & 0x003f) << 0;
+
+  return insn;
+}
+#endif /* INSERT_SIMM13_A16_20 */
+
+#ifndef EXTRACT_SIMM13_A16_20
+#define EXTRACT_SIMM13_A16_20
+/* mask = 00000000000000000000111111222222.  */
+static int
+extract_simm13_a16_20 (unsigned insn ATTRIBUTE_UNUSED,
+                      bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 6) & 0x003f) << 1;
+  value |= ((insn >> 0) & 0x003f) << 7;
+
+  /* Extend the sign.  */
+  int signbit = 1 << (13 - 1);
+  value = (value ^ signbit) - signbit;
+
+  return value;
+}
+#endif /* EXTRACT_SIMM13_A16_20 */
+
+#ifndef INSERT_UIMM8_8_S
+#define INSERT_UIMM8_8_S
+/* mask = 0000000011111111
+   insn = 11011bbbuuuuuuuu.  */
+static unsigned
+insert_uimm8_8_s (unsigned insn ATTRIBUTE_UNUSED,
+                 int value ATTRIBUTE_UNUSED,
+                 const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x00ff) << 0;
+
+  return insn;
+}
+#endif /* INSERT_UIMM8_8_S */
+
+#ifndef EXTRACT_UIMM8_8_S
+#define EXTRACT_UIMM8_8_S
+/* mask = 0000000011111111.  */
+static int
+extract_uimm8_8_s (unsigned insn ATTRIBUTE_UNUSED,
+                  bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 0) & 0x00ff) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM8_8_S */
+
+#ifndef INSERT_UIMM6_5_S
+#define INSERT_UIMM6_5_S
+/* mask = 0000011111100000
+   insn = 01111uuuuuu11111.  */
+static unsigned
+insert_uimm6_5_s (unsigned insn ATTRIBUTE_UNUSED,
+                 int value ATTRIBUTE_UNUSED,
+                 const char **errmsg ATTRIBUTE_UNUSED)
+{
+
+  insn |= ((value >> 0) & 0x003f) << 5;
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_5_S */
+
+#ifndef EXTRACT_UIMM6_5_S
+#define EXTRACT_UIMM6_5_S
+/* mask = 0000011111100000.  */
+static int
+extract_uimm6_5_s (unsigned insn ATTRIBUTE_UNUSED,
+                  bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  value |= ((insn >> 5) & 0x003f) << 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_5_S */
+
+#ifndef INSERT_UIMM6_AXX_
+#define INSERT_UIMM6_AXX_
+/* mask = 00000000000000000000000000000000
+   insn = 00110bbb11100001100001100001QQQQ.  */
+static ATTRIBUTE_UNUSED unsigned
+insert_uimm6_axx_ (unsigned insn ATTRIBUTE_UNUSED,
+                  int value ATTRIBUTE_UNUSED,
+                  const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x3f)
+    *errmsg = _("Target address is not 512bit aligned.");
+
+  return insn;
+}
+#endif /* INSERT_UIMM6_AXX_ */
+
+#ifndef EXTRACT_UIMM6_AXX_
+#define EXTRACT_UIMM6_AXX_
+/* mask = 00000000000000000000000000000000.  */
+static ATTRIBUTE_UNUSED int
+extract_uimm6_axx_ (unsigned insn ATTRIBUTE_UNUSED,
+                   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  unsigned value = 0;
+
+  return value;
+}
+#endif /* EXTRACT_UIMM6_AXX_ */

diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 309bb0c..db11a1f 100644 (file)
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1,6 +1,7 @@
 /* Opcode table for the ARC.
    Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
    This file is part of libopcodes.
 
@@ -20,1743 +21,1327 @@
 
 #include "sysdep.h"
 #include <stdio.h>
-#include "ansidecl.h"
 #include "bfd.h"
 #include "opcode/arc.h"
 #include "opintl.h"
+#include "libiberty.h"
 
-enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
-
-#define OPERANDS 3
-
-enum operand ls_operand[OPERANDS];
-
-struct arc_opcode *arc_ext_opcodes;
-struct arc_ext_operand_value *arc_ext_operands;
-
-#define LS_VALUE  0
-#define LS_DEST   0
-#define LS_BASE   1
-#define LS_OFFSET 2
-
-/* Given a format letter, yields the index into `arc_operands'.
-   eg: arc_operand_map['a'] = REGA.  */
-unsigned char arc_operand_map[256];
-
-/* Nonzero if we've seen an 'f' suffix (in certain insns).  */
-static int flag_p;
-
-/* Nonzero if we've finished processing the 'f' suffix.  */
-static int flagshimm_handled_p;
-
-/* Nonzero if we've seen a 'a' suffix (address writeback).  */
-static int addrwb_p;
-
-/* Nonzero if we've seen a 'q' suffix (condition code).  */
-static int cond_p;
-
-/* Nonzero if we've inserted a nullify condition.  */
-static int nullify_p;
-
-/* The value of the a nullify condition we inserted.  */
-static int nullify;
-
-/* Nonzero if we've inserted jumpflags.  */
-static int jumpflags_p;
-
-/* Nonzero if we've inserted a shimm.  */
-static int shimm_p;
-
-/* The value of the shimm we inserted (each insn only gets one but it can
-   appear multiple times).  */
-static int shimm;
-
-/* Nonzero if we've inserted a limm (during assembly) or seen a limm
-   (during disassembly).  */
-static int limm_p;
-
-/* The value of the limm we inserted.  Each insn only gets one but it can
-   appear multiple times.  */
-static long limm;
-\f
-#define INSERT_FN(fn) \
-static arc_insn fn (arc_insn, const struct arc_operand *, \
-                   int, const struct arc_operand_value *, long, \
-                   const char **)
-
-#define EXTRACT_FN(fn) \
-static long fn (arc_insn *, const struct arc_operand *, \
-               int, const struct arc_operand_value **, int *)
-
-INSERT_FN (insert_reg);
-INSERT_FN (insert_shimmfinish);
-INSERT_FN (insert_limmfinish);
-INSERT_FN (insert_offset);
-INSERT_FN (insert_base);
-INSERT_FN (insert_st_syntax);
-INSERT_FN (insert_ld_syntax);
-INSERT_FN (insert_addr_wb);
-INSERT_FN (insert_flag);
-INSERT_FN (insert_nullify);
-INSERT_FN (insert_flagfinish);
-INSERT_FN (insert_cond);
-INSERT_FN (insert_forcelimm);
-INSERT_FN (insert_reladdr);
-INSERT_FN (insert_absaddr);
-INSERT_FN (insert_jumpflags);
-INSERT_FN (insert_unopmacro);
-
-EXTRACT_FN (extract_reg);
-EXTRACT_FN (extract_ld_offset);
-EXTRACT_FN (extract_ld_syntax);
-EXTRACT_FN (extract_st_offset);
-EXTRACT_FN (extract_st_syntax);
-EXTRACT_FN (extract_flag);
-EXTRACT_FN (extract_cond);
-EXTRACT_FN (extract_reladdr);
-EXTRACT_FN (extract_jumpflags);
-EXTRACT_FN (extract_unopmacro);
-
-/* Various types of ARC operands, including insn suffixes.  */
-
-/* Insn format values:
-
-   'a' REGA            register A field
-   'b' REGB            register B field
-   'c' REGC            register C field
-   'S' SHIMMFINISH     finish inserting a shimm value
-   'L' LIMMFINISH      finish inserting a limm value
-   'o' OFFSET          offset in st insns
-   'O' OFFSET          offset in ld insns
-   '0' SYNTAX_ST_NE    enforce store insn syntax, no errors
-   '1' SYNTAX_LD_NE    enforce load insn syntax, no errors
-   '2'  SYNTAX_ST       enforce store insn syntax, errors, last pattern only
-   '3'  SYNTAX_LD       enforce load insn syntax, errors, last pattern only
-   's'  BASE            base in st insn
-   'f' FLAG            F flag
-   'F' FLAGFINISH      finish inserting the F flag
-   'G' FLAGINSN        insert F flag in "flag" insn
-   'n' DELAY           N field (nullify field)
-   'q' COND            condition code field
-   'Q' FORCELIMM       set `cond_p' to 1 to ensure a constant is a limm
-   'B' BRANCH          branch address (22 bit pc relative)
-   'J' JUMP            jump address (26 bit absolute)
-   'j'  JUMPFLAGS       optional high order bits of 'J'
-   'z' SIZE1           size field in ld a,[b,c]
-   'Z' SIZE10          size field in ld a,[b,shimm]
-   'y' SIZE22          size field in st c,[b,shimm]
-   'x' SIGN0           sign extend field ld a,[b,c]
-   'X' SIGN9           sign extend field ld a,[b,shimm]
-   'w' ADDRESS3        write-back field in ld a,[b,c]
-   'W' ADDRESS12       write-back field in ld a,[b,shimm]
-   'v' ADDRESS24       write-back field in st c,[b,shimm]
-   'e' CACHEBYPASS5    cache bypass in ld a,[b,c]
-   'E' CACHEBYPASS14   cache bypass in ld a,[b,shimm]
-   'D' CACHEBYPASS26   cache bypass in st c,[b,shimm]
-   'U' UNOPMACRO       fake operand to copy REGB to REGC for unop macros
-
-   The following modifiers may appear between the % and char (eg: %.f):
-
-   '.' MODDOT          '.' prefix must be present
-   'r' REG             generic register value, for register table
-   'A' AUXREG          auxiliary register in lr a,[b], sr c,[b]
-
-   Fields are:
-
-   CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN  */
-
-const struct arc_operand arc_operands[] =
+/* Insert RB register into a 32-bit opcode.  */
+static unsigned
+insert_rb (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-/* Place holder (??? not sure if needed).  */
-#define UNUSED 0
-  { 0, 0, 0, 0, 0, 0 },
-
-/* Register A or shimm/limm indicator.  */
-#define REGA (UNUSED + 1)
-  { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-
-/* Register B or shimm/limm indicator.  */
-#define REGB (REGA + 1)
-  { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-
-/* Register C or shimm/limm indicator.  */
-#define REGC (REGB + 1)
-  { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-
-/* Fake operand used to insert shimm value into most instructions.  */
-#define SHIMMFINISH (REGC + 1)
-  { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
-
-/* Fake operand used to insert limm value into most instructions.  */
-#define LIMMFINISH (SHIMMFINISH + 1)
-  { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
-
-/* Shimm operand when there is no reg indicator (st).  */
-#define ST_OFFSET (LIMMFINISH + 1)
-  { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
+  return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
 
-/* Shimm operand when there is no reg indicator (ld).  */
-#define LD_OFFSET (ST_OFFSET + 1)
-  { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
+static int
+extract_rb (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
 
-/* Operand for base.  */
-#define BASE (LD_OFFSET + 1)
-  { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
+  if (value == 0x3e && invalid)
+    *invalid = TRUE; /* A limm operand, it should be extracted in a
+                       different way.  */
 
-/* 0 enforce syntax for st insns.  */
-#define SYNTAX_ST_NE (BASE + 1)
-  { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
+  return value;
+}
 
-/* 1 enforce syntax for ld insns.  */
-#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
-  { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
+static unsigned
+insert_rad (unsigned insn,
+           int value,
+           const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Improper register value.");
 
-/* 0 enforce syntax for st insns.  */
-#define SYNTAX_ST (SYNTAX_LD_NE + 1)
-  { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
+  return insn | (value & 0x3F);
+}
 
-/* 0 enforce syntax for ld insns.  */
-#define SYNTAX_LD (SYNTAX_ST + 1)
-  { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
+static unsigned
+insert_rcd (unsigned insn,
+           int value,
+           const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value & 0x01)
+    *errmsg = _("Improper register value.");
 
-/* Flag update bit (insertion is defered until we know how).  */
-#define FLAG (SYNTAX_LD + 1)
-  { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
+  return insn | ((value & 0x3F) << 6);
+}
 
-/* Fake utility operand to finish 'f' suffix handling.  */
-#define FLAGFINISH (FLAG + 1)
-  { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
+/* Dummy insert ZERO operand function.  */
 
-/* Fake utility operand to set the 'f' flag for the "flag" insn.  */
-#define FLAGINSN (FLAGFINISH + 1)
-  { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
+static unsigned
+insert_za (unsigned insn,
+          int value,
+          const char **errmsg)
+{
+  if (value)
+    *errmsg = _("operand is not zero");
+  return insn;
+}
 
-/* Branch delay types.  */
-#define DELAY (FLAGINSN + 1)
-  { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
+/* Insert Y-bit in bbit/br instructions.  This function is called only
+   when solving fixups.  */
 
-/* Conditions.  */
-#define COND (DELAY + 1)
-  { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
+static unsigned
+insert_Ybit (unsigned insn,
+            int value,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value > 0)
+    insn |= 0x08;
 
-/* Set `cond_p' to 1 to ensure a constant is treated as a limm.  */
-#define FORCELIMM (COND + 1)
-  { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
+  return insn;
+}
 
-/* Branch address; b, bl, and lp insns.  */
-#define BRANCH (FORCELIMM + 1)
-  { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
+/* Insert Y-bit in bbit/br instructions.  This function is called only
+   when solving fixups.  */
 
-/* Jump address; j insn (this is basically the same as 'L' except that the
-   value is right shifted by 2).  */
-#define JUMP (BRANCH + 1)
-  { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
+static unsigned
+insert_NYbit (unsigned insn,
+             int value,
+             const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value < 0)
+    insn |= 0x08;
 
-/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values.  */
-#define JUMPFLAGS (JUMP + 1)
-  { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
+  return insn;
+}
 
-/* Size field, stored in bit 1,2.  */
-#define SIZE1 (JUMPFLAGS + 1)
-  { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
+/* Insert H register into a 16-bit opcode.  */
 
-/* Size field, stored in bit 10,11.  */
-#define SIZE10 (SIZE1 + 1)
-  { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
+static unsigned
+insert_rhv1 (unsigned insn,
+            int value,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
+}
 
-/* Size field, stored in bit 22,23.  */
-#define SIZE22 (SIZE10 + 1)
-  { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
+static int
+extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
+             bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
 
-/* Sign extend field, stored in bit 0.  */
-#define SIGN0 (SIZE22 + 1)
-  { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Sign extend field, stored in bit 9.  */
-#define SIGN9 (SIGN0 + 1)
-  { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Address write back, stored in bit 3.  */
-#define ADDRESS3 (SIGN9 + 1)
-  { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-
-/* Address write back, stored in bit 12.  */
-#define ADDRESS12 (ADDRESS3 + 1)
-  { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-
-/* Address write back, stored in bit 24.  */
-#define ADDRESS24 (ADDRESS12 + 1)
-  { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-
-/* Cache bypass, stored in bit 5.  */
-#define CACHEBYPASS5 (ADDRESS24 + 1)
-  { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Cache bypass, stored in bit 14.  */
-#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
-  { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Cache bypass, stored in bit 26.  */
-#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
-  { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Unop macro, used to copy REGB to REGC.  */
-#define UNOPMACRO (CACHEBYPASS26 + 1)
-  { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
-
-/* '.' modifier ('.' required).  */
-#define MODDOT (UNOPMACRO + 1)
-  { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
-
-/* Dummy 'r' modifier for the register table.
-   It's called a "dummy" because there's no point in inserting an 'r' into all
-   the %a/%b/%c occurrences in the insn table.  */
-#define REG (MODDOT + 1)
-  { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
+  return value;
+}
 
-/* Known auxiliary register modifier (stored in shimm field).  */
-#define AUXREG (REG + 1)
-  { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
+/* Insert H register into a 16-bit opcode.  */
 
-/* End of list place holder.  */
-  { 0, 0, 0, 0, 0, 0 }
-};
-\f
-/* Insert a value into a register field.
-   If REG is NULL, then this is actually a constant.
-
-   We must also handle auxiliary registers for lr/sr insns.  */
-
-static arc_insn
-insert_reg (arc_insn insn,
-           const struct arc_operand *operand,
-           int mods,
-           const struct arc_operand_value *reg,
-           long value,
-           const char **errmsg)
+static unsigned
+insert_rhv2 (unsigned insn,
+            int value,
+            const char **errmsg)
 {
-  static char buf[100];
-  enum operand op_type = OP_NONE;
+  if (value == 0x1E)
+    *errmsg =
+      _("Register R30 is a limm indicator for this type of instruction.");
+  return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
+}
 
-  if (reg == NULL)
-    {
-      /* We have a constant that also requires a value stored in a register
-        field.  Handle these by updating the register field and saving the
-        value for later handling by either %S (shimm) or %L (limm).  */
-
-      /* Try to use a shimm value before a limm one.  */
-      if (ARC_SHIMM_CONST_P (value)
-         /* If we've seen a conditional suffix we have to use a limm.  */
-         && !cond_p
-         /* If we already have a shimm value that is different than ours
-            we have to use a limm.  */
-         && (!shimm_p || shimm == value))
-       {
-         int marker;
-
-         op_type = OP_SHIMM;
-         /* Forget about shimm as dest mlm.  */
-
-         if ('a' != operand->fmt)
-           {
-             shimm_p = 1;
-             shimm = value;
-             flagshimm_handled_p = 1;
-             marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
-           }
-         else
-           {
-             /* Don't request flag setting on shimm as dest.  */
-             marker = ARC_REG_SHIMM;
-           }
-         insn |= marker << operand->shift;
-         /* insn |= value & 511; - done later.  */
-       }
-      /* We have to use a limm.  If we've already seen one they must match.  */
-      else if (!limm_p || limm == value)
-       {
-         op_type = OP_LIMM;
-         limm_p = 1;
-         limm = value;
-         insn |= ARC_REG_LIMM << operand->shift;
-         /* The constant is stored later.  */
-       }
-      else
-       *errmsg = _("unable to fit different valued constants into instruction");
-    }
-  else
-    {
-      /* We have to handle both normal and auxiliary registers.  */
-
-      if (reg->type == AUXREG)
-       {
-         if (!(mods & ARC_MOD_AUXREG))
-           *errmsg = _("auxiliary register not allowed here");
-         else
-           {
-             if ((insn & I(-1)) == I(2)) /* Check for use validity.  */
-               {
-                 if (reg->flags & ARC_REGISTER_READONLY)
-                   *errmsg = _("attempt to set readonly register");
-               }
-             else
-               {
-                 if (reg->flags & ARC_REGISTER_WRITEONLY)
-                   *errmsg = _("attempt to read writeonly register");
-               }
-             insn |= ARC_REG_SHIMM << operand->shift;
-             insn |= reg->value << arc_operands[reg->type].shift;
-           }
-       }
-      else
-       {
-         /* check for use validity.  */
-         if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
-           {
-             if (reg->flags & ARC_REGISTER_READONLY)
-               *errmsg = _("attempt to set readonly register");
-           }
-         if ('a' != operand->fmt)
-           {
-             if (reg->flags & ARC_REGISTER_WRITEONLY)
-               *errmsg = _("attempt to read writeonly register");
-           }
-         /* We should never get an invalid register number here.  */
-         if ((unsigned int) reg->value > 60)
-           {
-             sprintf (buf, _("invalid register number `%d'"), reg->value);
-             *errmsg = buf;
-           }
-         insn |= reg->value << operand->shift;
-         op_type = OP_REG;
-       }
-    }
+static int
+extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
+             bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
 
-  switch (operand->fmt)
-    {
-    case 'a':
-      ls_operand[LS_DEST] = op_type;
-      break;
-    case 's':
-      ls_operand[LS_BASE] = op_type;
-      break;
-    case 'c':
-      if ((insn & I(-1)) == I(2))
-       ls_operand[LS_VALUE] = op_type;
-      else
-       ls_operand[LS_OFFSET] = op_type;
-      break;
-    case 'o': case 'O':
-      ls_operand[LS_OFFSET] = op_type;
-      break;
-    }
+  return value;
+}
 
+static unsigned
+insert_r0 (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value != 0)
+    *errmsg = _("Register must be R0.");
   return insn;
 }
 
-/* Called when we see an 'f' flag.  */
-
-static arc_insn
-insert_flag (arc_insn insn,
-            const struct arc_operand *operand ATTRIBUTE_UNUSED,
-            int mods ATTRIBUTE_UNUSED,
-            const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-            long value ATTRIBUTE_UNUSED,
-            const char **errmsg ATTRIBUTE_UNUSED)
+static int
+extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  /* We can't store anything in the insn until we've parsed the registers.
-     Just record the fact that we've got this flag.  `insert_reg' will use it
-     to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100).  */
-  flag_p = 1;
-  return insn;
+  return 0;
 }
 
-/* Called when we see an nullify condition.  */
 
-static arc_insn
-insert_nullify (arc_insn insn,
-               const struct arc_operand *operand,
-               int mods ATTRIBUTE_UNUSED,
-               const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-               long value,
-               const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned
+insert_r1 (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-  nullify_p = 1;
-  insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
-  nullify = value;
+  if (value != 1)
+    *errmsg = _("Register must be R1.");
   return insn;
 }
 
-/* Called after completely building an insn to ensure the 'f' flag gets set
-   properly.  This is needed because we don't know how to set this flag until
-   we've parsed the registers.  */
-
-static arc_insn
-insert_flagfinish (arc_insn insn,
-                  const struct arc_operand *operand,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                  long value ATTRIBUTE_UNUSED,
-                  const char **errmsg ATTRIBUTE_UNUSED)
+static int
+extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  if (flag_p && !flagshimm_handled_p)
-    {
-      if (shimm_p)
-       abort ();
-      flagshimm_handled_p = 1;
-      insn |= (1 << operand->shift);
-    }
-  return insn;
+  return 1;
 }
 
-/* Called when we see a conditional flag (eg: .eq).  */
-
-static arc_insn
-insert_cond (arc_insn insn,
-            const struct arc_operand *operand,
-            int mods ATTRIBUTE_UNUSED,
-            const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-            long value,
-            const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned
+insert_r2 (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-  cond_p = 1;
-  insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+  if (value != 2)
+    *errmsg = _("Register must be R2.");
   return insn;
 }
 
-/* Used in the "j" instruction to prevent constants from being interpreted as
-   shimm values (which the jump insn doesn't accept).  This can also be used
-   to force the use of limm values in other situations (eg: ld r0,[foo] uses
-   this).
-   ??? The mechanism is sound.  Access to it is a bit klunky right now.  */
-
-static arc_insn
-insert_forcelimm (arc_insn insn,
-                 const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                 int mods ATTRIBUTE_UNUSED,
-                 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                 long value ATTRIBUTE_UNUSED,
-                 const char **errmsg ATTRIBUTE_UNUSED)
+static int
+extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  cond_p = 1;
-  return insn;
+  return 2;
 }
 
-static arc_insn
-insert_addr_wb (arc_insn insn,
-               const struct arc_operand *operand,
-               int mods ATTRIBUTE_UNUSED,
-               const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-               long value ATTRIBUTE_UNUSED,
-               const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned
+insert_r3 (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-  addrwb_p = 1 << operand->shift;
+  if (value != 3)
+    *errmsg = _("Register must be R3.");
   return insn;
 }
 
-static arc_insn
-insert_base (arc_insn insn,
-            const struct arc_operand *operand,
-            int mods,
-            const struct arc_operand_value *reg,
-            long value,
-            const char **errmsg)
+static int
+extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  if (reg != NULL)
-    {
-      arc_insn myinsn;
-      myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
-      insn |= B(myinsn);
-      ls_operand[LS_BASE] = OP_REG;
-    }
-  else if (ARC_SHIMM_CONST_P (value) && !cond_p)
-    {
-      if (shimm_p && value != shimm)
-       {
-         /* Convert the previous shimm operand to a limm.  */
-         limm_p = 1;
-         limm = shimm;
-         insn &= ~C(-1); /* We know where the value is in insn.  */
-         insn |= C(ARC_REG_LIMM);
-         ls_operand[LS_VALUE] = OP_LIMM;
-       }
-      insn |= ARC_REG_SHIMM << operand->shift;
-      shimm_p = 1;
-      shimm = value;
-      ls_operand[LS_BASE] = OP_SHIMM;
-      ls_operand[LS_OFFSET] = OP_SHIMM;
-    }
-  else
-    {
-      if (limm_p && value != limm)
-       {
-         *errmsg = _("too many long constants");
-         return insn;
-       }
-      limm_p = 1;
-      limm = value;
-      insn |= B(ARC_REG_LIMM);
-      ls_operand[LS_BASE] = OP_LIMM;
-    }
-
-  return insn;
+  return 3;
 }
 
-/* Used in ld/st insns to handle the offset field. We don't try to
-   match operand syntax here. we catch bad combinations later.  */
-
-static arc_insn
-insert_offset (arc_insn insn,
-              const struct arc_operand *operand,
-              int mods,
-              const struct arc_operand_value *reg,
-              long value,
-              const char **errmsg)
+static unsigned
+insert_sp (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-  long minval, maxval;
-
-  if (reg != NULL)
-    {
-      arc_insn myinsn;
-      myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
-      ls_operand[LS_OFFSET] = OP_REG;
-      if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later.  */
-       if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later.  */
-         insn |= C (myinsn);
-    }
-  else
-    {
-      /* This is *way* more general than necessary, but maybe some day it'll
-        be useful.  */
-      if (operand->flags & ARC_OPERAND_SIGNED)
-       {
-         minval = -(1 << (operand->bits - 1));
-         maxval = (1 << (operand->bits - 1)) - 1;
-       }
-      else
-       {
-         minval = 0;
-         maxval = (1 << operand->bits) - 1;
-       }
-      if ((cond_p && !limm_p) || (value < minval || value > maxval))
-       {
-         if (limm_p && value != limm)
-           *errmsg = _("too many long constants");
-
-         else
-           {
-             limm_p = 1;
-             limm = value;
-             if (operand->flags & ARC_OPERAND_STORE)
-               insn |= B(ARC_REG_LIMM);
-             if (operand->flags & ARC_OPERAND_LOAD)
-               insn |= C(ARC_REG_LIMM);
-             ls_operand[LS_OFFSET] = OP_LIMM;
-           }
-       }
-      else
-       {
-         if ((value < minval || value > maxval))
-           *errmsg = "need too many limms";
-         else if (shimm_p && value != shimm)
-           {
-             /* Check for bad operand combinations
-                before we lose info about them.  */
-             if ((insn & I(-1)) == I(1))
-               {
-                 *errmsg = _("too many shimms in load");
-                 goto out;
-               }
-             if (limm_p && operand->flags & ARC_OPERAND_LOAD)
-               {
-                 *errmsg = _("too many long constants");
-                 goto out;
-               }
-             /* Convert what we thought was a shimm to a limm.  */
-             limm_p = 1;
-             limm = shimm;
-             if (ls_operand[LS_VALUE] == OP_SHIMM
-                 && operand->flags & ARC_OPERAND_STORE)
-               {
-                 insn &= ~C(-1);
-                 insn |= C(ARC_REG_LIMM);
-                 ls_operand[LS_VALUE] = OP_LIMM;
-               }
-             if (ls_operand[LS_BASE] == OP_SHIMM
-                 && operand->flags & ARC_OPERAND_STORE)
-               {
-                 insn &= ~B(-1);
-                 insn |= B(ARC_REG_LIMM);
-                 ls_operand[LS_BASE] = OP_LIMM;
-               }
-           }
-         shimm = value;
-         shimm_p = 1;
-         ls_operand[LS_OFFSET] = OP_SHIMM;
-       }
-    }
- out:
+  if (value != 28)
+    *errmsg = _("Register must be SP.");
   return insn;
 }
 
-/* Used in st insns to do final disasemble syntax check.  */
-
-static long
-extract_st_syntax (arc_insn *insn,
-                  const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
-                  int *invalid)
+static int
+extract_sp (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-#define ST_SYNTAX(V,B,O) \
-((ls_operand[LS_VALUE]  == (V) && \
-  ls_operand[LS_BASE]   == (B) && \
-  ls_operand[LS_OFFSET] == (O)))
-
-  if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
-       || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
-       || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
-       || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
-       || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
-       || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
-       || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
-       || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
-       || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
-       || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
-       || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
-       || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
-       || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
-       || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
-    *invalid = 1;
-  return 0;
+  return 28;
 }
 
-int
-arc_limm_fixup_adjust (arc_insn insn)
+static unsigned
+insert_gp (unsigned insn,
+          int value,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-  int retval = 0;
-
-  /* Check for st shimm,[limm].  */
-  if ((insn & (I(-1) | C(-1) | B(-1))) ==
-      (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
-    {
-      retval = insn & 0x1ff;
-      if (retval & 0x100) /* Sign extend 9 bit offset.  */
-       retval |= ~0x1ff;
-    }
-  return -retval; /* Negate offset for return.  */
+  if (value != 26)
+    *errmsg = _("Register must be GP.");
+  return insn;
 }
 
-/* Used in st insns to do final syntax check.  */
-
-static arc_insn
-insert_st_syntax (arc_insn insn,
-                 const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                 int mods ATTRIBUTE_UNUSED,
-                 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                 long value ATTRIBUTE_UNUSED,
-                 const char **errmsg)
+static int
+extract_gp (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
-    {
-      /* Change an illegal insn into a legal one, it's easier to
-        do it here than to try to handle it during operand scan.  */
-      limm_p = 1;
-      limm = shimm;
-      shimm_p = 0;
-      shimm = 0;
-      insn = insn & ~(C(-1) | 511);
-      insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
-      ls_operand[LS_VALUE] = OP_LIMM;
-    }
-
-  if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE)
-      || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE))
-    {
-      /* Try to salvage this syntax.  */
-      if (shimm & 0x1) /* Odd shimms won't work.  */
-       {
-         if (limm_p) /* Do we have a limm already?  */
-           *errmsg = _("impossible store");
-
-         limm_p = 1;
-         limm = shimm;
-         shimm = 0;
-         shimm_p = 0;
-         insn = insn & ~(B(-1) | 511);
-         insn |= B(ARC_REG_LIMM);
-         ls_operand[LS_BASE] = OP_LIMM;
-       }
-      else
-       {
-         shimm >>= 1;
-         insn = insn & ~511;
-         insn |= shimm;
-         ls_operand[LS_OFFSET] = OP_SHIMM;
-       }
-    }
-  if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
-    limm += arc_limm_fixup_adjust(insn);
-
-  if (!   (ST_SYNTAX (OP_REG,OP_REG,OP_NONE)
-       || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE)
-       || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM)
-       || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM)
-       || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
-       || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE)
-       || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE)
-       || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM)
-       || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM)
-       || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM)
-       || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE)
-       || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM)))
-    *errmsg = _("st operand error");
-  if (addrwb_p)
-    {
-      if (ls_operand[LS_BASE] != OP_REG)
-       *errmsg = _("address writeback not allowed");
-      insn |= addrwb_p;
-    }
-  if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
-    *errmsg = _("store value must be zero");
-  return insn;
+  return 26;
 }
 
-/* Used in ld insns to do final syntax check.  */
-
-static arc_insn
-insert_ld_syntax (arc_insn insn,
-                 const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                 int mods ATTRIBUTE_UNUSED,
-                 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                 long value ATTRIBUTE_UNUSED,
-                 const char **errmsg)
+static unsigned
+insert_pcl (unsigned insn,
+           int value,
+           const char **errmsg ATTRIBUTE_UNUSED)
 {
-#define LD_SYNTAX(D, B, O) \
-  (   (ls_operand[LS_DEST]   == (D) \
-    && ls_operand[LS_BASE]   == (B) \
-    && ls_operand[LS_OFFSET] == (O)))
-
-  int test = insn & I (-1);
-
-  if (!(test == I (1)))
-    {
-      if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
-          || ls_operand[LS_OFFSET] == OP_SHIMM))
-       *errmsg = _("invalid load/shimm insn");
-    }
-  if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
-       || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
-       || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
-       || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
-       || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
-       || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
-       || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
-    *errmsg = _("ld operand error");
-  if (addrwb_p)
-    {
-      if (ls_operand[LS_BASE] != OP_REG)
-       *errmsg = _("address writeback not allowed");
-      insn |= addrwb_p;
-    }
+  if (value != 63)
+    *errmsg = _("Register must be PCL.");
   return insn;
 }
 
-/* Used in ld insns to do final syntax check.  */
-
-static long
-extract_ld_syntax (arc_insn *insn,
-                  const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
-                  int *invalid)
+static int
+extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
+            bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  int test = insn[0] & I(-1);
-
-  if (!(test == I(1)))
-    {
-      if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
-          || ls_operand[LS_OFFSET] == OP_SHIMM))
-       *invalid = 1;
-    }
-  if (!(   (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1)))
-       ||  LD_SYNTAX (OP_REG, OP_REG, OP_REG)
-       ||  LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM)
-       || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1)))
-       || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1)))
-       || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0))
-       ||  LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM)
-       || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1)))))
-    *invalid = 1;
-  return 0;
+  return 63;
 }
 
-/* Called at the end of processing normal insns (eg: add) to insert a shimm
-   value (if present) into the insn.  */
-
-static arc_insn
-insert_shimmfinish (arc_insn insn,
-                   const struct arc_operand *operand,
-                   int mods ATTRIBUTE_UNUSED,
-                   const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                   long value ATTRIBUTE_UNUSED,
-                   const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned
+insert_blink (unsigned insn,
+             int value,
+             const char **errmsg ATTRIBUTE_UNUSED)
 {
-  if (shimm_p)
-    insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
+  if (value != 31)
+    *errmsg = _("Register must be BLINK.");
   return insn;
 }
 
-/* Called at the end of processing normal insns (eg: add) to insert a limm
-   value (if present) into the insn.
-
-   Note that this function is only intended to handle instructions (with 4 byte
-   immediate operands).  It is not intended to handle data.  */
-
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
-   caller must do that.  The extract fns take a pointer to two words.  The
-   insert fns could be converted and then we could do something useful, but
-   then the reloc handlers would have to know to work on the second word of
-   a 2 word quantity.  That's too much so we don't handle them.  */
-
-static arc_insn
-insert_limmfinish (arc_insn insn,
-                  const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                  long value ATTRIBUTE_UNUSED,
-                  const char **errmsg ATTRIBUTE_UNUSED)
+static int
+extract_blink (unsigned insn ATTRIBUTE_UNUSED,
+              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  return insn;
+  return 31;
 }
 
-static arc_insn
-insert_jumpflags (arc_insn insn,
-                 const struct arc_operand *operand,
-                 int mods ATTRIBUTE_UNUSED,
-                 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                 long value,
-                 const char **errmsg)
+static unsigned
+insert_ilink1 (unsigned insn,
+              int value,
+              const char **errmsg ATTRIBUTE_UNUSED)
 {
-  if (!flag_p)
-    *errmsg = _("jump flags, but no .f seen");
-
-  else if (!limm_p)
-    *errmsg = _("jump flags, but no limm addr");
-
-  else if (limm & 0xfc000000)
-    *errmsg = _("flag bits of jump address limm lost");
-
-  else if (limm & 0x03000000)
-    *errmsg = _("attempt to set HR bits");
-
-  else if ((value & ((1 << operand->bits) - 1)) != value)
-    *errmsg = _("bad jump flags value");
-
-  jumpflags_p = 1;
-  limm = ((limm & ((1 << operand->shift) - 1))
-         | ((value & ((1 << operand->bits) - 1)) << operand->shift));
+  if (value != 29)
+    *errmsg = _("Register must be ILINK1.");
   return insn;
 }
 
-/* Called at the end of unary operand macros to copy the B field to C.  */
-
-static arc_insn
-insert_unopmacro (arc_insn insn,
-                 const struct arc_operand *operand,
-                 int mods ATTRIBUTE_UNUSED,
-                 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-                 long value ATTRIBUTE_UNUSED,
-                 const char **errmsg ATTRIBUTE_UNUSED)
+static int
+extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
+               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
-  return insn;
+  return 29;
 }
 
-/* Insert a relative address for a branch insn (b, bl, or lp).  */
-
-static arc_insn
-insert_reladdr (arc_insn insn,
-               const struct arc_operand *operand,
-               int mods ATTRIBUTE_UNUSED,
-               const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-               long value,
-               const char **errmsg)
+static unsigned
+insert_ilink2 (unsigned insn,
+              int value,
+              const char **errmsg ATTRIBUTE_UNUSED)
 {
-  if (value & 3)
-    *errmsg = _("branch address not on 4 byte boundary");
-  insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
+  if (value != 30)
+    *errmsg = _("Register must be ILINK2.");
   return insn;
 }
 
-/* Insert a limm value as a 26 bit address right shifted 2 into the insn.
-
-   Note that this function is only intended to handle instructions (with 4 byte
-   immediate operands).  It is not intended to handle data.  */
-
-/* ??? Actually, there's little for us to do as we can't call frag_more, the
-   caller must do that.  The extract fns take a pointer to two words.  The
-   insert fns could be converted and then we could do something useful, but
-   then the reloc handlers would have to know to work on the second word of
-   a 2 word quantity.  That's too much so we don't handle them.
-
-   We do check for correct usage of the nullify suffix, or we
-   set the default correctly, though.  */
+static int
+extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
+               bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  return 30;
+}
 
-static arc_insn
-insert_absaddr (arc_insn insn,
-               const struct arc_operand *operand ATTRIBUTE_UNUSED,
-               int mods ATTRIBUTE_UNUSED,
-               const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
-               long value ATTRIBUTE_UNUSED,
-               const char **errmsg)
+static unsigned
+insert_ras (unsigned insn,
+           int value,
+           const char **errmsg ATTRIBUTE_UNUSED)
 {
-  if (limm_p)
+  switch (value)
     {
-      /* If it is a jump and link, .jd must be specified.  */
-      if (insn & R (-1, 9, 1))
-       {
-         if (!nullify_p)
-           insn |=  0x02 << 5;  /* Default nullify to .jd.  */
-
-         else if (nullify != 0x02)
-           *errmsg = _("must specify .jd or no nullify suffix");
-       }
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+      insn |= value;
+      break;
+    case 12:
+    case 13:
+    case 14:
+    case 15:
+      insn |= (value - 8);
+      break;
+    default:
+      *errmsg = _("Register must be either r0-r3 or r12-r15.");
+      break;
     }
   return insn;
 }
-\f
-/* Extraction functions.
 
-   The suffix extraction functions' return value is redundant since it can be
-   obtained from (*OPVAL)->value.  However, the boolean suffixes don't have
-   a suffix table entry for the "false" case, so values of zero must be
-   obtained from the return value (*OPVAL == NULL).  */
-
-/* Called by the disassembler before printing an instruction.  */
-
-void
-arc_opcode_init_extract (void)
+static int
+extract_ras (unsigned insn ATTRIBUTE_UNUSED,
+            bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  arc_opcode_init_insert ();
+  int value = insn & 0x07;
+  if (value > 3)
+    return (value + 8);
+  else
+    return value;
 }
 
-static const struct arc_operand_value *
-lookup_register (int type, long regno)
+static unsigned
+insert_rbs (unsigned insn,
+           int value,
+           const char **errmsg ATTRIBUTE_UNUSED)
 {
-  const struct arc_operand_value *r,*end;
-  struct arc_ext_operand_value *ext_oper = arc_ext_operands;
-
-  while (ext_oper)
+  switch (value)
     {
-      if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
-       return (&ext_oper->operand);
-      ext_oper = ext_oper->next;
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+      insn |= value << 8;
+      break;
+    case 12:
+    case 13:
+    case 14:
+    case 15:
+      insn |= ((value - 8)) << 8;
+      break;
+    default:
+      *errmsg = _("Register must be either r0-r3 or r12-r15.");
+      break;
     }
-
-  if (type == REG)
-    return &arc_reg_names[regno];
-
-  /* ??? This is a little slow and can be speeded up.  */
-  for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
-       r < end; ++r)
-    if (type == r->type        && regno == r->value)
-      return r;
-  return 0;
+  return insn;
 }
 
-/* As we're extracting registers, keep an eye out for the 'f' indicator
-   (ARC_REG_SHIMM_UPDATE).  If we find a register (not a constant marker,
-   like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
-
-   We must also handle auxiliary registers for lr/sr insns.  They are just
-   constants with special names.  */
-
-static long
-extract_reg (arc_insn *insn,
-            const struct arc_operand *operand,
-            int mods,
-            const struct arc_operand_value **opval,
-            int *invalid ATTRIBUTE_UNUSED)
+static int
+extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
+            bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  int regno;
-  long value;
-  enum operand op_type;
-
-  /* Get the register number.  */
-  regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
+  int value = (insn >> 8) & 0x07;
+  if (value > 3)
+    return (value + 8);
+  else
+    return value;
+}
 
-  /* Is it a constant marker?  */
-  if (regno == ARC_REG_SHIMM)
-    {
-      op_type = OP_SHIMM;
-      /* Always return zero if dest is a shimm  mlm.  */
-
-      if ('a' != operand->fmt)
-       {
-         value = *insn & 511;
-         if ((operand->flags & ARC_OPERAND_SIGNED)
-             && (value & 256))
-           value -= 512;
-         if (!flagshimm_handled_p)
-           flag_p = 0;
-         flagshimm_handled_p = 1;
-       }
-      else
-       value = 0;
-    }
-  else if (regno == ARC_REG_SHIMM_UPDATE)
-    {
-      op_type = OP_SHIMM;
-
-      /* Always return zero if dest is a shimm  mlm.  */
-      if ('a' != operand->fmt)
-       {
-         value = *insn & 511;
-         if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
-           value -= 512;
-       }
-      else
-       value = 0;
-
-      flag_p = 1;
-      flagshimm_handled_p = 1;
-    }
-  else if (regno == ARC_REG_LIMM)
+static unsigned
+insert_rcs (unsigned insn,
+           int value,
+           const char **errmsg ATTRIBUTE_UNUSED)
+{
+  switch (value)
     {
-      op_type = OP_LIMM;
-      value = insn[1];
-      limm_p = 1;
-
-      /* If this is a jump instruction (j,jl), show new pc correctly.  */
-      if (0x07 == ((*insn & I(-1)) >> 27))
-       value = (value & 0xffffff);
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+      insn |= value << 5;
+      break;
+    case 12:
+    case 13:
+    case 14:
+    case 15:
+      insn |= ((value - 8)) << 5;
+      break;
+    default:
+      *errmsg = _("Register must be either r0-r3 or r12-r15.");
+      break;
     }
+  return insn;
+}
 
-  /* It's a register, set OPVAL (that's the only way we distinguish registers
-     from constants here).  */
+static int
+extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
+            bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = (insn >> 5) & 0x07;
+  if (value > 3)
+    return (value + 8);
   else
-    {
-      const struct arc_operand_value *reg = lookup_register (REG, regno);
-
-      op_type = OP_REG;
-
-      if (reg == NULL)
-       abort ();
-      if (opval != NULL)
-       *opval = reg;
-      value = regno;
-    }
-
-  /* If this field takes an auxiliary register, see if it's a known one.  */
-  if ((mods & ARC_MOD_AUXREG)
-      && ARC_REG_CONSTANT_P (regno))
-    {
-      const struct arc_operand_value *reg = lookup_register (AUXREG, value);
-
-      /* This is really a constant, but tell the caller it has a special
-        name.  */
-      if (reg != NULL && opval != NULL)
-       *opval = reg;
-    }
+    return value;
+}
 
-  switch(operand->fmt)
+static unsigned
+insert_simm3s (unsigned insn,
+              int value,
+              const char **errmsg ATTRIBUTE_UNUSED)
+{
+  int tmp = 0;
+  switch (value)
     {
-    case 'a':
-      ls_operand[LS_DEST] = op_type;
+    case -1:
+      tmp = 0x07;
       break;
-    case 's':
-      ls_operand[LS_BASE] = op_type;
+    case 0:
+      tmp = 0x00;
+      break;
+    case 1:
+      tmp = 0x01;
       break;
-    case 'c':
-      if ((insn[0]& I(-1)) == I(2))
-       ls_operand[LS_VALUE] = op_type;
-      else
-       ls_operand[LS_OFFSET] = op_type;
+    case 2:
+      tmp = 0x02;
       break;
-    case 'o': case 'O':
-      ls_operand[LS_OFFSET] = op_type;
+    case 3:
+      tmp = 0x03;
+      break;
+    case 4:
+      tmp = 0x04;
+      break;
+    case 5:
+      tmp = 0x05;
+      break;
+    case 6:
+      tmp = 0x06;
+      break;
+    default:
+      *errmsg = _("Accepted values are from -1 to 6.");
       break;
     }
 
-  return value;
+  insn |= tmp << 8;
+  return insn;
 }
 
-/* Return the value of the "flag update" field for shimm insns.
-   This value is actually stored in the register field.  */
-
-static long
-extract_flag (arc_insn *insn,
-             const struct arc_operand *operand,
-             int mods ATTRIBUTE_UNUSED,
-             const struct arc_operand_value **opval,
-             int *invalid ATTRIBUTE_UNUSED)
+static int
+extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
+               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  int f;
-  const struct arc_operand_value *val;
-
-  if (flagshimm_handled_p)
-    f = flag_p != 0;
+  int value = (insn >> 8) & 0x07;
+  if (value == 7)
+    return -1;
   else
-    f = (*insn & (1 << operand->shift)) != 0;
-
-  /* There is no text for zero values.  */
-  if (f == 0)
-    return 0;
-  flag_p = 1;
-  val = arc_opcode_lookup_suffix (operand, 1);
-  if (opval != NULL && val != NULL)
-    *opval = val;
-  return val->value;
+    return value;
 }
 
-/* Extract the condition code (if it exists).
-   If we've seen a shimm value in this insn (meaning that the insn can't have
-   a condition code field), then we don't store anything in OPVAL and return
-   zero.  */
-
-static long
-extract_cond (arc_insn *insn,
-             const struct arc_operand *operand,
-             int mods ATTRIBUTE_UNUSED,
-             const struct arc_operand_value **opval,
-             int *invalid ATTRIBUTE_UNUSED)
+static unsigned
+insert_rrange (unsigned insn,
+              int value,
+              const char **errmsg ATTRIBUTE_UNUSED)
 {
-  long cond;
-  const struct arc_operand_value *val;
-
-  if (flagshimm_handled_p)
-    return 0;
-
-  cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
-  val = arc_opcode_lookup_suffix (operand, cond);
-
-  /* Ignore NULL values of `val'.  Several condition code values are
-     reserved for extensions.  */
-  if (opval != NULL && val != NULL)
-    *opval = val;
-  return cond;
+  int reg1 = (value >> 16) & 0xFFFF;
+  int reg2 = value & 0xFFFF;
+  if (reg1 != 13)
+    {
+      *errmsg = _("First register of the range should be r13.");
+      return insn;
+    }
+  if (reg2 < 13 || reg2 > 26)
+    {
+      *errmsg = _("Last register of the range doesn't fit.");
+      return insn;
+    }
+  insn |= ((reg2 - 12) & 0x0F) << 1;
+  return insn;
 }
 
-/* Extract a branch address.
-   We return the value as a real address (not right shifted by 2).  */
+static int
+extract_rrange (unsigned insn  ATTRIBUTE_UNUSED,
+               bfd_boolean * invalid  ATTRIBUTE_UNUSED)
+{
+  return (insn >> 1) & 0x0F;
+}
 
-static long
-extract_reladdr (arc_insn *insn,
-                const struct arc_operand *operand,
-                int mods ATTRIBUTE_UNUSED,
-                const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
-                int *invalid ATTRIBUTE_UNUSED)
+static unsigned
+insert_fpel (unsigned insn,
+            int value,
+            const char **errmsg ATTRIBUTE_UNUSED)
 {
-  long addr;
+  if (value != 27)
+    {
+      *errmsg = _("Invalid register number, should be fp.");
+      return insn;
+    }
 
-  addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
-  if ((operand->flags & ARC_OPERAND_SIGNED)
-      && (addr & (1 << (operand->bits - 1))))
-    addr -= 1 << operand->bits;
-  return addr << 2;
+  insn |= 0x0100;
+  return insn;
 }
 
-/* Extract the flags bits from a j or jl long immediate.  */
-
-static long
-extract_jumpflags (arc_insn *insn,
-                  const struct arc_operand *operand,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
-                  int *invalid)
+static int
+extract_fpel (unsigned insn  ATTRIBUTE_UNUSED,
+             bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 {
-  if (!flag_p || !limm_p)
-    *invalid = 1;
-  return ((flag_p && limm_p)
-         ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
+  return (insn & 0x0100) ? 27 : -1;
 }
 
-/* Extract st insn's offset.  */
-
-static long
-extract_st_offset (arc_insn *insn,
-                  const struct arc_operand *operand,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
-                  int *invalid)
+static unsigned
+insert_blinkel (unsigned insn,
+               int value,
+               const char **errmsg ATTRIBUTE_UNUSED)
 {
-  int value = 0;
-
-  if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
+  if (value != 31)
     {
-      value = insn[0] & 511;
-      if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
-       value -= 512;
-      if (value)
-       ls_operand[LS_OFFSET] = OP_SHIMM;
+      *errmsg = _("Invalid register number, should be blink.");
+      return insn;
     }
-  else
-    *invalid = 1;
 
-  return value;
+  insn |= 0x0200;
+  return insn;
 }
 
-/* Extract ld insn's offset.  */
-
-static long
-extract_ld_offset (arc_insn *insn,
-                  const struct arc_operand *operand,
-                  int mods,
-                  const struct arc_operand_value **opval,
-                  int *invalid)
+static int
+extract_blinkel (unsigned insn  ATTRIBUTE_UNUSED,
+                bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 {
-  int test = insn[0] & I(-1);
-  int value;
+  return (insn & 0x0200) ? 31 : -1;
+}
 
-  if (test)
+static unsigned
+insert_pclel (unsigned insn,
+             int value,
+             const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value != 63)
     {
-      value = insn[0] & 511;
-      if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
-       value -= 512;
-      if (value)
-       ls_operand[LS_OFFSET] = OP_SHIMM;
-
-      return value;
+      *errmsg = _("Invalid register number, should be pcl.");
+      return insn;
     }
-  /* If it isn't in the insn, it's concealed behind reg 'c'.  */
-  return extract_reg (insn, &arc_operands[arc_operand_map['c']],
-                     mods, opval, invalid);
-}
 
-/* The only thing this does is set the `invalid' flag if B != C.
-   This is needed because the "mov" macro appears before it's real insn "and"
-   and we don't want the disassembler to confuse them.  */
+  insn |= 0x0400;
+  return insn;
+}
 
-static long
-extract_unopmacro (arc_insn *insn,
-                  const struct arc_operand *operand ATTRIBUTE_UNUSED,
-                  int mods ATTRIBUTE_UNUSED,
-                  const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
-                  int *invalid)
+static int
+extract_pclel (unsigned insn  ATTRIBUTE_UNUSED,
+              bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 {
-  /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
-     C == ARC_REG_SHIMM (or vice versa).  No big deal.  Those insns will get
-     printed as "and"s.  */
-  if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
-      != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
-    if (invalid != NULL)
-      *invalid = 1;
-  return 0;
+  return (insn & 0x0400) ? 63 : -1;
 }
-\f
-/* ARC instructions.
-
-   Longer versions of insns must appear before shorter ones (if gas sees
-   "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
-   junk).  This isn't necessary for `ld' because of the trailing ']'.
-
-   Instructions that are really macros based on other insns must appear
-   before the real insn so they're chosen when disassembling.  Eg: The `mov'
-   insn is really the `and' insn.  */
 
-struct arc_opcode arc_opcodes[] =
+#define INSERT_W6
+/* mask = 00000000000000000000111111000000
+   insn = 00011bbb000000000BBBwwwwwwDaaZZ1.  */
+static unsigned
+insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
+          int value ATTRIBUTE_UNUSED,
+          const char **errmsg ATTRIBUTE_UNUSED)
 {
-  /* Base case instruction set (core versions 5-8).  */
-
-  /* "mov" is really an "and".  */
-  { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
-  /* "asl" is really an "add".  */
-  { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
-  /* "lsl" is really an "add".  */
-  { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
-  /* "nop" is really an "xor".  */
-  { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
-  /* "rlc" is really an "adc".  */
-  { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
-  { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
-  { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
-  { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
-  { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
-  { "bic%.q%.f %a,%b,%c%F%S%L",        I(-1), I(14), ARC_MACH_5, 0, 0 },
-  { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
-  { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
-  { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
-  { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
-  { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
-  { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
-  /* %Q: force cond_p=1 -> no shimm values. This insn allows an
-     optional flags spec.  */
-  { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  /* This insn allows an optional flags spec.  */
-  { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  /* Put opcode 1 ld insns first so shimm gets prefered over limm.
-     "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
-  { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
-  { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
-  { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
-  { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1),        I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
-  { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
-  { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
-  { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
-  { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
-  { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
-  { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
-  { "sbc%.q%.f %a,%b,%c%F%S%L",        I(-1), I(11), ARC_MACH_5, 0, 0 },
-  { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
-  { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
-  { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
-  /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
-  { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
-  { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
-  { "sub%.q%.f %a,%b,%c%F%S%L",        I(-1), I(10), ARC_MACH_5, 0, 0 },
-  { "xor%.q%.f %a,%b,%c%F%S%L",        I(-1), I(15), ARC_MACH_5, 0, 0 }
-};
+  insn |= ((value >> 0) & 0x003f) << 6;
 
-const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
+  return insn;
+}
 
-const struct arc_operand_value arc_reg_names[] =
+#define EXTRACT_W6
+/* mask = 00000000000000000000111111000000.  */
+static int
+extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
+           bfd_boolean * invalid ATTRIBUTE_UNUSED)
 {
-  /* Core register set r0-r63.  */
-
-  /* r0-r28 - general purpose registers.  */
-  { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
-  { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
-  { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
-  { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
-  { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
-  { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
-  { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
-  { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
-  { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
-  { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
-  /* Maskable interrupt link register.  */
-  { "ilink1", 29, REG, 0 },
-  /* Maskable interrupt link register.  */
-  { "ilink2", 30, REG, 0 },
-  /* Branch-link register.  */
-  { "blink", 31, REG, 0 },
-
-  /* r32-r59 reserved for extensions.  */
-  { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
-  { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
-  { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
-  { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
-  { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
-  { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
-  { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
-  { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
-  { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
-  { "r59", 59, REG, 0 },
-
-  /* Loop count register (24 bits).  */
-  { "lp_count", 60, REG, 0 },
-  /* Short immediate data indicator setting flags.  */
-  { "r61", 61, REG, ARC_REGISTER_READONLY },
-  /* Long immediate data indicator setting flags.  */
-  { "r62", 62, REG, ARC_REGISTER_READONLY },
-  /* Short immediate data indicator not setting flags.  */
-  { "r63", 63, REG, ARC_REGISTER_READONLY },
-
-  /* Small-data base register.  */
-  { "gp", 26, REG, 0 },
-  /* Frame pointer.  */
-  { "fp", 27, REG, 0 },
-  /* Stack pointer.  */
-  { "sp", 28, REG, 0 },
-
-  { "r29", 29, REG, 0 },
-  { "r30", 30, REG, 0 },
-  { "r31", 31, REG, 0 },
-  { "r60", 60, REG, 0 },
-
-  /* Auxiliary register set.  */
-
-  /* Auxiliary register address map:
-     0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
-     0xfffffeff-0x80000000 - customer limm allocation
-     0x7fffffff-0x00000100 - ARC limm allocation
-     0x000000ff-0x00000000 - ARC shimm allocation  */
-
-  /* Base case auxiliary registers (shimm address).  */
-  { "status",         0x00, AUXREG, 0 },
-  { "semaphore",      0x01, AUXREG, 0 },
-  { "lp_start",       0x02, AUXREG, 0 },
-  { "lp_end",         0x03, AUXREG, 0 },
-  { "identity",       0x04, AUXREG, ARC_REGISTER_READONLY },
-  { "debug",          0x05, AUXREG, 0 },
-};
+  unsigned value = 0;
 
-const int arc_reg_names_count =
-  sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
+  value |= ((insn >> 6) & 0x003f) << 0;
 
-/* The suffix table.
-   Operands with the same name must be stored together.  */
+  return value;
+}
 
-const struct arc_operand_value arc_suffixes[] =
+#define INSERT_G_S
+/* mask = 0000011100022000
+   insn = 01000ggghhhGG0HH.  */
+static unsigned
+insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
+           int value ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)
 {
-  /* Entry 0 is special, default values aren't printed by the disassembler.  */
-  { "", 0, -1, 0 },
-
-  /* Base case condition codes.  */
-  { "al", 0, COND, 0 },
-  { "ra", 0, COND, 0 },
-  { "eq", 1, COND, 0 },
-  { "z", 1, COND, 0 },
-  { "ne", 2, COND, 0 },
-  { "nz", 2, COND, 0 },
-  { "pl", 3, COND, 0 },
-  { "p", 3, COND, 0 },
-  { "mi", 4, COND, 0 },
-  { "n", 4, COND, 0 },
-  { "cs", 5, COND, 0 },
-  { "c", 5, COND, 0 },
-  { "lo", 5, COND, 0 },
-  { "cc", 6, COND, 0 },
-  { "nc", 6, COND, 0 },
-  { "hs", 6, COND, 0 },
-  { "vs", 7, COND, 0 },
-  { "v", 7, COND, 0 },
-  { "vc", 8, COND, 0 },
-  { "nv", 8, COND, 0 },
-  { "gt", 9, COND, 0 },
-  { "ge", 10, COND, 0 },
-  { "lt", 11, COND, 0 },
-  { "le", 12, COND, 0 },
-  { "hi", 13, COND, 0 },
-  { "ls", 14, COND, 0 },
-  { "pnz", 15, COND, 0 },
-
-  /* Condition codes 16-31 reserved for extensions.  */
-
-  { "f", 1, FLAG, 0 },
-
-  { "nd", ARC_DELAY_NONE, DELAY, 0 },
-  { "d", ARC_DELAY_NORMAL, DELAY, 0 },
-  { "jd", ARC_DELAY_JUMP, DELAY, 0 },
-
-  { "b", 1, SIZE1, 0 },
-  { "b", 1, SIZE10, 0 },
-  { "b", 1, SIZE22, 0 },
-  { "w", 2, SIZE1, 0 },
-  { "w", 2, SIZE10, 0 },
-  { "w", 2, SIZE22, 0 },
-  { "x", 1, SIGN0, 0 },
-  { "x", 1, SIGN9, 0 },
-  { "a", 1, ADDRESS3, 0 },
-  { "a", 1, ADDRESS12, 0 },
-  { "a", 1, ADDRESS24, 0 },
-
-  { "di", 1, CACHEBYPASS5, 0 },
-  { "di", 1, CACHEBYPASS14, 0 },
-  { "di", 1, CACHEBYPASS26, 0 },
-};
+  insn |= ((value >> 0) & 0x0007) << 8;
+  insn |= ((value >> 3) & 0x0003) << 3;
 
-const int arc_suffixes_count =
-  sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
-
-/* Indexed by first letter of opcode.  Points to chain of opcodes with same
-   first letter.  */
-static struct arc_opcode *opcode_map[26 + 1];
+  return insn;
+}
 
-/* Indexed by insn code.  Points to chain of opcodes with same insn code.  */
-static struct arc_opcode *icode_map[32];
-\f
-/* Configuration flags.  */
+#define EXTRACT_G_S
+/* mask = 0000011100022000.  */
+static int
+extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
+            bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
 
-/* Various ARC_HAVE_XXX bits.  */
-static int cpu_type;
+  value |= ((insn >> 8) & 0x0007) << 0;
+  value |= ((insn >> 3) & 0x0003) << 3;
 
-/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value.  */
+  /* Extend the sign.  */
+  int signbit = 1 << (6 - 1);
+  value = (value ^ signbit) - signbit;
 
-int
-arc_get_opcode_mach (int bfd_mach, int big_p)
-{
-  static int mach_type_map[] =
-  {
-    ARC_MACH_5,
-    ARC_MACH_6,
-    ARC_MACH_7,
-    ARC_MACH_8
-  };
-  return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0);
+  return value;
 }
 
-/* Initialize any tables that need it.
-   Must be called once at start up (or when first needed).
+/* Include the generic extract/insert functions.  Order is important
+   as some of the functions present in the .h may be disabled via
+   defines.  */
+#include "arc-fxi.h"
 
-   FLAGS is a set of bits that say what version of the cpu we have,
-   and in particular at least (one of) ARC_MACH_XXX.  */
+/* Abbreviations for instruction subsets.  */
+#define BASE                   ARC_OPCODE_BASE
 
-void
-arc_opcode_init_tables (int flags)
-{
-  static int init_p = 0;
+/* The flag operands table.
 
-  cpu_type = flags;
+   The format of the table is
+   NAME CODE BITS SHIFT FAVAIL.  */
+const struct arc_flag_operand arc_flag_operands[] =
+{
+#define F_NULL 0
+  { 0, 0, 0, 0, 0},
+#define F_ALWAYS    (F_NULL + 1)
+  { "al", 0, 0, 0, 0 },
+#define F_RA       (F_ALWAYS + 1)
+  { "ra", 0, 0, 0, 0 },
+#define F_EQUAL            (F_RA + 1)
+  { "eq", 1, 5, 0, 1 },
+#define F_ZERO     (F_EQUAL + 1)
+  { "z",  1, 5, 0, 0 },
+#define F_NOTEQUAL  (F_ZERO + 1)
+  { "ne", 2, 5, 0, 1 },
+#define F_NOTZERO   (F_NOTEQUAL + 1)
+  { "nz", 2, 5, 0, 0 },
+#define F_POZITIVE  (F_NOTZERO + 1)
+  { "p",  3, 5, 0, 1 },
+#define F_PL       (F_POZITIVE + 1)
+  { "pl", 3, 5, 0, 0 },
+#define F_NEGATIVE  (F_PL + 1)
+  { "n",  4, 5, 0, 1 },
+#define F_MINUS            (F_NEGATIVE + 1)
+  { "mi", 4, 5, 0, 0 },
+#define F_CARRY            (F_MINUS + 1)
+  { "c",  5, 5, 0, 1 },
+#define F_CARRYSET  (F_CARRY + 1)
+  { "cs", 5, 5, 0, 0 },
+#define F_LOWER            (F_CARRYSET + 1)
+  { "lo", 5, 5, 0, 0 },
+#define F_CARRYCLR  (F_LOWER + 1)
+  { "cc", 6, 5, 0, 0 },
+#define F_NOTCARRY (F_CARRYCLR + 1)
+  { "nc", 6, 5, 0, 1 },
+#define F_HIGHER   (F_NOTCARRY + 1)
+  { "hs", 6, 5, 0, 0 },
+#define F_OVERFLOWSET (F_HIGHER + 1)
+  { "vs", 7, 5, 0, 0 },
+#define F_OVERFLOW (F_OVERFLOWSET + 1)
+  { "v",  7, 5, 0, 1 },
+#define F_NOTOVERFLOW (F_OVERFLOW + 1)
+  { "nv", 8, 5, 0, 1 },
+#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
+  { "vc", 8, 5, 0, 0 },
+#define F_GT      (F_OVERFLOWCLR + 1)
+  { "gt", 9, 5, 0, 1 },
+#define F_GE      (F_GT + 1)
+  { "ge", 10, 5, 0, 1 },
+#define F_LT      (F_GE + 1)
+  { "lt", 11, 5, 0, 1 },
+#define F_LE      (F_LT + 1)
+  { "le", 12, 5, 0, 1 },
+#define F_HI      (F_LE + 1)
+  { "hi", 13, 5, 0, 1 },
+#define F_LS      (F_HI + 1)
+  { "ls", 14, 5, 0, 1 },
+#define F_PNZ     (F_LS + 1)
+  { "pnz", 15, 5, 0, 1 },
+
+  /* FLAG.  */
+#define F_FLAG     (F_PNZ + 1)
+  { "f",  1, 1, 15, 1 },
+#define F_FFAKE     (F_FLAG + 1)
+  { "f",  0, 0, 0, 1 },
+
+  /* Delay slot.  */
+#define F_ND      (F_FFAKE + 1)
+  { "nd", 0, 1, 5, 0 },
+#define F_D       (F_ND + 1)
+  { "d",  1, 1, 5, 1 },
+#define F_DFAKE           (F_D + 1)
+  { "d",  0, 0, 0, 1 },
+
+  /* Data size.  */
+#define F_SIZEB1   (F_DFAKE + 1)
+  { "b", 1, 2, 1, 1 },
+#define F_SIZEB7   (F_SIZEB1 + 1)
+  { "b", 1, 2, 7, 1 },
+#define F_SIZEB17  (F_SIZEB7 + 1)
+  { "b", 1, 2, 17, 1 },
+#define F_SIZEW1   (F_SIZEB17 + 1)
+  { "w", 2, 2, 1, 0 },
+#define F_SIZEW7   (F_SIZEW1 + 1)
+  { "w", 2, 2, 7, 0 },
+#define F_SIZEW17  (F_SIZEW7 + 1)
+  { "w", 2, 2, 17, 0 },
+
+  /* Sign extension.  */
+#define F_SIGN6   (F_SIZEW17 + 1)
+  { "x", 1, 1, 6, 1 },
+#define F_SIGN16  (F_SIGN6 + 1)
+  { "x", 1, 1, 16, 1 },
+#define F_SIGNX   (F_SIGN16 + 1)
+  { "x", 0, 0, 0, 1 },
+
+  /* Address write-back modes.  */
+#define F_A3       (F_SIGNX + 1)
+  { "a", 1, 2, 3, 0 },
+#define F_A9       (F_A3 + 1)
+  { "a", 1, 2, 9, 0 },
+#define F_A22      (F_A9 + 1)
+  { "a", 1, 2, 22, 0 },
+#define F_AW3      (F_A22 + 1)
+  { "aw", 1, 2, 3, 1 },
+#define F_AW9      (F_AW3 + 1)
+  { "aw", 1, 2, 9, 1 },
+#define F_AW22     (F_AW9 + 1)
+  { "aw", 1, 2, 22, 1 },
+#define F_AB3      (F_AW22 + 1)
+  { "ab", 2, 2, 3, 1 },
+#define F_AB9      (F_AB3 + 1)
+  { "ab", 2, 2, 9, 1 },
+#define F_AB22     (F_AB9 + 1)
+  { "ab", 2, 2, 22, 1 },
+#define F_AS3      (F_AB22 + 1)
+  { "as", 3, 2, 3, 1 },
+#define F_AS9      (F_AS3 + 1)
+  { "as", 3, 2, 9, 1 },
+#define F_AS22     (F_AS9 + 1)
+  { "as", 3, 2, 22, 1 },
+#define F_ASFAKE   (F_AS22 + 1)
+  { "as", 0, 0, 0, 1 },
+
+  /* Cache bypass.  */
+#define F_DI5     (F_ASFAKE + 1)
+  { "di", 1, 1, 5, 1 },
+#define F_DI11    (F_DI5 + 1)
+  { "di", 1, 1, 11, 1 },
+#define F_DI15    (F_DI11 + 1)
+  { "di", 1, 1, 15, 1 },
+
+  /* ARCv2 specific.  */
+#define F_NT     (F_DI15 + 1)
+  { "nt", 0, 1, 3, 1},
+#define F_T      (F_NT + 1)
+  { "t", 1, 1, 3, 1},
+#define F_H1     (F_T + 1)
+  { "h", 2, 2, 1, 1 },
+#define F_H7     (F_H1 + 1)
+  { "h", 2, 2, 7, 1 },
+#define F_H17    (F_H7 + 1)
+  { "h", 2, 2, 17, 1 },
+
+  /* Fake Flags.  */
+#define F_NE   (F_H17 + 1)
+  { "ne", 0, 0, 0, 1 },
+};
 
-  /* We may be intentionally called more than once (for example gdb will call
-     us each time the user switches cpu).  These tables only need to be init'd
-     once though.  */
-  if (!init_p)
-    {
-      int i,n;
+const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
 
-      memset (arc_operand_map, 0, sizeof (arc_operand_map));
-      n = sizeof (arc_operands) / sizeof (arc_operands[0]);
-      for (i = 0; i < n; ++i)
-       arc_operand_map[arc_operands[i].fmt] = i;
+/* Table of the flag classes.
 
-      memset (opcode_map, 0, sizeof (opcode_map));
-      memset (icode_map, 0, sizeof (icode_map));
-      /* Scan the table backwards so macros appear at the front.  */
-      for (i = arc_opcodes_count - 1; i >= 0; --i)
-       {
-         int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
-         int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
+   The format of the table is
+   CLASS {FLAG_CODE}.  */
+const struct arc_flag_class arc_flag_classes[] =
+{
+#define C_EMPTY     0
+  { FNONE, { F_NULL } },
+
+#define C_CC       (C_EMPTY + 1)
+  { CND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO,
+          F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET,
+          F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET,
+          F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
+          F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+
+#define C_AA_ADDR3  (C_CC + 1)
+#define C_AA27     (C_CC + 1)
+  { WBM, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
+#define C_AA_ADDR9  (C_AA_ADDR3 + 1)
+#define C_AA21      (C_AA_ADDR3 + 1)
+  { WBM, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
+#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
+#define C_AA8     (C_AA_ADDR9 + 1)
+  { WBM, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
+
+#define C_F        (C_AA_ADDR22 + 1)
+  { FLG, { F_FLAG, F_NULL } },
+#define C_FHARD            (C_F + 1)
+  { FLG, { F_FFAKE, F_NULL } },
+
+#define C_T        (C_FHARD + 1)
+  { SBP, { F_NT, F_T, F_NULL } },
+#define C_D        (C_T + 1)
+  { DLY, { F_ND, F_D, F_NULL } },
+
+#define C_DHARD            (C_D + 1)
+  { DLY, { F_DFAKE, F_NULL } },
+
+#define C_DI20     (C_DHARD + 1)
+  { DIF, { F_DI11, F_NULL }},
+#define C_DI16     (C_DI20 + 1)
+  { DIF, { F_DI15, F_NULL }},
+#define C_DI26     (C_DI16 + 1)
+  { DIF, { F_DI5, F_NULL }},
+
+#define C_X25      (C_DI26 + 1)
+  { SGX, { F_SIGN6, F_NULL }},
+#define C_X15     (C_X25 + 1)
+  { SGX, { F_SIGN16, F_NULL }},
+#define C_XHARD           (C_X15 + 1)
+#define C_X       (C_X15 + 1)
+  { SGX, { F_SIGNX, F_NULL }},
+
+#define C_ZZ13       (C_X + 1)
+  { SZM, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
+#define C_ZZ23       (C_ZZ13 + 1)
+  { SZM, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
+#define C_ZZ29       (C_ZZ23 + 1)
+  { SZM, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
+
+#define C_AS       (C_ZZ29 + 1)
+  { SZM, { F_ASFAKE, F_NULL}},
+
+#define C_NE       (C_AS + 1)
+  { CND, { F_NE, F_NULL}},
+};
 
-         arc_opcodes[i].next_asm = opcode_map[opcode_hash];
-         opcode_map[opcode_hash] = &arc_opcodes[i];
+/* The operands table.
 
-         arc_opcodes[i].next_dis = icode_map[icode_hash];
-         icode_map[icode_hash] = &arc_opcodes[i];
-       }
+   The format of the operands table is:
 
-      init_p = 1;
-    }
-}
-
-/* Return non-zero if OPCODE is supported on the specified cpu.
-   Cpu selection is made when calling `arc_opcode_init_tables'.  */
-
-int
-arc_opcode_supported (const struct arc_opcode *opcode)
+   BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN.  */
+const struct arc_operand arc_operands[] =
 {
-  if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
-    return 1;
-  return 0;
-}
-
-/* Return the first insn in the chain for assembling INSN.  */
+  /* The fields are bits, shift, insert, extract, flags.  The zero
+     index is used to indicate end-of-list.  */
+#define UNUSED         0
+  { 0, 0, 0, 0, 0, 0 },
+  /* The plain integer register fields.  Used by 32 bit
+     instructions.  */
+#define RA             (UNUSED + 1)
+  { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
+#define RB             (RA + 1)
+  { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
+#define RC             (RB + 1)
+  { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
+#define RBdup          (RC + 1)
+  { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
+
+#define RAD            (RBdup + 1)
+  { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
+#define RCD            (RAD + 1)
+  { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
+
+  /* The plain integer register fields.  Used by short
+     instructions.  */
+#define RA16           (RCD + 1)
+#define RA_S           (RCD + 1)
+  { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
+#define RB16           (RA16 + 1)
+#define RB_S           (RA16 + 1)
+  { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
+#define RB16dup                (RB16 + 1)
+#define RB_Sdup                (RB16 + 1)
+  { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
+#define RC16           (RB16dup + 1)
+#define RC_S           (RB16dup + 1)
+  { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
+#define R6H            (RC16 + 1)   /* 6bit register field 'h' used
+                                       by V1 cpus.  */
+  { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
+#define R5H            (R6H + 1)    /* 5bit register field 'h' used
+                                       by V2 cpus.  */
+#define RH_S           (R6H + 1)    /* 5bit register field 'h' used
+                                       by V2 cpus.  */
+  { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
+#define R5Hdup         (R5H + 1)
+#define RH_Sdup                (R5H + 1)
+  { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
+    insert_rhv2, extract_rhv2 },
+
+#define RG             (R5Hdup + 1)
+#define G_S            (R5Hdup + 1)
+  { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
+
+  /* Fix registers.  */
+#define R0             (RG + 1)
+#define R0_S           (RG + 1)
+  { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
+#define R1             (R0 + 1)
+#define R1_S           (R0 + 1)
+  { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
+#define R2             (R1 + 1)
+#define R2_S           (R1 + 1)
+  { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
+#define R3             (R2 + 1)
+#define R3_S           (R2 + 1)
+  { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
+#define SP             (R3 + 1)
+#define SP_S           (R3 + 1)
+  { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
+#define SPdup          (SP + 1)
+#define SP_Sdup                (SP + 1)
+  { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
+#define GP             (SPdup + 1)
+#define GP_S           (SPdup + 1)
+  { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
+
+#define PCL_S          (GP + 1)
+  { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
+
+#define BLINK          (PCL_S + 1)
+#define BLINK_S                (PCL_S + 1)
+  { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
+
+#define ILINK1         (BLINK + 1)
+  { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
+#define ILINK2         (ILINK1 + 1)
+  { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
+
+  /* Long immediate.  */
+#define LIMM           (ILINK2 + 1)
+#define LIMM_S         (ILINK2 + 1)
+  { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
+#define LIMMdup                (LIMM + 1)
+  { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
+
+  /* Special operands.  */
+#define ZA             (LIMMdup + 1)
+#define ZB             (LIMMdup + 1)
+#define ZA_S           (LIMMdup + 1)
+#define ZB_S           (LIMMdup + 1)
+#define ZC_S           (LIMMdup + 1)
+  { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
+
+#define RRANGE_EL      (ZA + 1)
+  { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
+    insert_rrange, extract_rrange},
+#define FP_EL          (RRANGE_EL + 1)
+  { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+    insert_fpel, extract_fpel },
+#define BLINK_EL       (FP_EL + 1)
+  { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+    insert_blinkel, extract_blinkel },
+#define PCL_EL         (BLINK_EL + 1)
+  { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+    insert_pclel, extract_pclel },
+
+  /* Fake operand to handle the T flag.  */
+#define BRAKET         (PCL_EL + 1)
+#define BRAKETdup      (PCL_EL + 1)
+  { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
+
+  /* Fake operand to handle the T flag.  */
+#define FKT_T          (BRAKET + 1)
+  { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
+  /* Fake operand to handle the T flag.  */
+#define FKT_NT         (FKT_T + 1)
+  { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
+
+  /* UIMM6_20 mask = 00000000000000000000111111000000.  */
+#define UIMM6_20       (FKT_NT + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
+
+  /* SIMM12_20 mask = 00000000000000000000111111222222.  */
+#define SIMM12_20      (UIMM6_20 + 1)
+  {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
+
+  /* SIMM3_5_S mask = 0000011100000000.  */
+#define SIMM3_5_S      (SIMM12_20 + 1)
+  {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
+   insert_simm3s, extract_simm3s},
+
+  /* UIMM7_A32_11_S mask = 0000000000011111.  */
+#define UIMM7_A32_11_S      (SIMM3_5_S + 1)
+  {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
+   extract_uimm7_a32_11_s},
+
+  /* UIMM7_9_S mask = 0000000001111111.  */
+#define UIMM7_9_S      (UIMM7_A32_11_S + 1)
+  {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
+
+  /* UIMM3_13_S mask = 0000000000000111.  */
+#define UIMM3_13_S      (UIMM7_9_S + 1)
+  {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
+
+  /* SIMM11_A32_7_S mask = 0000000111111111.  */
+#define SIMM11_A32_7_S      (UIMM3_13_S + 1)
+  {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
+
+  /* UIMM6_13_S mask = 0000000002220111.  */
+#define UIMM6_13_S      (SIMM11_A32_7_S + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
+  /* UIMM5_11_S mask = 0000000000011111.  */
+#define UIMM5_11_S      (UIMM6_13_S + 1)
+  {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
+   extract_uimm5_11_s},
+
+  /* SIMM9_A16_8 mask = 00000000111111102000000000000000.  */
+#define SIMM9_A16_8      (UIMM5_11_S + 1)
+  {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
+   extract_simm9_a16_8},
+
+  /* UIMM6_8 mask = 00000000000000000000111111000000.   */
+#define UIMM6_8              (SIMM9_A16_8 + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
+
+  /* SIMM21_A16_5 mask = 00000111111111102222222222000000.  */
+#define SIMM21_A16_5      (UIMM6_8 + 1)
+  {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
+   | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
+   insert_simm21_a16_5, extract_simm21_a16_5},
+
+  /* SIMM25_A16_5 mask = 00000111111111102222222222003333.  */
+#define SIMM25_A16_5      (SIMM21_A16_5 + 1)
+  {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
+   | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
+   insert_simm25_a16_5, extract_simm25_a16_5},
+
+  /* SIMM10_A16_7_S mask = 0000000111111111.  */
+#define SIMM10_A16_7_S      (SIMM25_A16_5 + 1)
+  {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
+   extract_simm10_a16_7_s},
+
+#define SIMM10_A16_7_Sbis    (SIMM10_A16_7_S + 1)
+  {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
+
+  /* SIMM7_A16_10_S mask = 0000000000111111.  */
+#define SIMM7_A16_10_S      (SIMM10_A16_7_Sbis + 1)
+  {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
+   extract_simm7_a16_10_s},
+
+  /* SIMM21_A32_5 mask = 00000111111111002222222222000000.  */
+#define SIMM21_A32_5      (SIMM7_A16_10_S + 1)
+  {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
+   extract_simm21_a32_5},
+
+  /* SIMM25_A32_5 mask = 00000111111111002222222222003333.  */
+#define SIMM25_A32_5      (SIMM21_A32_5 + 1)
+  {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
+   extract_simm25_a32_5},
+
+  /* SIMM13_A32_5_S mask = 0000011111111111.  */
+#define SIMM13_A32_5_S      (SIMM25_A32_5 + 1)
+  {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
+   extract_simm13_a32_5_s},
+
+  /* SIMM8_A16_9_S mask = 0000000001111111.  */
+#define SIMM8_A16_9_S      (SIMM13_A32_5_S + 1)
+  {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
+   extract_simm8_a16_9_s},
+
+  /* UIMM3_23 mask = 00000000000000000000000111000000.  */
+#define UIMM3_23       (SIMM8_A16_9_S + 1)
+  {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
+
+  /* UIMM10_6_S mask = 0000001111111111.  */
+#define UIMM10_6_S      (UIMM3_23 + 1)
+  {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
+
+  /* UIMM6_11_S mask = 0000002200011110.  */
+#define UIMM6_11_S      (UIMM10_6_S + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
+
+  /* SIMM9_8 mask = 00000000111111112000000000000000.   */
+#define SIMM9_8              (UIMM6_11_S + 1)
+  {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
+   insert_simm9_8, extract_simm9_8},
+
+  /* UIMM10_A32_8_S mask = 0000000011111111.  */
+#define UIMM10_A32_8_S      (SIMM9_8 + 1)
+  {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
+   extract_uimm10_a32_8_s},
+
+  /* SIMM9_7_S mask = 0000000111111111.  */
+#define SIMM9_7_S      (UIMM10_A32_8_S + 1)
+  {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
+   extract_simm9_7_s},
+
+  /* UIMM6_A16_11_S mask = 0000000000011111.  */
+#define UIMM6_A16_11_S      (SIMM9_7_S + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE  | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
+   extract_uimm6_a16_11_s},
+
+  /* UIMM5_A32_11_S mask = 0000020000011000.  */
+#define UIMM5_A32_11_S      (UIMM6_A16_11_S + 1)
+  {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
+   extract_uimm5_a32_11_s},
+
+  /* SIMM11_A32_13_S mask = 0000022222200111.   */
+#define SIMM11_A32_13_S              (UIMM5_A32_11_S + 1)
+  {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
+
+  /* UIMM7_13_S mask = 0000000022220111.  */
+#define UIMM7_13_S      (SIMM11_A32_13_S + 1)
+  {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
+
+  /* UIMM6_A16_21 mask = 00000000000000000000011111000000.  */
+#define UIMM6_A16_21      (UIMM7_13_S + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
+
+  /* UIMM7_11_S mask = 0000022200011110.  */
+#define UIMM7_11_S      (UIMM6_A16_21 + 1)
+  {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
+
+  /* UIMM7_A16_20 mask = 00000000000000000000111111000000.  */
+#define UIMM7_A16_20      (UIMM7_11_S + 1)
+  {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
+   extract_uimm7_a16_20},
+
+  /* SIMM13_A16_20 mask = 00000000000000000000111111222222.  */
+#define SIMM13_A16_20      (UIMM7_A16_20 + 1)
+  {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
+   extract_simm13_a16_20},
+
+  /* UIMM8_8_S mask = 0000000011111111.  */
+#define UIMM8_8_S      (SIMM13_A16_20 + 1)
+  {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
+
+  /* W6 mask = 00000000000000000000111111000000.  */
+#define W6      (UIMM8_8_S + 1)
+  {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
+
+  /* UIMM6_5_S mask = 0000011111100000.  */
+#define UIMM6_5_S      (W6 + 1)
+  {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+};
 
-const struct arc_opcode *
-arc_opcode_lookup_asm (const char *insn)
-{
-  return opcode_map[ARC_HASH_OPCODE (insn)];
-}
+const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
 
-/* Return the first insn in the chain for disassembling INSN.  */
+const unsigned arc_Toperand = FKT_T;
+const unsigned arc_NToperand = FKT_NT;
 
-const struct arc_opcode *
-arc_opcode_lookup_dis (unsigned int insn)
-{
-  return icode_map[ARC_HASH_ICODE (insn)];
-}
+/* The opcode table.
 
-/* Called by the assembler before parsing an instruction.  */
+   The format of the opcode table is:
 
-void
-arc_opcode_init_insert (void)
+   NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.  */
+const struct arc_opcode arc_opcodes[] =
 {
-  int i;
-
-  for(i = 0; i < OPERANDS; i++)
-    ls_operand[i] = OP_NONE;
-
-  flag_p = 0;
-  flagshimm_handled_p = 0;
-  cond_p = 0;
-  addrwb_p = 0;
-  shimm_p = 0;
-  limm_p = 0;
-  jumpflags_p = 0;
-  nullify_p = 0;
-  nullify = 0; /* The default is important.  */
-}
+#include "arc-tbl.h"
+};
 
-/* Called by the assembler to see if the insn has a limm operand.
-   Also called by the disassembler to see if the insn contains a limm.  */
+const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
 
-int
-arc_opcode_limm_p (long *limmp)
+/* List with special cases instructions and the applicable flags.  */
+const struct arc_flag_special arc_flag_special_cases[] =
 {
-  if (limmp)
-    *limmp = limm;
-  return limm_p;
-}
+  { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+          F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+          F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+          F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+           F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+           F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+           F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+           F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+           F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+           F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+          F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+          F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+          F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+           F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+           F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+           F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+           F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+           F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+           F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+            F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+            F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+            F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
+  { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
+};
 
-/* Utility for the extraction functions to return the index into
-   `arc_suffixes'.  */
+const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
 
-const struct arc_operand_value *
-arc_opcode_lookup_suffix (const struct arc_operand *type, int value)
-{
-  const struct arc_operand_value *v,*end;
-  struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+/* Relocations.  */
+#undef DEF
+#define DEF(NAME, EXC1, EXC2, RELOC1, RELOC2)  \
+  { #NAME, EXC1, EXC2, RELOC1, RELOC2}
 
-  while (ext_oper)
-    {
-      if (type == &arc_operands[ext_oper->operand.type]
-         && value == ext_oper->operand.value)
-       return (&ext_oper->operand);
-      ext_oper = ext_oper->next;
-    }
+const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
+{
+  DEF (sda, "ld", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
+  DEF (sda, "st", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
+  DEF (sda, "ldw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
+  DEF (sda, "ldh", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
+  DEF (sda, "stw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
+  DEF (sda, "sth", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
+
+  /* Short instructions.  */
+  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD),
+  DEF (sda, 0, F_NULL, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1),
+  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2),
+  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2),
+
+  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME),
+  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST),
+
+  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25H_PCREL,
+       BFD_RELOC_ARC_S25H_PCREL_PLT),
+  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21H_PCREL,
+       BFD_RELOC_ARC_S21H_PCREL_PLT),
+  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25W_PCREL,
+       BFD_RELOC_ARC_S25W_PCREL_PLT),
+  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21W_PCREL,
+       BFD_RELOC_ARC_S21W_PCREL_PLT),
+
+  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32),
+};
 
-  /* ??? This is a little slow and can be speeded up.  */
-  for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
-    if (type == &arc_operands[v->type]
-       && value == v->value)
-      return v;
-  return 0;
-}
+const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
 
-int
-arc_insn_is_j (arc_insn insn)
+const struct arc_pseudo_insn arc_pseudo_insns[] =
 {
-  return (insn & (I(-1))) == I(0x7);
-}
+  { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+                             { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
+                             { BRAKETdup, 1, 0, 4} } },
+  { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+                            { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
+                            { BRAKETdup, 1, 0, 4} } },
+
+  { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+
+  { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+
+  { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+
+  { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+  { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+                              { SIMM9_A16_8, 0, 0, 2 } } },
+};
 
-int
-arc_insn_not_jl (arc_insn insn)
-{
-  return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
-         != (I(0x7) | R(-1,9,1)));
-}
+const unsigned arc_num_pseudo_insn =
+  sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
 
-int
-arc_operand_type (int opertype)
+const struct arc_aux_reg arc_aux_regs[] =
 {
-  switch (opertype)
-    {
-    case 0:
-      return COND;
-      break;
-    case 1:
-      return REG;
-      break;
-    case 2:
-      return AUXREG;
-      break;
-    }
-  return -1;
-}
+#undef DEF
+#define DEF(ADDR, NAME)                                \
+  { ADDR, #NAME, sizeof (#NAME)-1 },
 
-struct arc_operand_value *
-get_ext_suffix (char *s)
-{
-  struct arc_ext_operand_value *suffix = arc_ext_operands;
+#include "arc-regs.h"
 
-  while (suffix)
-    {
-      if ((COND == suffix->operand.type)
-         && !strcmp(s,suffix->operand.name))
-       return(&suffix->operand);
-      suffix = suffix->next;
-    }
-  return NULL;
-}
+#undef DEF
+};
 
-int
-arc_get_noshortcut_flag (void)
-{
-  return ARC_REGISTER_NOSHORT_CUT;
-}
+const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);

diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
new file mode 100644 (file)
index 0000000..b2060c8
--- /dev/null
+++ b/opcodes/arc-regs.h
@@ -0,0 +1,403 @@
+/* ARC Auxiliary register definitions
+   Copyright (C) 2015 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+DEF (0x0,   STATUS)
+DEF (0x1,   SEMAPHORE)
+DEF (0x2,   LP_START)
+DEF (0x3,   LP_END)
+DEF (0x4,   IDENTITY)
+DEF (0x5,   DEBUG)
+DEF (0x6,   PC)
+DEF (0x7,   ADCR)
+DEF (0x8,   APCR)
+DEF (0x9,   ACR)
+DEF (0xA,   STATUS32)
+DEF (0xB,   STATUS32_L1)
+DEF (0xC,   STATUS32_L2)
+DEF (0xF,   BPU_FLUSH)
+DEF (0x10,  IVIC)
+DEF (0x10,  IC_IVIC)
+DEF (0x11,  CHE_MODE)
+DEF (0x11,  IC_CTRL)
+DEF (0x12,  MULHI)
+DEF (0x13,  LOCKLINE)
+DEF (0x13,  IC_LIL)
+DEF (0x14,  DMC_CODE_RAM)
+DEF (0x15,  TAG_ADDR_MASK)
+DEF (0x16,  TAG_DATA_MASK)
+DEF (0x17,  LINE_LENGTH_MASK)
+DEF (0x18,  AUX_LDST_RAM)
+DEF (0x18,  AUX_DCCM)
+DEF (0x19,  UNLOCKLINE)
+DEF (0x19,  IC_IVIL)
+DEF (0x1A,  IC_RAM_ADDRESS)
+DEF (0x1A,  IC_RAM_ADDRESS)
+DEF (0x1B,  IC_TAG)
+DEF (0x1B,  IC_TAG)
+DEF (0x1C,  IC_WP)
+DEF (0x1C,  IC_WP)
+DEF (0x1D,  IC_DATA)
+DEF (0x1D,  IC_DATA)
+DEF (0x20,  SRAM_SEQ)
+DEF (0x21,  COUNT0)
+DEF (0x22,  CONTROL0)
+DEF (0x22,  CONTROL0)
+DEF (0x23,  LIMIT0)
+DEF (0x24,  PCPORT)
+DEF (0x25,  INT_VECTOR_BASE)
+DEF (0x26,  AUX_VBFDW_MODE)
+DEF (0x26,  JLI_BASE)
+DEF (0x27,  AUX_VBFDW_BM0)
+DEF (0x28,  AUX_VBFDW_BM1)
+DEF (0x29,  AUX_VBFDW_ACCU)
+DEF (0x2A,  AUX_VBFDW_OFST)
+DEF (0x2B,  AUX_VBFDW_INTSTAT)
+DEF (0x2C,  AX2 (A4))
+DEF (0x2C,  AUX_XMAC0_24)
+DEF (0x2D,  AY2 (A4))
+DEF (0x2D,  AUX_XMAC1_24)
+DEF (0x2E,  MX2 (A4))
+DEF (0x2E,  AUX_XMAC2_24)
+DEF (0x2F,  MY2 (A4))
+DEF (0x2F,  AUX_FBF_STORE_16)
+DEF (0x30,  AX0)
+DEF (0x31,  AX1)
+DEF (0x32,  AY0 (A4))
+DEF (0x32,  AUX_CRC_POLY)
+DEF (0x33,  AY1 (A4))
+DEF (0x33,  AUX_CRC_MODE)
+DEF (0x34,  MX0)
+DEF (0x35,  MX1)
+DEF (0x36,  MY0)
+DEF (0x37,  MY1)
+DEF (0x38,  XYCONFIG)
+DEF (0x39,  SCRATCH_A)
+DEF (0x3A,  BURSTSYS)
+DEF (0x3A,  TSCH)
+DEF (0x3B,  BURSTXYM)
+DEF (0x3C,  BURSTSZ)
+DEF (0x3D,  BURSTVAL)
+DEF (0x40,  XTP_NEWVAL)
+DEF (0x41,  AUX_MACMODE)
+DEF (0x42,  LSP_NEWVAL)
+DEF (0x43,  AUX_IRQ_LV12)
+DEF (0x44,  AUX_XMAC0)
+DEF (0x45,  AUX_XMAC1)
+DEF (0x46,  AUX_XMAC2)
+DEF (0x47,  DC_IVDC)
+DEF (0x48,  DC_CTRL)
+DEF (0x49,  DC_LDL)
+DEF (0x4A,  DC_IVDL)
+DEF (0x4B,  DC_FLSH)
+DEF (0x4C,  DC_FLDL)
+DEF (0x50,  HEXDATA)
+DEF (0x51,  HEXCTRL)
+DEF (0x52,  LED)
+DEF (0x53,  LCDINSTR (A4))
+DEF (0x54,  LCDDATA (A4))
+DEF (0x55,  LCDSTAT (A4))
+DEF (0x56,  DILSTAT)
+DEF (0x57,  SWSTAT)
+DEF (0x58,  DC_RAM_ADDR)
+DEF (0x58,  DC_RAM_ADDR)
+DEF (0x59,  DC_TAG)
+DEF (0x59,  DC_TAG)
+DEF (0x5A,  DC_WP)
+DEF (0x5B,  DC_DATA)
+DEF (0x61,  DCCM_BASE_BUILD)
+DEF (0x62,  CRC_BUILD)
+DEF (0x63,  BTA_LINK_BUILD)
+DEF (0x64,  VBFDW_BUILD)
+DEF (0x65,  EA_BUILD)
+DEF (0x66,  DATASPACE)
+DEF (0x67,  MEMSUBSYS)
+DEF (0x68,  VECBASE_AC_BUILD)
+DEF (0x69,  P_BASE_ADDR)
+DEF (0x6A,  DATA_UNCACHED_BUILD)
+DEF (0x6B,  FP_BUILD)
+DEF (0x6C,  DPFP_BUILD)
+DEF (0x6D,  MPU_BUILD)
+DEF (0x6E,  RF_BUILD)
+DEF (0x6F,  MMU_BUILD)
+DEF (0x70,  AA2_BUILD)
+DEF (0x71,  VECBASE_BUILD)
+DEF (0x72,  D_CACHE_BUILD)
+DEF (0x73,  MADI_BUILD)
+DEF (0x74,  DCCM_BUILD)
+DEF (0x75,  TIMER_BUILD)
+DEF (0x76,  AP_BUILD)
+DEF (0x77,  I_CACHE_BUILD)
+DEF (0x78,  ICCM_BUILD)
+DEF (0x79,  DSPRAM_BUILD)
+DEF (0x7A,  MAC_BUILD)
+DEF (0x7B,  MULTIPLY_BUILD)
+DEF (0x7C,  SWAP_BUILD)
+DEF (0x7D,  NORM_BUILD)
+DEF (0x7E,  MINMAX_BUILD)
+DEF (0x7F,  BARREL_BUILD)
+DEF (0x80,  AX0)
+DEF (0x81,  AX1)
+DEF (0x82,  AX2)
+DEF (0x83,  AX3)
+DEF (0x84,  AY0)
+DEF (0x85,  AY1)
+DEF (0x86,  AY2)
+DEF (0x87,  AY3)
+DEF (0x88,  MX00)
+DEF (0x89,  MX01)
+DEF (0x8A,  MX10)
+DEF (0x8B,  MX11)
+DEF (0x8C,  MX20)
+DEF (0x8D,  MX21)
+DEF (0x8E,  MX30)
+DEF (0x8F,  MX31)
+DEF (0x90,  MY00)
+DEF (0x91,  MY01)
+DEF (0x92,  MY10)
+DEF (0x93,  MY11)
+DEF (0x94,  MY20)
+DEF (0x95,  MY21)
+DEF (0x96,  MY30)
+DEF (0x97,  MY31)
+DEF (0x98,  XYCONFIG)
+DEF (0x99,  BURSTSYS)
+DEF (0x9A,  BURSTXYM)
+DEF (0x9B,  BURSTSZ)
+DEF (0x9C,  BURSTVAL)
+DEF (0x9D,  XYLSBASEX)
+DEF (0x9E,  XYLSBASEY)
+DEF (0x9F,  AUX_XMACLW_H)
+DEF (0xA0,  AUX_XMACLW_L)
+DEF (0xA1,  SE_CTRL)
+DEF (0xA2,  SE_STAT)
+DEF (0xA3,  SE_ERR)
+DEF (0xA4,  SE_EADR)
+DEF (0xA5,  SE_SPC)
+DEF (0xA6,  SDM_BASE)
+DEF (0xA7,  SCM_BASE)
+DEF (0xA8,  SE_DBG_CTRL)
+DEF (0xA9,  SE_DBG_DATA0)
+DEF (0xAA,  SE_DBG_DATA1)
+DEF (0xAB,  SE_DBG_DATA2)
+DEF (0xAC,  SE_DBG_DATA3)
+DEF (0xAD,  SE_WATCH)
+DEF (0xC0,  BPU_BUILD)
+DEF (0xC1,  ARC600_BUILD_CONFIG)
+DEF (0xC2,  ISA_CONFIG)
+DEF (0xF4,  HWP_BUILD)
+DEF (0xF5,  PCT_BUILD)
+DEF (0xF6,  CC_BUILD)
+DEF (0xF7,  PM_BCR)
+DEF (0xF8,  SCQ_SWITCH_BUILD)
+DEF (0xF9,  VRAPTOR_BUILD)
+DEF (0xFA,  DMA_CONFIG)
+DEF (0xFB,  SIMD_CONFIG)
+DEF (0xFC,  VLC_BUILD)
+DEF (0xFD,  SIMD_DMA_BUILD)
+DEF (0xFE,  IFETCH_QUEUE_BUILD)
+DEF (0xFF,  SMART_BUILD)
+DEF (0x100, COUNT1)
+DEF (0x101, CONTROL1)
+DEF (0x101, CONTROL1)
+DEF (0x102, LIMIT1)
+DEF (0x103, TIMER_XX)
+DEF (0x120, ARCANGEL_PERIPH_XX)
+DEF (0x140, PERIPH_XX)
+DEF (0x200, AUX_IRQ_LEV)
+DEF (0x201, AUX_IRQ_HINT)
+DEF (0x202, AUX_INTER_CORE_INTERRUPT)
+DEF (0x210, AES_AUX_0)
+DEF (0x211, AES_AUX_1)
+DEF (0x212, AES_AUX_2)
+DEF (0x213, AES_CRYPT_MODE)
+DEF (0x214, AES_AUXS)
+DEF (0x215, AES_AUXI)
+DEF (0x216, AES_AUX_3)
+DEF (0x217, AES_AUX_4)
+DEF (0x218, ARITH_CTL_AUX)
+DEF (0x219, DES_AUX)
+DEF (0x220, AP_AMV0)
+DEF (0x221, AP_AMM0)
+DEF (0x222, AP_AC0)
+DEF (0x223, AP_AMV1)
+DEF (0x224, AP_AMM1)
+DEF (0x225, AP_AC1)
+DEF (0x226, AP_AMV2)
+DEF (0x227, AP_AMM2)
+DEF (0x228, AP_AC2)
+DEF (0x229, AP_AMV3)
+DEF (0x22A, AP_AMM3)
+DEF (0x22B, AP_AC3)
+DEF (0x22C, AP_AMV4)
+DEF (0x22D, AP_AMM4)
+DEF (0x22E, AP_AC4)
+DEF (0x22F, AP_AMV5)
+DEF (0x230, AP_AMM5)
+DEF (0x231, AP_AC5)
+DEF (0x232, AP_AMV6)
+DEF (0x233, AP_AMM6)
+DEF (0x234, AP_AC6)
+DEF (0x235, AP_AMV7)
+DEF (0x236, AP_AMM7)
+DEF (0x237, AP_AC7)
+DEF (0x240, CC_*)
+DEF (0x250, PCT_COUNT*)
+DEF (0x260, PCT_SNAP*)
+DEF (0x270, PCT_CONFIG*)
+DEF (0x278, PCT_CONTROL)
+DEF (0x279, PCT_BANK)
+DEF (0x300, FP_STATUS)
+DEF (0x300, RTT (A5 - A4))
+DEF (0x301, AUX_DPFP1L)
+DEF (0x301, RTT (A5 - A4))
+DEF (0x302, AUX_DPFP1H)
+DEF (0x302, RTT (A5 - A4))
+DEF (0x303, AUX_DPFP2L)
+DEF (0x303, RTT (A5 - A4))
+DEF (0x304, AUX_DPFP2H)
+DEF (0x304, RTT (A5 - A4))
+DEF (0x305, DPFP_STATUS)
+DEF (0x305, RTT (A5 - A4))
+DEF (0x306, RTT)
+DEF (0x400, ERET)
+DEF (0x401, ERBTA)
+DEF (0x402, ERSTATUS)
+DEF (0x403, ECR)
+DEF (0x404, EFA)
+DEF (0x405, TLBPD0)
+DEF (0x406, TLBPD1)
+DEF (0x407, TLBIndex)
+DEF (0x408, TLBCommand)
+DEF (0x409, PID)
+DEF (0x409, MPUEN)
+DEF (0x40A, ICAUSE1)
+DEF (0x40B, ICAUSE2)
+DEF (0x40C, AUX_IENABLE)
+DEF (0x40D, AUX_ITRIGGER)
+DEF (0x410, XPU)
+DEF (0x412, BTA)
+DEF (0x413, BTA_L1)
+DEF (0x414, BTA_L2)
+DEF (0x415, AUX_IRQ_PULSE_CANCEL)
+DEF (0x416, AUX_IRQ_PENDING)
+DEF (0x418, SCRATCH_DATA0)
+DEF (0x420, MPUIC)
+DEF (0x421, MPUFA)
+DEF (0x422, MPURDB0)
+DEF (0x423, MPURDP0)
+DEF (0x424, MPURDB1)
+DEF (0x425, MPURDP1)
+DEF (0x426, MPURDB2)
+DEF (0x427, MPURDP2)
+DEF (0x428, MPURDB3)
+DEF (0x429, MPURDP3)
+DEF (0x42A, MPURDB4)
+DEF (0x42B, MPURDP4)
+DEF (0x42C, MPURDB5)
+DEF (0x42D, MPURDP5)
+DEF (0x42E, MPURDB6)
+DEF (0x42F, MPURDP6)
+DEF (0x430, MPURDB7)
+DEF (0x431, MPURDP7)
+DEF (0x432, MPURDB8)
+DEF (0x433, MPURDP8)
+DEF (0x434, MPURDB9)
+DEF (0x435, MPURDP9)
+DEF (0x436, MPURDB10)
+DEF (0x437, MPURDP10)
+DEF (0x438, MPURDB11)
+DEF (0x439, MPURDP11)
+DEF (0x43A, MPURDB12)
+DEF (0x43B, MPURDP12)
+DEF (0x43C, MPURDB13)
+DEF (0x43D, MPURDP13)
+DEF (0x43E, MPURDB14)
+DEF (0x43F, MPURDP14)
+DEF (0x440, MPURDB15)
+DEF (0x441, MPURDP15)
+DEF (0x44F, EIA_FLAGS)
+DEF (0x450, PM_STATUS)
+DEF (0x451, WAKE)
+DEF (0x452, DVFS_PERFORMANCE)
+DEF (0x453, PWR_CTRL)
+DEF (0x500, AUX_VLC_BUF_IDX)
+DEF (0x501, AUX_VLC_READ_BUF)
+DEF (0x502, AUX_VLC_VALID_BITS)
+DEF (0x503, AUX_VLC_BUF_IN)
+DEF (0x504, AUX_VLC_BUF_FREE)
+DEF (0x505, AUX_VLC_IBUF_STATUS)
+DEF (0x506, AUX_VLC_SETUP)
+DEF (0x507, AUX_VLC_BITS)
+DEF (0x508, AUX_VLC_TABLE)
+DEF (0x509, AUX_VLC_GET_SYMBOL)
+DEF (0x50A, AUX_VLC_READ_SYMBOL)
+DEF (0x510, AUX_UCAVLC_SETUP)
+DEF (0x511, AUX_UCAVLC_STATE)
+DEF (0x512, AUX_CAVLC_ZERO_LEFT)
+DEF (0x514, AUX_UVLC_I_STATE)
+DEF (0x51C, AUX_VLC_DMA_PTR)
+DEF (0x51D, AUX_VLC_DMA_END)
+DEF (0x51E, AUX_VLC_DMA_ESC)
+DEF (0x51F, AUX_VLC_DMA_CTRL)
+DEF (0x520, AUX_VLC_GET_0BIT)
+DEF (0x521, AUX_VLC_GET_1BIT)
+DEF (0x522, AUX_VLC_GET_2BIT)
+DEF (0x523, AUX_VLC_GET_3BIT)
+DEF (0x524, AUX_VLC_GET_4BIT)
+DEF (0x525, AUX_VLC_GET_5BIT)
+DEF (0x526, AUX_VLC_GET_6BIT)
+DEF (0x527, AUX_VLC_GET_7BIT)
+DEF (0x528, AUX_VLC_GET_8BIT)
+DEF (0x529, AUX_VLC_GET_9BIT)
+DEF (0x52A, AUX_VLC_GET_10BIT)
+DEF (0x52B, AUX_VLC_GET_11BIT)
+DEF (0x52C, AUX_VLC_GET_12BIT)
+DEF (0x52D, AUX_VLC_GET_13BIT)
+DEF (0x52E, AUX_VLC_GET_14BIT)
+DEF (0x52F, AUX_VLC_GET_15BIT)
+DEF (0x530, AUX_VLC_GET_16BIT)
+DEF (0x531, AUX_VLC_GET_17BIT)
+DEF (0x532, AUX_VLC_GET_18BIT)
+DEF (0x533, AUX_VLC_GET_19BIT)
+DEF (0x534, AUX_VLC_GET_20BIT)
+DEF (0x535, AUX_VLC_GET_21BIT)
+DEF (0x536, AUX_VLC_GET_22BIT)
+DEF (0x537, AUX_VLC_GET_23BIT)
+DEF (0x538, AUX_VLC_GET_24BIT)
+DEF (0x539, AUX_VLC_GET_25BIT)
+DEF (0x53A, AUX_VLC_GET_26BIT)
+DEF (0x53B, AUX_VLC_GET_27BIT)
+DEF (0x53C, AUX_VLC_GET_28BIT)
+DEF (0x53D, AUX_VLC_GET_29BIT)
+DEF (0x53E, AUX_VLC_GET_30BIT)
+DEF (0x53F, AUX_VLC_GET_31BIT)
+DEF (0x540, AUX_CABAC_CTRL)
+DEF (0x541, AUX_CABAC_CTX_STATE)
+DEF (0x542, AUX_CABAC_COD_PARAM)
+DEF (0x543, AUX_CABAC_MISC0)
+DEF (0x544, AUX_CABAC_MISC1)
+DEF (0x545, AUX_CABAC_MISC2)
+DEF (0x600, ARC600_BUILD_CONFIG)
+DEF (0x700, SMART_CONTROL)
+DEF (0x701, SMART_DATA_0)
+DEF (0x701, SMART_DATA_1)
+DEF (0x701, SMART_DATA_2)
+DEF (0x701, SMART_DATA_3)

diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
new file mode 100644 (file)
index 0000000..78e5b51
--- /dev/null
+++ b/opcodes/arc-tbl.h
@@ -0,0 +1,18198 @@
+/* ARC instruction defintions.
+   Copyright (C) 1994-2015 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001.  */
+{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* abs<.f> 0,c 0010011000101111F111CCCCCC001001.  */
+{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001.  */
+{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001.  */
+{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abs<.f> b,limm 00100bbb00101111FBBB111110001001.  */
+{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* abs<.f> 0,limm 0010011000101111F111111110001001.  */
+{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* abss<.f> b,c 00101bbb00101111FBBBCCCCCC000101.  */
+{ "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* abss<.f> 0,c 0010111000101111F111CCCCCC000101.  */
+{ "abss", 0x2E2F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* abss<.f> b,u6 00101bbb01101111FBBBuuuuuu000101.  */
+{ "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abss<.f> 0,u6 0010111001101111F111uuuuuu000101.  */
+{ "abss", 0x2E6F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abss<.f> b,limm 00101bbb00101111FBBB111110000101.  */
+{ "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* abss<.f> 0,limm 0010111000101111F111111110000101.  */
+{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100.  */
+{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }},
+
+/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100.  */
+{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100.  */
+{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100.  */
+{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100.  */
+{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }},
+
+/* abssh<.f> 0,limm 0010111000101111F111111110000100.  */
+{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* abssw<.f> b,c 00101bbb00101111FBBBCCCCCC000100.  */
+{ "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* abssw<.f> 0,c 0010111000101111F111CCCCCC000100.  */
+{ "abssw", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* abssw<.f> b,u6 00101bbb01101111FBBBuuuuuu000100.  */
+{ "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abssw<.f> 0,u6 0010111001101111F111uuuuuu000100.  */
+{ "abssw", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abssw<.f> b,limm 00101bbb00101111FBBB111110000100.  */
+{ "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* abssw<.f> 0,limm 0010111000101111F111111110000100.  */
+{ "abssw", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* abs_s b,c 01111bbbccc10001.  */
+{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* acm<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA.  */
+{ "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* acm<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ.  */
+{ "acm", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* acm<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA.  */
+{ "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* acm<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ.  */
+{ "acm", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* acm<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS.  */
+{ "acm", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* acm<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA.  */
+{ "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* acm<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA.  */
+{ "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* acm<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ.  */
+{ "acm", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA.  */
+{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110.  */
+{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ.  */
+{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA.  */
+{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110.  */
+{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ.  */
+{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS.  */
+{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA.  */
+{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA.  */
+{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110.  */
+{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110.  */
+{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ.  */
+{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ.  */
+{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA.  */
+{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110.  */
+{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ.  */
+{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS.  */
+{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA.  */
+{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adc<.f> 0,limm,limm 0010011000000001F111111110111110.  */
+{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ.  */
+{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA.  */
+{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110.  */
+{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ.  */
+{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA.  */
+{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110.  */
+{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.  */
+{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS.  */
+{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA.  */
+{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA.  */
+{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110.  */
+{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110.  */
+{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ.  */
+{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ.  */
+{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA.  */
+{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110.  */
+{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ.  */
+{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS.  */
+{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA.  */
+{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add<.f> 0,limm,limm 0010011000000000F111111110111110.  */
+{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ.  */
+{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA.  */
+{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110.  */
+{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ.  */
+{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA.  */
+{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110.  */
+{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ.  */
+{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS.  */
+{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA.  */
+{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA.  */
+{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110.  */
+{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110.  */
+{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ.  */
+{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ.  */
+{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA.  */
+{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110.  */
+{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ.  */
+{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS.  */
+{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA.  */
+{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add1<.f> 0,limm,limm 0010011000010100F111111110111110.  */
+{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ.  */
+{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1_s b,b,c 01111bbbccc10100.  */
+{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA.  */
+{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110.  */
+{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ.  */
+{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA.  */
+{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110.  */
+{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ.  */
+{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS.  */
+{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA.  */
+{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA.  */
+{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110.  */
+{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110.  */
+{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ.  */
+{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ.  */
+{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA.  */
+{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110.  */
+{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ.  */
+{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS.  */
+{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA.  */
+{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add2<.f> 0,limm,limm 0010011000010101F111111110111110.  */
+{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ.  */
+{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add2_s b,b,c 01111bbbccc10101.  */
+{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA.  */
+{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110.  */
+{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ.  */
+{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA.  */
+{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110.  */
+{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ.  */
+{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS.  */
+{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA.  */
+{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA.  */
+{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110.  */
+{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110.  */
+{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ.  */
+{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ.  */
+{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA.  */
+{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110.  */
+{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ.  */
+{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS.  */
+{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA.  */
+{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add3<.f> 0,limm,limm 0010011000010110F111111110111110.  */
+{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ.  */
+{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add3_s b,b,c 01111bbbccc10110.  */
+{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* addqbs<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA.  */
+{ "addqbs", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* addqbs<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ.  */
+{ "addqbs", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* addqbs<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA.  */
+{ "addqbs", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* addqbs<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ.  */
+{ "addqbs", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* addqbs<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS.  */
+{ "addqbs", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* addqbs<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA.  */
+{ "addqbs", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* addqbs<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA.  */
+{ "addqbs", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* addqbs<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ.  */
+{ "addqbs", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adds<.f> a,b,c 00101bbb00000110FBBBCCCCCCAAAAAA.  */
+{ "adds", 0x28060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adds<.f> 0,b,c 00101bbb00000110FBBBCCCCCC111110.  */
+{ "adds", 0x2806003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adds<.f><.cc> b,b,c 00101bbb11000110FBBBCCCCCC0QQQQQ.  */
+{ "adds", 0x28C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adds<.f> a,b,u6 00101bbb01000110FBBBuuuuuuAAAAAA.  */
+{ "adds", 0x28460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adds<.f> 0,b,u6 00101bbb01000110FBBBuuuuuu111110.  */
+{ "adds", 0x2846003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adds<.f><.cc> b,b,u6 00101bbb11000110FBBBuuuuuu1QQQQQ.  */
+{ "adds", 0x28C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adds<.f> b,b,s12 00101bbb10000110FBBBssssssSSSSSS.  */
+{ "adds", 0x28860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adds<.f> a,limm,c 0010111000000110F111CCCCCCAAAAAA.  */
+{ "adds", 0x2E067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adds<.f> a,b,limm 00101bbb00000110FBBB111110AAAAAA.  */
+{ "adds", 0x28060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adds<.f> 0,limm,c 0010111000000110F111CCCCCC111110.  */
+{ "adds", 0x2E06703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adds<.f> 0,b,limm 00101bbb00000110FBBB111110111110.  */
+{ "adds", 0x28060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adds<.f><.cc> b,b,limm 00101bbb11000110FBBB1111100QQQQQ.  */
+{ "adds", 0x28C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adds<.f><.cc> 0,limm,c 0010111011000110F111CCCCCC0QQQQQ.  */
+{ "adds", 0x2EC67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adds<.f> a,limm,u6 0010111001000110F111uuuuuuAAAAAA.  */
+{ "adds", 0x2E467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adds<.f> 0,limm,u6 0010111001000110F111uuuuuu111110.  */
+{ "adds", 0x2E46703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adds<.f><.cc> 0,limm,u6 0010111011000110F111uuuuuu1QQQQQ.  */
+{ "adds", 0x2EC67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adds<.f> 0,limm,s12 0010111010000110F111ssssssSSSSSS.  */
+{ "adds", 0x2E867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adds<.f> a,limm,limm 0010111000000110F111111110AAAAAA.  */
+{ "adds", 0x2E067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adds<.f> 0,limm,limm 0010111000000110F111111110111110.  */
+{ "adds", 0x2E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adds<.f><.cc> 0,limm,limm 0010111011000110F1111111100QQQQQ.  */
+{ "adds", 0x2EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* addsdw<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA.  */
+{ "addsdw", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* addsdw<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110.  */
+{ "addsdw", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* addsdw<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ.  */
+{ "addsdw", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* addsdw<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA.  */
+{ "addsdw", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* addsdw<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110.  */
+{ "addsdw", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* addsdw<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ.  */
+{ "addsdw", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* addsdw<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS.  */
+{ "addsdw", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* addsdw<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA.  */
+{ "addsdw", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* addsdw<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA.  */
+{ "addsdw", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* addsdw<.f> 0,limm,c 0010111000101000F111CCCCCC111110.  */
+{ "addsdw", 0x2E28703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* addsdw<.f> 0,b,limm 00101bbb00101000FBBB111110111110.  */
+{ "addsdw", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* addsdw<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ.  */
+{ "addsdw", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* addsdw<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ.  */
+{ "addsdw", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* addsdw<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA.  */
+{ "addsdw", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* addsdw<.f> 0,limm,u6 0010111001101000F111uuuuuu111110.  */
+{ "addsdw", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* addsdw<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ.  */
+{ "addsdw", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* addsdw<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS.  */
+{ "addsdw", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* addsdw<.f> a,limm,limm 0010111000101000F111111110AAAAAA.  */
+{ "addsdw", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* addsdw<.f> 0,limm,limm 0010111000101000F111111110111110.  */
+{ "addsdw", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* addsdw<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ.  */
+{ "addsdw", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add_s a,b,c 01100bbbccc11aaa.  */
+{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA_S, RB_S, RC_S }, { 0 }},
+
+/* add_s b,b,h 01110bbbhhh00HHH.  */
+{ "add_s", 0x00007000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RB_Sdup, R6H }, { 0 }},
+
+/* add_s b,b,h 01110bbbhhh000HH.  */
+{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RH_S }, { 0 }},
+
+/* add_s h,h,s3 01110ssshhh001HH.  */
+{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RH_S, RH_Sdup, SIMM3_5_S }, { 0 }},
+
+/* add_s c,b,u3 01101bbbccc00uuu.  */
+{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* add_s R0,b,u6 01001bbb0UUU1uuu.  */
+{ "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { R0_S, RB_S, UIMM6_13_S }, { 0 }},
+
+/* add_s R1,b,u6 01001bbb1UUU1uuu.  */
+{ "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { R1_S, RB_S, UIMM6_13_S }, { 0 }},
+
+/* add_s b,sp,u7 11000bbb100uuuuu.  */
+{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
+
+/* add_s b,b,u7 11100bbb0uuuuuuu.  */
+{ "add_s", 0x0000E000, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, UIMM7_9_S }, { 0 }},
+
+/* add_s SP,SP,u7 11000000101uuuuu.  */
+{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+
+/* add_s R0,GP,s11 1100111sssssssss.  */
+{ "add_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { R0_S, GP_S, SIMM11_A32_7_S }, { 0 }},
+
+/* add_s b,b,limm 01110bbb11000111.  */
+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 }},
+
+/* add_s b,b,limm 01110bbb11000011.  */
+{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 }},
+
+/* add_s 0,limm,s3 01110sss11000111.  */
+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 }},
+
+/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR.  */
+{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ.  */
+{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR.  */
+{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ.  */
+{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS.  */
+{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aex limm,c 0010011000100111R111CCCCCCRRRRRR.  */
+{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aex b,limm 00100bbb00100111RBBB111110RRRRRR.  */
+{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ.  */
+{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ.  */
+{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC }},
+
+/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR.  */
+{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ.  */
+{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aex limm,s12 0010011010100111R111ssssssSSSSSS.  */
+{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aex limm,limm 0010011000100111R111111110RRRRRR.  */
+{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ.  */
+{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_CC }},
+
+/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA.  */
+{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110.  */
+{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ.  */
+{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA.  */
+{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110.  */
+{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ.  */
+{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS.  */
+{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA.  */
+{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA.  */
+{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110.  */
+{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110.  */
+{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ.  */
+{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ.  */
+{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA.  */
+{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110.  */
+{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ.  */
+{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS.  */
+{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA.  */
+{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* and<.f> 0,limm,limm 0010011000000100F111111110111110.  */
+{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ.  */
+{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* and_s b,b,c 01111bbbccc00100.  */
+{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000.  */
+{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* asl<.f> 0,c 0010011000101111F111CCCCCC000000.  */
+{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA.  */
+{ "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110.  */
+{ "asl", 0x2800003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ.  */
+{ "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000.  */
+{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000.  */
+{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA.  */
+{ "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110.  */
+{ "asl", 0x2840003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ.  */
+{ "asl", 0x28C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS.  */
+{ "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asl<.f> b,limm 00100bbb00101111FBBB111110000000.  */
+{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* asl<.f> 0,limm 0010011000101111F111111110000000.  */
+{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA.  */
+{ "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA.  */
+{ "asl", 0x28000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110.  */
+{ "asl", 0x2E00703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110.  */
+{ "asl", 0x28000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ.  */
+{ "asl", 0x28C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ.  */
+{ "asl", 0x2EC07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA.  */
+{ "asl", 0x2E407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110.  */
+{ "asl", 0x2E40703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ.  */
+{ "asl", 0x2EC07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS.  */
+{ "asl", 0x2E807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA.  */
+{ "asl", 0x2E007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asl<.f> 0,limm,limm 0010111000000000F111111110111110.  */
+{ "asl", 0x2E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ.  */
+{ "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* aslacc c 00101000001011110000CCCCCC111111.  */
+{ "aslacc", 0x282F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }},
+
+/* aslacc u6 00101000011011110000uuuuuu111111.  */
+{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* asldw<.f> a,b,c 00101bbb00100001FBBBCCCCCCAAAAAA.  */
+{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* asldw<.f> 0,b,c 00101bbb00100001FBBBCCCCCC111110.  */
+{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asldw<.f><.cc> b,b,c 00101bbb11100001FBBBCCCCCC0QQQQQ.  */
+{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asldw<.f> a,b,u6 00101bbb01100001FBBBuuuuuuAAAAAA.  */
+{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asldw<.f> 0,b,u6 00101bbb01100001FBBBuuuuuu111110.  */
+{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asldw<.f><.cc> b,b,u6 00101bbb11100001FBBBuuuuuu1QQQQQ.  */
+{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asldw<.f> b,b,s12 00101bbb10100001FBBBssssssSSSSSS.  */
+{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asldw<.f> a,limm,c 0010111000100001F111CCCCCCAAAAAA.  */
+{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asldw<.f> a,b,limm 00101bbb00100001FBBB111110AAAAAA.  */
+{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asldw<.f> 0,limm,c 0010111000100001F111CCCCCC111110.  */
+{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asldw<.f> 0,b,limm 00101bbb00100001FBBB111110111110.  */
+{ "asldw", 0x28210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asldw<.f><.cc> 0,limm,c 0010111011100001F111CCCCCC0QQQQQ.  */
+{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asldw<.f><.cc> b,b,limm 00101bbb11100001FBBB1111100QQQQQ.  */
+{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asldw<.f> a,limm,u6 0010111001100001F111uuuuuuAAAAAA.  */
+{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asldw<.f> 0,limm,u6 0010111001100001F111uuuuuu111110.  */
+{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asldw<.f><.cc> 0,limm,u6 0010111011100001F111uuuuuu1QQQQQ.  */
+{ "asldw", 0x2EE17020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asldw<.f> 0,limm,s12 0010111010100001F111ssssssSSSSSS.  */
+{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asldw<.f> a,limm,limm 0010111000100001F111111110AAAAAA.  */
+{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asldw<.f> 0,limm,limm 0010111000100001F111111110111110.  */
+{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asldw<.f><.cc> 0,limm,limm 0010111011100001F1111111100QQQQQ.  */
+{ "asldw", 0x2EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asls<.f> a,b,c 00101bbb00001010FBBBCCCCCCAAAAAA.  */
+{ "asls", 0x280A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asls<.f> 0,b,c 00101bbb00001010FBBBCCCCCC111110.  */
+{ "asls", 0x280A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asls<.f><.cc> b,b,c 00101bbb11001010FBBBCCCCCC0QQQQQ.  */
+{ "asls", 0x28CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asls<.f> a,b,u6 00101bbb01001010FBBBuuuuuuAAAAAA.  */
+{ "asls", 0x284A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asls<.f> 0,b,u6 00101bbb01001010FBBBuuuuuu111110.  */
+{ "asls", 0x284A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asls<.f><.cc> b,b,u6 00101bbb11001010FBBBuuuuuu1QQQQQ.  */
+{ "asls", 0x28CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asls<.f> b,b,s12 00101bbb10001010FBBBssssssSSSSSS.  */
+{ "asls", 0x288A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asls<.f> a,limm,c 0010111000001010F111CCCCCCAAAAAA.  */
+{ "asls", 0x2E0A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asls<.f> a,b,limm 00101bbb00001010FBBB111110AAAAAA.  */
+{ "asls", 0x280A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asls<.f> 0,limm,c 0010111000001010F111CCCCCC111110.  */
+{ "asls", 0x2E0A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asls<.f> 0,b,limm 00101bbb00001010FBBB111110111110.  */
+{ "asls", 0x280A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asls<.f><.cc> b,b,limm 00101bbb11001010FBBB1111100QQQQQ.  */
+{ "asls", 0x28CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asls<.f><.cc> 0,limm,c 0010111011001010F111CCCCCC0QQQQQ.  */
+{ "asls", 0x2ECA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asls<.f> a,limm,u6 0010111001001010F111uuuuuuAAAAAA.  */
+{ "asls", 0x2E4A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asls<.f> 0,limm,u6 0010111001001010F111uuuuuu111110.  */
+{ "asls", 0x2E4A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asls<.f><.cc> 0,limm,u6 0010111011001010F111uuuuuu1QQQQQ.  */
+{ "asls", 0x2ECA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asls<.f> 0,limm,s12 0010111010001010F111ssssssSSSSSS.  */
+{ "asls", 0x2E8A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asls<.f> a,limm,limm 0010111000001010F111111110AAAAAA.  */
+{ "asls", 0x2E0A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asls<.f> 0,limm,limm 0010111000001010F111111110111110.  */
+{ "asls", 0x2E0A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asls<.f><.cc> 0,limm,limm 0010111011001010F1111111100QQQQQ.  */
+{ "asls", 0x2ECA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* aslsacc c 00101001001011110000CCCCCC111111.  */
+{ "aslsacc", 0x292F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }},
+
+/* aslsacc u6 00101001011011110000uuuuuu111111.  */
+{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* aslsdw<.f> a,b,c 00101bbb00100100FBBBCCCCCCAAAAAA.  */
+{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* aslsdw<.f> 0,b,c 00101bbb00100100FBBBCCCCCC111110.  */
+{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* aslsdw<.f><.cc> b,b,c 00101bbb11100100FBBBCCCCCC0QQQQQ.  */
+{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* aslsdw<.f> a,b,u6 00101bbb01100100FBBBuuuuuuAAAAAA.  */
+{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* aslsdw<.f> 0,b,u6 00101bbb01100100FBBBuuuuuu111110.  */
+{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* aslsdw<.f><.cc> b,b,u6 00101bbb11100100FBBBuuuuuu1QQQQQ.  */
+{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* aslsdw<.f> b,b,s12 00101bbb10100100FBBBssssssSSSSSS.  */
+{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* aslsdw<.f> a,limm,c 0010111000100100F111CCCCCCAAAAAA.  */
+{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* aslsdw<.f> a,b,limm 00101bbb00100100FBBB111110AAAAAA.  */
+{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* aslsdw<.f> 0,limm,c 0010111000100100F111CCCCCC111110.  */
+{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* aslsdw<.f> 0,b,limm 00101bbb00100100FBBB111110111110.  */
+{ "aslsdw", 0x28240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* aslsdw<.f><.cc> 0,limm,c 0010111011100100F111CCCCCC0QQQQQ.  */
+{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* aslsdw<.f><.cc> b,b,limm 00101bbb11100100FBBB1111100QQQQQ.  */
+{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* aslsdw<.f> a,limm,u6 0010111001100100F111uuuuuuAAAAAA.  */
+{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* aslsdw<.f> 0,limm,u6 0010111001100100F111uuuuuu111110.  */
+{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* aslsdw<.f><.cc> 0,limm,u6 0010111011100100F111uuuuuu1QQQQQ.  */
+{ "aslsdw", 0x2EE47020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* aslsdw<.f> 0,limm,s12 0010111010100100F111ssssssSSSSSS.  */
+{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* aslsdw<.f> a,limm,limm 0010111000100100F111111110AAAAAA.  */
+{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* aslsdw<.f> 0,limm,limm 0010111000100100F111111110111110.  */
+{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* aslsdw<.f><.cc> 0,limm,limm 0010111011100100F1111111100QQQQQ.  */
+{ "aslsdw", 0x2EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asl_s b,c 01111bbbccc11011.  */
+{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* asl_s b,b,c 01111bbbccc11000.  */
+{ "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asl_s c,b,u3 01101bbbccc10uuu.  */
+{ "asl_s", 0x00006810, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* asl_s b,b,u5 10111bbb000uuuuu.  */
+{ "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001.  */
+{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* asr<.f> 0,c 0010011000101111F111CCCCCC000001.  */
+{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA.  */
+{ "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110.  */
+{ "asr", 0x2802003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ.  */
+{ "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001.  */
+{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001.  */
+{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA.  */
+{ "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110.  */
+{ "asr", 0x2842003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ.  */
+{ "asr", 0x28C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS.  */
+{ "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asr<.f> b,limm 00100bbb00101111FBBB111110000001.  */
+{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* asr<.f> 0,limm 0010011000101111F111111110000001.  */
+{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA.  */
+{ "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA.  */
+{ "asr", 0x28020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110.  */
+{ "asr", 0x2E02703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110.  */
+{ "asr", 0x28020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ.  */
+{ "asr", 0x28C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ.  */
+{ "asr", 0x2EC27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA.  */
+{ "asr", 0x2E427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110.  */
+{ "asr", 0x2E42703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ.  */
+{ "asr", 0x2EC27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS.  */
+{ "asr", 0x2E827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA.  */
+{ "asr", 0x2E027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asr<.f> 0,limm,limm 0010111000000010F111111110111110.  */
+{ "asr", 0x2E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ.  */
+{ "asr", 0x2EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100.  */
+{ "asr16", 0x282F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100.  */
+{ "asr16", 0x2E2F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100.  */
+{ "asr16", 0x286F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100.  */
+{ "asr16", 0x2E6F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100.  */
+{ "asr16", 0x282F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* asr16<.f> 0,limm 0010111000101111F111111110001100.  */
+{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101.  */
+{ "asr8", 0x282F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101.  */
+{ "asr8", 0x2E2F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101.  */
+{ "asr8", 0x286F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101.  */
+{ "asr8", 0x2E6F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101.  */
+{ "asr8", 0x282F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* asr8<.f> 0,limm 0010111000101111F111111110001101.  */
+{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* asrdw<.f> a,b,c 00101bbb00100010FBBBCCCCCCAAAAAA.  */
+{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrdw<.f> 0,b,c 00101bbb00100010FBBBCCCCCC111110.  */
+{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrdw<.f><.cc> b,b,c 00101bbb11100010FBBBCCCCCC0QQQQQ.  */
+{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrdw<.f> a,b,u6 00101bbb01100010FBBBuuuuuuAAAAAA.  */
+{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrdw<.f> 0,b,u6 00101bbb01100010FBBBuuuuuu111110.  */
+{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrdw<.f><.cc> b,b,u6 00101bbb11100010FBBBuuuuuu1QQQQQ.  */
+{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrdw<.f> b,b,s12 00101bbb10100010FBBBssssssSSSSSS.  */
+{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrdw<.f> a,limm,c 0010111000100010F111CCCCCCAAAAAA.  */
+{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrdw<.f> a,b,limm 00101bbb00100010FBBB111110AAAAAA.  */
+{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrdw<.f> 0,limm,c 0010111000100010F111CCCCCC111110.  */
+{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrdw<.f> 0,b,limm 00101bbb00100010FBBB111110111110.  */
+{ "asrdw", 0x28220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrdw<.f><.cc> 0,limm,c 0010111011100010F111CCCCCC0QQQQQ.  */
+{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrdw<.f><.cc> b,b,limm 00101bbb11100010FBBB1111100QQQQQ.  */
+{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrdw<.f> a,limm,u6 0010111001100010F111uuuuuuAAAAAA.  */
+{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrdw<.f> 0,limm,u6 0010111001100010F111uuuuuu111110.  */
+{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrdw<.f><.cc> 0,limm,u6 0010111011100010F111uuuuuu1QQQQQ.  */
+{ "asrdw", 0x2EE27020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrdw<.f> 0,limm,s12 0010111010100010F111ssssssSSSSSS.  */
+{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrdw<.f> a,limm,limm 0010111000100010F111111110AAAAAA.  */
+{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrdw<.f> 0,limm,limm 0010111000100010F111111110111110.  */
+{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrdw<.f><.cc> 0,limm,limm 0010111011100010F1111111100QQQQQ.  */
+{ "asrdw", 0x2EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA.  */
+{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110.  */
+{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ.  */
+{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA.  */
+{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110.  */
+{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ.  */
+{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS.  */
+{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA.  */
+{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA.  */
+{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110.  */
+{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110.  */
+{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ.  */
+{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ.  */
+{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA.  */
+{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110.  */
+{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ.  */
+{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS.  */
+{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA.  */
+{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrs<.f> 0,limm,limm 0010111000001011F111111110111110.  */
+{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ.  */
+{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asrsdw<.f> a,b,c 00101bbb00100101FBBBCCCCCCAAAAAA.  */
+{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrsdw<.f> 0,b,c 00101bbb00100101FBBBCCCCCC111110.  */
+{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrsdw<.f><.cc> b,b,c 00101bbb11100101FBBBCCCCCC0QQQQQ.  */
+{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrsdw<.f> a,b,u6 00101bbb01100101FBBBuuuuuuAAAAAA.  */
+{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrsdw<.f> 0,b,u6 00101bbb01100101FBBBuuuuuu111110.  */
+{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrsdw<.f><.cc> b,b,u6 00101bbb11100101FBBBuuuuuu1QQQQQ.  */
+{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrsdw<.f> b,b,s12 00101bbb10100101FBBBssssssSSSSSS.  */
+{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrsdw<.f> a,limm,c 0010111000100101F111CCCCCCAAAAAA.  */
+{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrsdw<.f> a,b,limm 00101bbb00100101FBBB111110AAAAAA.  */
+{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrsdw<.f> 0,limm,c 0010111000100101F111CCCCCC111110.  */
+{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrsdw<.f> 0,b,limm 00101bbb00100101FBBB111110111110.  */
+{ "asrsdw", 0x28250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrsdw<.f><.cc> 0,limm,c 0010111011100101F111CCCCCC0QQQQQ.  */
+{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrsdw<.f><.cc> b,b,limm 00101bbb11100101FBBB1111100QQQQQ.  */
+{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrsdw<.f> a,limm,u6 0010111001100101F111uuuuuuAAAAAA.  */
+{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrsdw<.f> 0,limm,u6 0010111001100101F111uuuuuu111110.  */
+{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrsdw<.f><.cc> 0,limm,u6 0010111011100101F111uuuuuu1QQQQQ.  */
+{ "asrsdw", 0x2EE57020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrsdw<.f> 0,limm,s12 0010111010100101F111ssssssSSSSSS.  */
+{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrsdw<.f> a,limm,limm 0010111000100101F111111110AAAAAA.  */
+{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrsdw<.f> 0,limm,limm 0010111000100101F111111110111110.  */
+{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrsdw<.f><.cc> 0,limm,limm 0010111011100101F1111111100QQQQQ.  */
+{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA.  */
+{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110.  */
+{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ.  */
+{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA.  */
+{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110.  */
+{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ.  */
+{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS.  */
+{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA.  */
+{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA.  */
+{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110.  */
+{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrsr<.f> 0,b,limm 00101bbb00001100FBBB111110111110.  */
+{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ.  */
+{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ.  */
+{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA.  */
+{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110.  */
+{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ.  */
+{ "asrsr", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrsr<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS.  */
+{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA.  */
+{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110.  */
+{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrsr<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ.  */
+{ "asrsr", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asr_s b,c 01111bbbccc11100.  */
+{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* asr_s b,b,c 01111bbbccc11010.  */
+{ "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asr_s c,b,u3 01101bbbccc11uuu.  */
+{ "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* asr_s b,b,u5 10111bbb010uuuuu.  */
+{ "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* avgqb<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA.  */
+{ "avgqb", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* avgqb<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ.  */
+{ "avgqb", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* avgqb<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA.  */
+{ "avgqb", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* avgqb<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ.  */
+{ "avgqb", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* avgqb<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS.  */
+{ "avgqb", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* avgqb<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA.  */
+{ "avgqb", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* avgqb<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA.  */
+{ "avgqb", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* avgqb<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ.  */
+{ "avgqb", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt.  */
+{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }},
+
+/* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ.  */
+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }},
+
+/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110.  */
+{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110.  */
+{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110.  */
+{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110.  */
+{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110.  */
+{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110.  */
+{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110.  */
+{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110.  */
+{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110.  */
+{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110.  */
+{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* bbit0 limm,limm,s9 00001110sssssss1S111111110001110.  */
+{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110.  */
+{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111.  */
+{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111.  */
+{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111.  */
+{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111.  */
+{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111.  */
+{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111.  */
+{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111.  */
+{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111.  */
+{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111.  */
+{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111.  */
+{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* bbit1 limm,limm,s9 00001110sssssss1S111111110001111.  */
+{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111.  */
+{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA.  */
+{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110.  */
+{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ.  */
+{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA.  */
+{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110.  */
+{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ.  */
+{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS.  */
+{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA.  */
+{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA.  */
+{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110.  */
+{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110.  */
+{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ.  */
+{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ.  */
+{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA.  */
+{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110.  */
+{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ.  */
+{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS.  */
+{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA.  */
+{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110.  */
+{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ.  */
+{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bclr_s b,b,u5 10111bbb101uuuuu.  */
+{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* beq_s s10 1111001sssssssss.  */
+{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+
+/* bge_s s7 1111011001ssssss.  */
+{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* bgt_s s7 1111011000ssssss.  */
+{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* bhi_s s7 1111011100ssssss.  */
+{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* bhs_s s7 1111011101ssssss.  */
+{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* bi c 00100RRR001001000RRRCCCCCCRRRRRR.  */
+{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* bi limm 00100RRR001001000RRR111110RRRRRR.  */
+{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA.  */
+{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110.  */
+{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ.  */
+{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA.  */
+{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110.  */
+{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ.  */
+{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS.  */
+{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA.  */
+{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA.  */
+{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110.  */
+{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110.  */
+{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ.  */
+{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ.  */
+{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA.  */
+{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110.  */
+{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ.  */
+{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS.  */
+{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA.  */
+{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bic<.f> 0,limm,limm 0010011000000110F111111110111110.  */
+{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ.  */
+{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bic_s b,b,c 01111bbbccc00110.  */
+{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* bih c 00100RRR001001010RRRCCCCCCRRRRRR.  */
+{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* bih limm 00100RRR001001010RRR111110RRRRRR.  */
+{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt.  */
+{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A32_5 }, { C_D }},
+
+/* bl<.cc><.d> s21 00001sssssssss00SSSSSSSSSSNQQQQQ.  */
+{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }},
+
+/* ble_s s7 1111011011ssssss.  */
+{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* blo_s s7 1111011110ssssss.  */
+{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* bls_s s7 1111011111ssssss.  */
+{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* blt_s s7 1111011010ssssss.  */
+{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+
+/* bl_s s13 11111sssssssssss.  */
+{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }},
+
+/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA.  */
+{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110.  */
+{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ.  */
+{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA.  */
+{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110.  */
+{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ.  */
+{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS.  */
+{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA.  */
+{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA.  */
+{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110.  */
+{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110.  */
+{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ.  */
+{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ.  */
+{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA.  */
+{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110.  */
+{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ.  */
+{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS.  */
+{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA.  */
+{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110.  */
+{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ.  */
+{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA.  */
+{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110.  */
+{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ.  */
+{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA.  */
+{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110.  */
+{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ.  */
+{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS.  */
+{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA.  */
+{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA.  */
+{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110.  */
+{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110.  */
+{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ.  */
+{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ.  */
+{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA.  */
+{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110.  */
+{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ.  */
+{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS.  */
+{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA.  */
+{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110.  */
+{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ.  */
+{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmsk_s b,b,u5 10111bbb110uuuuu.  */
+{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* bne_s s10 1111010sssssssss.  */
+{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+
+/* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000.  */
+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000.  */
+{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000.  */
+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000.  */
+{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* breq b,limm,s9 00001bbbsssssss1SBBB111110000000.  */
+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* breq limm,c,s9 00001110sssssss1S111CCCCCC000000.  */
+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000.  */
+{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000.  */
+{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000.  */
+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000.  */
+{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000.  */
+{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* breq_s b,0,s8 11101bbb0sssssss.  */
+{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011.  */
+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011.  */
+{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011.  */
+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011.  */
+{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brge b,limm,s9 00001bbbsssssss1SBBB111110000011.  */
+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brge limm,c,s9 00001110sssssss1S111CCCCCC000011.  */
+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011.  */
+{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011.  */
+{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011.  */
+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011.  */
+{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011.  */
+{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101.  */
+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101.  */
+{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101.  */
+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101.  */
+{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101.  */
+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101.  */
+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101.  */
+{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101.  */
+{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101.  */
+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101.  */
+{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101.  */
+{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* brk  00100101011011110000000000111111.  */
+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+
+/* brk_s  0111111111111111.  */
+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+
+/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100.  */
+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100.  */
+{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100.  */
+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100.  */
+{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100.  */
+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100.  */
+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100.  */
+{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100.  */
+{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100.  */
+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100.  */
+{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100.  */
+{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010.  */
+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010.  */
+{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010.  */
+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010.  */
+{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010.  */
+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010.  */
+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010.  */
+{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010.  */
+{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010.  */
+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010.  */
+{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010.  */
+{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001.  */
+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001.  */
+{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001.  */
+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001.  */
+{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+
+/* brne b,limm,s9 00001bbbsssssss1SBBB111110000001.  */
+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brne limm,c,s9 00001110sssssss1S111CCCCCC000001.  */
+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001.  */
+{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+
+/* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001.  */
+{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+
+/* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001.  */
+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001.  */
+{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+
+/* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001.  */
+{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+
+/* brne_s b,0,s8 11101bbb1sssssss.  */
+{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA.  */
+{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110.  */
+{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ.  */
+{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA.  */
+{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110.  */
+{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ.  */
+{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS.  */
+{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA.  */
+{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA.  */
+{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110.  */
+{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110.  */
+{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ.  */
+{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ.  */
+{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA.  */
+{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110.  */
+{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ.  */
+{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS.  */
+{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA.  */
+{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bset<.f> 0,limm,limm 0010011000001111F111111110111110.  */
+{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ.  */
+{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bset_s b,b,u5 10111bbb100uuuuu.  */
+{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR.  */
+{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* btst b,c 00100bbb000100011BBBCCCCCC000000.  */
+{ "btst", 0x20118000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ.  */
+{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_CC }},
+
+/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR.  */
+{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* btst b,u6 00100bbb010100011BBBuuuuuu000000.  */
+{ "btst", 0x20518000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ.  */
+{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* btst b,s12 00100bbb100100011BBBssssssSSSSSS.  */
+{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* btst limm,c 00100110000100011111CCCCCCRRRRRR.  */
+{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* btst b,limm 00100bbb000100011BBB111110RRRRRR.  */
+{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* btst limm,c 00100110000100011111CCCCCC000000.  */
+{ "btst", 0x2611F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* btst b,limm 00100bbb000100011BBB111110000000.  */
+{ "btst", 0x20118F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ.  */
+{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_CC }},
+
+/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ.  */
+{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { C_CC }},
+
+/* btst limm,u6 00100110010100011111uuuuuuRRRRRR.  */
+{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* btst limm,u6 00100110010100011111uuuuuu000000.  */
+{ "btst", 0x2651F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ.  */
+{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* btst limm,s12 00100110100100011111ssssssSSSSSS.  */
+{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* btst limm,limm 00100110000100011111111110RRRRRR.  */
+{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* btst limm,limm 00100110000100011111111110000000.  */
+{ "btst", 0x2611FF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ.  */
+{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* btst_s b,u5 10111bbb111uuuuu.  */
+{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, UIMM5_11_S }, { 0 }},
+
+/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA.  */
+{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110.  */
+{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ.  */
+{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA.  */
+{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110.  */
+{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ.  */
+{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS.  */
+{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA.  */
+{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA.  */
+{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110.  */
+{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110.  */
+{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ.  */
+{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ.  */
+{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA.  */
+{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110.  */
+{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ.  */
+{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS.  */
+{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA.  */
+{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110.  */
+{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ.  */
+{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* b_s s10 1111000sssssssss.  */
+{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+
+/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA.  */
+{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110.  */
+{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ.  */
+{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA.  */
+{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110.  */
+{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ.  */
+{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS.  */
+{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA.  */
+{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA.  */
+{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110.  */
+{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cbflyhf0r 0,b,limm 00110bbb000110111BBB111110111110.  */
+{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ.  */
+{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ.  */
+{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA.  */
+{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110.  */
+{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r<.cc> 0,limm,u6 00110110110110111111uuuuuu1QQQQQ.  */
+{ "cbflyhf0r", 0x36DBF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cbflyhf0r 0,limm,s12 00110110100110111111ssssssSSSSSS.  */
+{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA.  */
+{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110.  */
+{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cbflyhf0r<.cc> 0,limm,limm 001101101101101111111111100QQQQQ.  */
+{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001.  */
+{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001.  */
+{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001.  */
+{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001.  */
+{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001.  */
+{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* cbflyhf1r 0,limm 00110110001011110111111110011001.  */
+{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* clamp<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA.  */
+{ "clamp", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* clamp<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ.  */
+{ "clamp", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* clamp<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA.  */
+{ "clamp", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* clamp<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ.  */
+{ "clamp", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* clamp<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS.  */
+{ "clamp", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* clamp<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA.  */
+{ "clamp", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* clamp<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA.  */
+{ "clamp", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* clamp<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ.  */
+{ "clamp", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* clri c 00100111001011110000CCCCCC111111.  */
+{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
+
+/* clri 0 00100111001011110000111110111111.  */
+{ "clri", 0x272F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { ZA }, { 0 }},
+
+/* clri u6 00100111011011110000uuuuuu111111.  */
+{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA.  */
+{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110.  */
+{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ.  */
+{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA.  */
+{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110.  */
+{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ.  */
+{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS.  */
+{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA.  */
+{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA.  */
+{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110.  */
+{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmacchfr 0,b,limm 00110bbb000010011BBB111110111110.  */
+{ "cmacchfr", 0x30098FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmacchfr<.cc> 0,limm,c 00110bbb110010011BBB1111100QQQQQ.  */
+{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmacchfr<.cc> b,b,limm 00110110110010011111CCCCCC0QQQQQ.  */
+{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA.  */
+{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110.  */
+{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchfr<.cc> 0,limm,u6 00110110110010011111uuuuuu1QQQQQ.  */
+{ "cmacchfr", 0x36C9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmacchfr 0,limm,s12 00110110100010011111ssssssSSSSSS.  */
+{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA.  */
+{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchfr 0,limm,limm 00110110000010011111111110111110.  */
+{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchfr<.cc> 0,limm,limm 001101101100100111111111100QQQQQ.  */
+{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA.  */
+{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110.  */
+{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ.  */
+{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA.  */
+{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110.  */
+{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ.  */
+{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS.  */
+{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA.  */
+{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA.  */
+{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110.  */
+{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmacchnfr 0,b,limm 00110bbb000010001BBB111110111110.  */
+{ "cmacchnfr", 0x30088FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmacchnfr<.cc> 0,limm,c 00110bbb110010001BBB1111100QQQQQ.  */
+{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmacchnfr<.cc> b,b,limm 00110110110010001111CCCCCC0QQQQQ.  */
+{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA.  */
+{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110.  */
+{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr<.cc> 0,limm,u6 00110110110010001111uuuuuu1QQQQQ.  */
+{ "cmacchnfr", 0x36C8F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmacchnfr 0,limm,s12 00110110100010001111ssssssSSSSSS.  */
+{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA.  */
+{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchnfr 0,limm,limm 00110110000010001111111110111110.  */
+{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchnfr<.cc> 0,limm,limm 001101101100100011111111100QQQQQ.  */
+{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA.  */
+{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110.  */
+{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ.  */
+{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA.  */
+{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110.  */
+{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ.  */
+{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS.  */
+{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA.  */
+{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA.  */
+{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110.  */
+{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmachfr 0,b,limm 00110bbb000001111BBB111110111110.  */
+{ "cmachfr", 0x30078FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmachfr<.cc> 0,limm,c 00110bbb110001111BBB1111100QQQQQ.  */
+{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmachfr<.cc> b,b,limm 00110110110001111111CCCCCC0QQQQQ.  */
+{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA.  */
+{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110.  */
+{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachfr<.cc> 0,limm,u6 00110110110001111111uuuuuu1QQQQQ.  */
+{ "cmachfr", 0x36C7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmachfr 0,limm,s12 00110110100001111111ssssssSSSSSS.  */
+{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA.  */
+{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmachfr 0,limm,limm 00110110000001111111111110111110.  */
+{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmachfr<.cc> 0,limm,limm 001101101100011111111111100QQQQQ.  */
+{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA.  */
+{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110.  */
+{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ.  */
+{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA.  */
+{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110.  */
+{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ.  */
+{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS.  */
+{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA.  */
+{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA.  */
+{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110.  */
+{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmachnfr 0,b,limm 00110bbb000001101BBB111110111110.  */
+{ "cmachnfr", 0x30068FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmachnfr<.cc> 0,limm,c 00110bbb110001101BBB1111100QQQQQ.  */
+{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmachnfr<.cc> b,b,limm 00110110110001101111CCCCCC0QQQQQ.  */
+{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA.  */
+{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110.  */
+{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachnfr<.cc> 0,limm,u6 00110110110001101111uuuuuu1QQQQQ.  */
+{ "cmachnfr", 0x36C6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmachnfr 0,limm,s12 00110110100001101111ssssssSSSSSS.  */
+{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA.  */
+{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmachnfr 0,limm,limm 00110110000001101111111110111110.  */
+{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmachnfr<.cc> 0,limm,limm 001101101100011011111111100QQQQQ.  */
+{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmacrdw<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA.  */
+{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* cmacrdw<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110.  */
+{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* cmacrdw<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ.  */
+{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* cmacrdw<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA.  */
+{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* cmacrdw<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110.  */
+{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* cmacrdw<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ.  */
+{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* cmacrdw<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS.  */
+{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* cmacrdw<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA.  */
+{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* cmacrdw<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA.  */
+{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* cmacrdw<.f> 0,limm,c 0010111000100110F111CCCCCC111110.  */
+{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* cmacrdw<.f> 0,b,limm 00101bbb00100110FBBB111110111110.  */
+{ "cmacrdw", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* cmacrdw<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ.  */
+{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* cmacrdw<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ.  */
+{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* cmacrdw<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA.  */
+{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* cmacrdw<.f> 0,limm,u6 0010111001100110F111uuuuuu111110.  */
+{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* cmacrdw<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ.  */
+{ "cmacrdw", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* cmacrdw<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS.  */
+{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* cmacrdw<.f> a,limm,limm 0010111000100110F111111110AAAAAA.  */
+{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* cmacrdw<.f> 0,limm,limm 0010111000100110F111111110111110.  */
+{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* cmacrdw<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ.  */
+{ "cmacrdw", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR.  */
+{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* cmp b,c 00100bbb000011001BBBCCCCCC000000.  */
+{ "cmp", 0x200C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ.  */
+{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR.  */
+{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cmp b,u6 00100bbb010011001BBBuuuuuu000000.  */
+{ "cmp", 0x204C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ.  */
+{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS.  */
+{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* cmp limm,c 00100110000011001111CCCCCCRRRRRR.  */
+{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* cmp b,limm 00100bbb000011001BBB111110RRRRRR.  */
+{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* cmp limm,c 00100110000011001111CCCCCC000000.  */
+{ "cmp", 0x260CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* cmp b,limm 00100bbb000011001BBB111110000000.  */
+{ "cmp", 0x200C8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ.  */
+{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ.  */
+{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR.  */
+{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* cmp limm,u6 00100110010011001111uuuuuu000000.  */
+{ "cmp", 0x264CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ.  */
+{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmp limm,s12 00100110100011001111ssssssSSSSSS.  */
+{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* cmp limm,limm 00100110000011001111111110RRRRRR.  */
+{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* cmp limm,limm 00100110000011001111111110000000.  */
+{ "cmp", 0x260CFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ.  */
+{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA.  */
+{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110.  */
+{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ.  */
+{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA.  */
+{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110.  */
+{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ.  */
+{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS.  */
+{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA.  */
+{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA.  */
+{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110.  */
+{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpychfr 0,b,limm 00110bbb000001011BBB111110111110.  */
+{ "cmpychfr", 0x30058FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpychfr<.cc> 0,limm,c 00110bbb110001011BBB1111100QQQQQ.  */
+{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpychfr<.cc> b,b,limm 00110110110001011111CCCCCC0QQQQQ.  */
+{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA.  */
+{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110.  */
+{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychfr<.cc> 0,limm,u6 00110110110001011111uuuuuu1QQQQQ.  */
+{ "cmpychfr", 0x36C5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpychfr 0,limm,s12 00110110100001011111ssssssSSSSSS.  */
+{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA.  */
+{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychfr 0,limm,limm 00110110000001011111111110111110.  */
+{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychfr<.cc> 0,limm,limm 001101101100010111111111100QQQQQ.  */
+{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA.  */
+{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110.  */
+{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ.  */
+{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA.  */
+{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110.  */
+{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ.  */
+{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS.  */
+{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA.  */
+{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA.  */
+{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110.  */
+{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpychnfr 0,b,limm 00110bbb000000001BBB111110111110.  */
+{ "cmpychnfr", 0x30008FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpychnfr<.cc> 0,limm,c 00110bbb110000001BBB1111100QQQQQ.  */
+{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpychnfr<.cc> b,b,limm 00110110110000001111CCCCCC0QQQQQ.  */
+{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA.  */
+{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110.  */
+{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr<.cc> 0,limm,u6 00110110110000001111uuuuuu1QQQQQ.  */
+{ "cmpychnfr", 0x36C0F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpychnfr 0,limm,s12 00110110100000001111ssssssSSSSSS.  */
+{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA.  */
+{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychnfr 0,limm,limm 00110110000000001111111110111110.  */
+{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychnfr<.cc> 0,limm,limm 001101101100000011111111100QQQQQ.  */
+{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA.  */
+{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110.  */
+{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ.  */
+{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA.  */
+{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110.  */
+{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ.  */
+{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS.  */
+{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA.  */
+{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA.  */
+{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110.  */
+{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpyhfmr 0,b,limm 00110bbb000110110BBB111110111110.  */
+{ "cmpyhfmr", 0x301B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpyhfmr<.cc> 0,limm,c 00110bbb110110110BBB1111100QQQQQ.  */
+{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpyhfmr<.cc> b,b,limm 00110110110110110111CCCCCC0QQQQQ.  */
+{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA.  */
+{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110.  */
+{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr<.cc> 0,limm,u6 00110110110110110111uuuuuu1QQQQQ.  */
+{ "cmpyhfmr", 0x36DB7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfmr 0,limm,s12 00110110100110110111ssssssSSSSSS.  */
+{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA.  */
+{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110.  */
+{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfmr<.cc> 0,limm,limm 001101101101101101111111100QQQQQ.  */
+{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA.  */
+{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110.  */
+{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ.  */
+{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA.  */
+{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110.  */
+{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ.  */
+{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS.  */
+{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA.  */
+{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA.  */
+{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110.  */
+{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpyhfr 0,b,limm 00110bbb000000011BBB111110111110.  */
+{ "cmpyhfr", 0x30018FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpyhfr<.cc> 0,limm,c 00110bbb110000011BBB1111100QQQQQ.  */
+{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpyhfr<.cc> b,b,limm 00110110110000011111CCCCCC0QQQQQ.  */
+{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA.  */
+{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110.  */
+{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr<.cc> 0,limm,u6 00110110110000011111uuuuuu1QQQQQ.  */
+{ "cmpyhfr", 0x36C1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfr 0,limm,s12 00110110100000011111ssssssSSSSSS.  */
+{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA.  */
+{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfr 0,limm,limm 00110110000000011111111110111110.  */
+{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfr<.cc> 0,limm,limm 001101101100000111111111100QQQQQ.  */
+{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA.  */
+{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110.  */
+{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ.  */
+{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA.  */
+{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110.  */
+{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ.  */
+{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS.  */
+{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA.  */
+{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA.  */
+{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110.  */
+{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpyhnfr 0,b,limm 00110bbb000000101BBB111110111110.  */
+{ "cmpyhnfr", 0x30028FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpyhnfr<.cc> 0,limm,c 00110bbb110000101BBB1111100QQQQQ.  */
+{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpyhnfr<.cc> b,b,limm 00110110110000101111CCCCCC0QQQQQ.  */
+{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA.  */
+{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110.  */
+{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr<.cc> 0,limm,u6 00110110110000101111uuuuuu1QQQQQ.  */
+{ "cmpyhnfr", 0x36C2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpyhnfr 0,limm,s12 00110110100000101111ssssssSSSSSS.  */
+{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA.  */
+{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110.  */
+{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhnfr<.cc> 0,limm,limm 001101101100001011111111100QQQQQ.  */
+{ "cmpyhnfr", 0x36C2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmp_s b,h 01110bbbhhh10HHH.  */
+{ "cmp_s", 0x00007010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, R6H }, { 0 }},
+
+/* cmp_s b,h 01110bbbhhh100HH.  */
+{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RH_S }, { 0 }},
+
+/* cmp_s h,s3 01110ssshhh101HH.  */
+{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RH_S, SIMM3_5_S }, { 0 }},
+
+/* cmp_s b,u7 11100bbb1uuuuuuu.  */
+{ "cmp_s", 0x0000E080, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, UIMM7_9_S }, { 0 }},
+
+/* cmp_s b,limm 01110bbb11010111.  */
+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, LIMM_S }, { 0 }},
+
+/* cmp_s b,limm 01110bbb11010011.  */
+{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, LIMM_S }, { 0 }},
+
+/* cmp_s limm,s3 01110sss11010111.  */
+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM_S, SIMM3_5_S }, { 0 }},
+
+/* crc<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA.  */
+{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* crc<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110.  */
+{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* crc<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ.  */
+{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* crc<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA.  */
+{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* crc<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110.  */
+{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* crc<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ.  */
+{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* crc<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS.  */
+{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* crc<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA.  */
+{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* crc<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA.  */
+{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* crc<.f> 0,limm,c 0010111000101100F111CCCCCC111110.  */
+{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* crc<.f> 0,b,limm 00101bbb00101100FBBB111110111110.  */
+{ "crc", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* crc<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ.  */
+{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* crc<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ.  */
+{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* crc<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA.  */
+{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* crc<.f> 0,limm,u6 0010111001101100F111uuuuuu111110.  */
+{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* crc<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ.  */
+{ "crc", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* crc<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS.  */
+{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* crc<.f> a,limm,limm 0010111000101100F111111110AAAAAA.  */
+{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* crc<.f> 0,limm,limm 0010111000101100F111111110111110.  */
+{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* crc<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ.  */
+{ "crc", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh11<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA.  */
+{ "daddh11", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh11<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110.  */
+{ "daddh11", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh11<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ.  */
+{ "daddh11", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh11<.f> a,b,c 00110bbb00110100FBBBCCCCCCAAAAAA.  */
+{ "daddh11", 0x30340000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh11<.f> 0,b,c 00110bbb00110100FBBBCCCCCC111110.  */
+{ "daddh11", 0x3034003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh11<.f><.cc> b,b,c 00110bbb11110100FBBBCCCCCC0QQQQQ.  */
+{ "daddh11", 0x30F40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh11<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA.  */
+{ "daddh11", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110.  */
+{ "daddh11", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ.  */
+{ "daddh11", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh11<.f> a,b,u6 00110bbb01110100FBBBuuuuuuAAAAAA.  */
+{ "daddh11", 0x30740000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f> 0,b,u6 00110bbb01110100FBBBuuuuuu111110.  */
+{ "daddh11", 0x3074003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f><.cc> b,b,u6 00110bbb11110100FBBBuuuuuu1QQQQQ.  */
+{ "daddh11", 0x30F40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh11<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS.  */
+{ "daddh11", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh11<.f> b,b,s12 00110bbb10110100FBBBssssssSSSSSS.  */
+{ "daddh11", 0x30B40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh11<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA.  */
+{ "daddh11", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh11<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA.  */
+{ "daddh11", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh11<.f> 0,limm,c 0011011000001100F111CCCCCC111110.  */
+{ "daddh11", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh11<.f> 0,b,limm 00110bbb00001100FBBB111110111110.  */
+{ "daddh11", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh11<.f><.cc> 0,limm,c 0011011011001100F111CCCCCC0QQQQQ.  */
+{ "daddh11", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh11<.f><.cc> b,b,limm 00110bbb11001100FBBB1111100QQQQQ.  */
+{ "daddh11", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh11<.f> a,limm,c 0011011000110100F111CCCCCCAAAAAA.  */
+{ "daddh11", 0x36347000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh11<.f> a,b,limm 00110bbb00110100FBBB111110AAAAAA.  */
+{ "daddh11", 0x30340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh11<.f> 0,limm,c 0011011000110100F111CCCCCC111110.  */
+{ "daddh11", 0x3634703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh11<.f> 0,b,limm 00110bbb00110100FBBB111110111110.  */
+{ "daddh11", 0x30340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh11<.f><.cc> 0,limm,c 0011011011110100F111CCCCCC0QQQQQ.  */
+{ "daddh11", 0x36F47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh11<.f><.cc> b,b,limm 00110bbb11110100FBBB1111100QQQQQ.  */
+{ "daddh11", 0x30F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh11<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA.  */
+{ "daddh11", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f> 0,limm,u6 0011011001001100F111uuuuuu111110.  */
+{ "daddh11", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ.  */
+{ "daddh11", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh11<.f> a,limm,u6 0011011001110100F111uuuuuuAAAAAA.  */
+{ "daddh11", 0x36747000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f> 0,limm,u6 0011011001110100F111uuuuuu111110.  */
+{ "daddh11", 0x3674703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh11<.f><.cc> 0,limm,u6 0011011011110100F111uuuuuu1QQQQQ.  */
+{ "daddh11", 0x36F47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh11<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS.  */
+{ "daddh11", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh11<.f> 0,limm,s12 0011011010110100F111ssssssSSSSSS.  */
+{ "daddh11", 0x36B47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh11<.f> a,limm,limm 0011011000001100F111111110AAAAAA.  */
+{ "daddh11", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh11<.f> 0,limm,limm 0011011000001100F111111110111110.  */
+{ "daddh11", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh11<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ.  */
+{ "daddh11", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh11<.f> a,limm,limm 0011011000110100F111111110AAAAAA.  */
+{ "daddh11", 0x36347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh11<.f> 0,limm,limm 0011011000110100F111111110111110.  */
+{ "daddh11", 0x36347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh11<.f><.cc> 0,limm,limm 0011011011110100F1111111100QQQQQ.  */
+{ "daddh11", 0x36F47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh12<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA.  */
+{ "daddh12", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh12<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110.  */
+{ "daddh12", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh12<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ.  */
+{ "daddh12", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh12<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA.  */
+{ "daddh12", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh12<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110.  */
+{ "daddh12", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh12<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ.  */
+{ "daddh12", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh12<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA.  */
+{ "daddh12", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110.  */
+{ "daddh12", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ.  */
+{ "daddh12", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh12<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA.  */
+{ "daddh12", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110.  */
+{ "daddh12", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ.  */
+{ "daddh12", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh12<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS.  */
+{ "daddh12", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh12<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS.  */
+{ "daddh12", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh12<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA.  */
+{ "daddh12", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh12<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA.  */
+{ "daddh12", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh12<.f> 0,limm,c 0011011000001101F111CCCCCC111110.  */
+{ "daddh12", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh12<.f> 0,b,limm 00110bbb00001101FBBB111110111110.  */
+{ "daddh12", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh12<.f><.cc> 0,limm,c 0011011011001101F111CCCCCC0QQQQQ.  */
+{ "daddh12", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh12<.f><.cc> b,b,limm 00110bbb11001101FBBB1111100QQQQQ.  */
+{ "daddh12", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh12<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA.  */
+{ "daddh12", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh12<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA.  */
+{ "daddh12", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh12<.f> 0,limm,c 0011011000110101F111CCCCCC111110.  */
+{ "daddh12", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh12<.f> 0,b,limm 00110bbb00110101FBBB111110111110.  */
+{ "daddh12", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh12<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ.  */
+{ "daddh12", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh12<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ.  */
+{ "daddh12", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh12<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA.  */
+{ "daddh12", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f> 0,limm,u6 0011011001001101F111uuuuuu111110.  */
+{ "daddh12", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ.  */
+{ "daddh12", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh12<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA.  */
+{ "daddh12", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f> 0,limm,u6 0011011001110101F111uuuuuu111110.  */
+{ "daddh12", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh12<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ.  */
+{ "daddh12", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh12<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS.  */
+{ "daddh12", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh12<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS.  */
+{ "daddh12", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh12<.f> a,limm,limm 0011011000001101F111111110AAAAAA.  */
+{ "daddh12", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh12<.f> 0,limm,limm 0011011000001101F111111110111110.  */
+{ "daddh12", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh12<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ.  */
+{ "daddh12", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh12<.f> a,limm,limm 0011011000110101F111111110AAAAAA.  */
+{ "daddh12", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh12<.f> 0,limm,limm 0011011000110101F111111110111110.  */
+{ "daddh12", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh12<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ.  */
+{ "daddh12", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh21<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA.  */
+{ "daddh21", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh21<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110.  */
+{ "daddh21", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh21<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ.  */
+{ "daddh21", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh21<.f> a,b,c 00110bbb00110110FBBBCCCCCCAAAAAA.  */
+{ "daddh21", 0x30360000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh21<.f> 0,b,c 00110bbb00110110FBBBCCCCCC111110.  */
+{ "daddh21", 0x3036003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh21<.f><.cc> b,b,c 00110bbb11110110FBBBCCCCCC0QQQQQ.  */
+{ "daddh21", 0x30F60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh21<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA.  */
+{ "daddh21", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110.  */
+{ "daddh21", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ.  */
+{ "daddh21", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh21<.f> a,b,u6 00110bbb01110110FBBBuuuuuuAAAAAA.  */
+{ "daddh21", 0x30760000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f> 0,b,u6 00110bbb01110110FBBBuuuuuu111110.  */
+{ "daddh21", 0x3076003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f><.cc> b,b,u6 00110bbb11110110FBBBuuuuuu1QQQQQ.  */
+{ "daddh21", 0x30F60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh21<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS.  */
+{ "daddh21", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh21<.f> b,b,s12 00110bbb10110110FBBBssssssSSSSSS.  */
+{ "daddh21", 0x30B60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh21<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA.  */
+{ "daddh21", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh21<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA.  */
+{ "daddh21", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh21<.f> 0,limm,c 0011011000001110F111CCCCCC111110.  */
+{ "daddh21", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh21<.f> 0,b,limm 00110bbb00001110FBBB111110111110.  */
+{ "daddh21", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh21<.f><.cc> 0,limm,c 0011011011001110F111CCCCCC0QQQQQ.  */
+{ "daddh21", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh21<.f><.cc> b,b,limm 00110bbb11001110FBBB1111100QQQQQ.  */
+{ "daddh21", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh21<.f> a,limm,c 0011011000110110F111CCCCCCAAAAAA.  */
+{ "daddh21", 0x36367000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh21<.f> a,b,limm 00110bbb00110110FBBB111110AAAAAA.  */
+{ "daddh21", 0x30360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh21<.f> 0,limm,c 0011011000110110F111CCCCCC111110.  */
+{ "daddh21", 0x3636703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh21<.f> 0,b,limm 00110bbb00110110FBBB111110111110.  */
+{ "daddh21", 0x30360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh21<.f><.cc> 0,limm,c 0011011011110110F111CCCCCC0QQQQQ.  */
+{ "daddh21", 0x36F67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh21<.f><.cc> b,b,limm 00110bbb11110110FBBB1111100QQQQQ.  */
+{ "daddh21", 0x30F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh21<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA.  */
+{ "daddh21", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f> 0,limm,u6 0011011001001110F111uuuuuu111110.  */
+{ "daddh21", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ.  */
+{ "daddh21", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh21<.f> a,limm,u6 0011011001110110F111uuuuuuAAAAAA.  */
+{ "daddh21", 0x36767000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f> 0,limm,u6 0011011001110110F111uuuuuu111110.  */
+{ "daddh21", 0x3676703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh21<.f><.cc> 0,limm,u6 0011011011110110F111uuuuuu1QQQQQ.  */
+{ "daddh21", 0x36F67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh21<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS.  */
+{ "daddh21", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh21<.f> 0,limm,s12 0011011010110110F111ssssssSSSSSS.  */
+{ "daddh21", 0x36B67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh21<.f> a,limm,limm 0011011000001110F111111110AAAAAA.  */
+{ "daddh21", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh21<.f> 0,limm,limm 0011011000001110F111111110111110.  */
+{ "daddh21", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh21<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ.  */
+{ "daddh21", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh21<.f> a,limm,limm 0011011000110110F111111110AAAAAA.  */
+{ "daddh21", 0x36367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh21<.f> 0,limm,limm 0011011000110110F111111110111110.  */
+{ "daddh21", 0x36367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh21<.f><.cc> 0,limm,limm 0011011011110110F1111111100QQQQQ.  */
+{ "daddh21", 0x36F67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh22<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA.  */
+{ "daddh22", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh22<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110.  */
+{ "daddh22", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh22<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ.  */
+{ "daddh22", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh22<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA.  */
+{ "daddh22", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* daddh22<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110.  */
+{ "daddh22", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* daddh22<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ.  */
+{ "daddh22", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* daddh22<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA.  */
+{ "daddh22", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110.  */
+{ "daddh22", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ.  */
+{ "daddh22", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh22<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA.  */
+{ "daddh22", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110.  */
+{ "daddh22", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ.  */
+{ "daddh22", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh22<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS.  */
+{ "daddh22", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh22<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS.  */
+{ "daddh22", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* daddh22<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA.  */
+{ "daddh22", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh22<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA.  */
+{ "daddh22", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh22<.f> 0,limm,c 0011011000001111F111CCCCCC111110.  */
+{ "daddh22", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh22<.f> 0,b,limm 00110bbb00001111FBBB111110111110.  */
+{ "daddh22", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh22<.f><.cc> 0,limm,c 0011011011001111F111CCCCCC0QQQQQ.  */
+{ "daddh22", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh22<.f><.cc> b,b,limm 00110bbb11001111FBBB1111100QQQQQ.  */
+{ "daddh22", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh22<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA.  */
+{ "daddh22", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* daddh22<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA.  */
+{ "daddh22", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* daddh22<.f> 0,limm,c 0011011000110111F111CCCCCC111110.  */
+{ "daddh22", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* daddh22<.f> 0,b,limm 00110bbb00110111FBBB111110111110.  */
+{ "daddh22", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* daddh22<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ.  */
+{ "daddh22", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* daddh22<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ.  */
+{ "daddh22", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* daddh22<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA.  */
+{ "daddh22", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f> 0,limm,u6 0011011001001111F111uuuuuu111110.  */
+{ "daddh22", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ.  */
+{ "daddh22", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh22<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA.  */
+{ "daddh22", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f> 0,limm,u6 0011011001110111F111uuuuuu111110.  */
+{ "daddh22", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* daddh22<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ.  */
+{ "daddh22", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* daddh22<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS.  */
+{ "daddh22", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh22<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS.  */
+{ "daddh22", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* daddh22<.f> a,limm,limm 0011011000001111F111111110AAAAAA.  */
+{ "daddh22", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh22<.f> 0,limm,limm 0011011000001111F111111110111110.  */
+{ "daddh22", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh22<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ.  */
+{ "daddh22", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* daddh22<.f> a,limm,limm 0011011000110111F111111110AAAAAA.  */
+{ "daddh22", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh22<.f> 0,limm,limm 0011011000110111F111111110111110.  */
+{ "daddh22", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* daddh22<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ.  */
+{ "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
+{ "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dexcl1<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110.  */
+{ "dexcl1", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dexcl1<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ.  */
+{ "dexcl1", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,b,c 00110bbb00111100FBBBCCCCCCAAAAAA.  */
+{ "dexcl1", 0x303C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dexcl1<.f> 0,b,c 00110bbb00111100FBBBCCCCCC111110.  */
+{ "dexcl1", 0x303C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dexcl1<.f><.cc> b,b,c 00110bbb11111100FBBBCCCCCC0QQQQQ.  */
+{ "dexcl1", 0x30FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA.  */
+{ "dexcl1", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110.  */
+{ "dexcl1", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ.  */
+{ "dexcl1", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,b,u6 00110bbb01111100FBBBuuuuuuAAAAAA.  */
+{ "dexcl1", 0x307C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f> 0,b,u6 00110bbb01111100FBBBuuuuuu111110.  */
+{ "dexcl1", 0x307C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f><.cc> b,b,u6 00110bbb11111100FBBBuuuuuu1QQQQQ.  */
+{ "dexcl1", 0x30FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl1<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS.  */
+{ "dexcl1", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dexcl1<.f> b,b,s12 00110bbb10111100FBBBssssssSSSSSS.  */
+{ "dexcl1", 0x30BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dexcl1<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA.  */
+{ "dexcl1", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dexcl1<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA.  */
+{ "dexcl1", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dexcl1<.f> 0,limm,c 0011011000011000F111CCCCCC111110.  */
+{ "dexcl1", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dexcl1<.f> 0,b,limm 00110bbb00011000FBBB111110111110.  */
+{ "dexcl1", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dexcl1<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ.  */
+{ "dexcl1", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dexcl1<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ.  */
+{ "dexcl1", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,limm,c 0011011000111100F111CCCCCCAAAAAA.  */
+{ "dexcl1", 0x363C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dexcl1<.f> a,b,limm 00110bbb00111100FBBB111110AAAAAA.  */
+{ "dexcl1", 0x303C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dexcl1<.f> 0,limm,c 0011011000111100F111CCCCCC111110.  */
+{ "dexcl1", 0x363C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dexcl1<.f> 0,b,limm 00110bbb00111100FBBB111110111110.  */
+{ "dexcl1", 0x303C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dexcl1<.f><.cc> 0,limm,c 0011011011111100F111CCCCCC0QQQQQ.  */
+{ "dexcl1", 0x36FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dexcl1<.f><.cc> b,b,limm 00110bbb11111100FBBB1111100QQQQQ.  */
+{ "dexcl1", 0x30FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA.  */
+{ "dexcl1", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f> 0,limm,u6 0011011001011000F111uuuuuu111110.  */
+{ "dexcl1", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ.  */
+{ "dexcl1", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,limm,u6 0011011001111100F111uuuuuuAAAAAA.  */
+{ "dexcl1", 0x367C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f> 0,limm,u6 0011011001111100F111uuuuuu111110.  */
+{ "dexcl1", 0x367C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl1<.f><.cc> 0,limm,u6 0011011011111100F111uuuuuu1QQQQQ.  */
+{ "dexcl1", 0x36FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl1<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS.  */
+{ "dexcl1", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dexcl1<.f> 0,limm,s12 0011011010111100F111ssssssSSSSSS.  */
+{ "dexcl1", 0x36BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dexcl1<.f> a,limm,limm 0011011000011000F111111110AAAAAA.  */
+{ "dexcl1", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl1<.f> 0,limm,limm 0011011000011000F111111110111110.  */
+{ "dexcl1", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl1<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ.  */
+{ "dexcl1", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dexcl1<.f> a,limm,limm 0011011000111100F111111110AAAAAA.  */
+{ "dexcl1", 0x363C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl1<.f> 0,limm,limm 0011011000111100F111111110111110.  */
+{ "dexcl1", 0x363C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl1<.f><.cc> 0,limm,limm 0011011011111100F1111111100QQQQQ.  */
+{ "dexcl1", 0x36FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA.  */
+{ "dexcl2", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dexcl2<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110.  */
+{ "dexcl2", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dexcl2<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ.  */
+{ "dexcl2", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,b,c 00110bbb00111101FBBBCCCCCCAAAAAA.  */
+{ "dexcl2", 0x303D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dexcl2<.f> 0,b,c 00110bbb00111101FBBBCCCCCC111110.  */
+{ "dexcl2", 0x303D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dexcl2<.f><.cc> b,b,c 00110bbb11111101FBBBCCCCCC0QQQQQ.  */
+{ "dexcl2", 0x30FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA.  */
+{ "dexcl2", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110.  */
+{ "dexcl2", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ.  */
+{ "dexcl2", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,b,u6 00110bbb01111101FBBBuuuuuuAAAAAA.  */
+{ "dexcl2", 0x307D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f> 0,b,u6 00110bbb01111101FBBBuuuuuu111110.  */
+{ "dexcl2", 0x307D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f><.cc> b,b,u6 00110bbb11111101FBBBuuuuuu1QQQQQ.  */
+{ "dexcl2", 0x30FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl2<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS.  */
+{ "dexcl2", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dexcl2<.f> b,b,s12 00110bbb10111101FBBBssssssSSSSSS.  */
+{ "dexcl2", 0x30BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dexcl2<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA.  */
+{ "dexcl2", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dexcl2<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA.  */
+{ "dexcl2", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dexcl2<.f> 0,limm,c 0011011000011001F111CCCCCC111110.  */
+{ "dexcl2", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dexcl2<.f> 0,b,limm 00110bbb00011001FBBB111110111110.  */
+{ "dexcl2", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dexcl2<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ.  */
+{ "dexcl2", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dexcl2<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ.  */
+{ "dexcl2", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,limm,c 0011011000111101F111CCCCCCAAAAAA.  */
+{ "dexcl2", 0x363D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dexcl2<.f> a,b,limm 00110bbb00111101FBBB111110AAAAAA.  */
+{ "dexcl2", 0x303D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dexcl2<.f> 0,limm,c 0011011000111101F111CCCCCC111110.  */
+{ "dexcl2", 0x363D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dexcl2<.f> 0,b,limm 00110bbb00111101FBBB111110111110.  */
+{ "dexcl2", 0x303D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dexcl2<.f><.cc> 0,limm,c 0011011011111101F111CCCCCC0QQQQQ.  */
+{ "dexcl2", 0x36FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dexcl2<.f><.cc> b,b,limm 00110bbb11111101FBBB1111100QQQQQ.  */
+{ "dexcl2", 0x30FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA.  */
+{ "dexcl2", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f> 0,limm,u6 0011011001011001F111uuuuuu111110.  */
+{ "dexcl2", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ.  */
+{ "dexcl2", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,limm,u6 0011011001111101F111uuuuuuAAAAAA.  */
+{ "dexcl2", 0x367D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f> 0,limm,u6 0011011001111101F111uuuuuu111110.  */
+{ "dexcl2", 0x367D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dexcl2<.f><.cc> 0,limm,u6 0011011011111101F111uuuuuu1QQQQQ.  */
+{ "dexcl2", 0x36FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dexcl2<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS.  */
+{ "dexcl2", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dexcl2<.f> 0,limm,s12 0011011010111101F111ssssssSSSSSS.  */
+{ "dexcl2", 0x36BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dexcl2<.f> a,limm,limm 0011011000011001F111111110AAAAAA.  */
+{ "dexcl2", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl2<.f> 0,limm,limm 0011011000011001F111111110111110.  */
+{ "dexcl2", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl2<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ.  */
+{ "dexcl2", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dexcl2<.f> a,limm,limm 0011011000111101F111111110AAAAAA.  */
+{ "dexcl2", 0x363D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl2<.f> 0,limm,limm 0011011000111101F111111110111110.  */
+{ "dexcl2", 0x363D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dexcl2<.f><.cc> 0,limm,limm 0011011011111101F1111111100QQQQQ.  */
+{ "dexcl2", 0x36FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA.  */
+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }},
+
+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110.  */
+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }},
+
+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ.  */
+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA.  */
+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110.  */
+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ.  */
+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS.  */
+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA.  */
+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }},
+
+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA.  */
+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }},
+
+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110.  */
+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110.  */
+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ.  */
+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ.  */
+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA.  */
+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110.  */
+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ.  */
+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS.  */
+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA.  */
+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f> 0,limm,limm 0010111000000100F111111110111110.  */
+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ.  */
+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divacc c 00101011001011110000CCCCCC111111.  */
+{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }},
+
+/* divacc u6 00101011011011110000uuuuuu111111.  */
+{ "divacc", 0x2B6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* divaw<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA.  */
+{ "divaw", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* divaw<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110.  */
+{ "divaw", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divaw<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ.  */
+{ "divaw", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* divaw<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA.  */
+{ "divaw", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* divaw<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110.  */
+{ "divaw", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divaw<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ.  */
+{ "divaw", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divaw<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS.  */
+{ "divaw", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* divaw<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA.  */
+{ "divaw", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* divaw<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA.  */
+{ "divaw", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* divaw<.f> 0,limm,c 0010111000001000F111CCCCCC111110.  */
+{ "divaw", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divaw<.f> 0,b,limm 00101bbb00001000FBBB111110111110.  */
+{ "divaw", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divaw<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ.  */
+{ "divaw", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divaw<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ.  */
+{ "divaw", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divaw<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA.  */
+{ "divaw", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divaw<.f> 0,limm,u6 0010111001001000F111uuuuuu111110.  */
+{ "divaw", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divaw<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ.  */
+{ "divaw", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divaw<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS.  */
+{ "divaw", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divaw<.f> a,limm,limm 0010111000001000F111111110AAAAAA.  */
+{ "divaw", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* divaw<.f> 0,limm,limm 0010111000001000F111111110111110.  */
+{ "divaw", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divaw<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ.  */
+{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA.  */
+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }},
+
+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110.  */
+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }},
+
+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ.  */
+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA.  */
+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110.  */
+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ.  */
+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS.  */
+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA.  */
+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }},
+
+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA.  */
+{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }},
+
+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110.  */
+{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110.  */
+{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ.  */
+{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ.  */
+{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA.  */
+{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110.  */
+{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ.  */
+{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS.  */
+{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA.  */
+{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110.  */
+{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ.  */
+{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA.  */
+{ "dmach", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }},
+
+/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110.  */
+{ "dmach", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ.  */
+{ "dmach", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA.  */
+{ "dmach", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110.  */
+{ "dmach", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ.  */
+{ "dmach", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS.  */
+{ "dmach", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA.  */
+{ "dmach", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }},
+
+/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA.  */
+{ "dmach", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }},
+
+/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110.  */
+{ "dmach", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110.  */
+{ "dmach", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ.  */
+{ "dmach", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ.  */
+{ "dmach", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA.  */
+{ "dmach", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110.  */
+{ "dmach", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ.  */
+{ "dmach", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS.  */
+{ "dmach", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA.  */
+{ "dmach", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110.  */
+{ "dmach", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ.  */
+{ "dmach", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachbl<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
+{ "dmachbl", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmachbl<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110.  */
+{ "dmachbl", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachbl<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ.  */
+{ "dmachbl", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachbl<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA.  */
+{ "dmachbl", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110.  */
+{ "dmachbl", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ.  */
+{ "dmachbl", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbl<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS.  */
+{ "dmachbl", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachbl<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA.  */
+{ "dmachbl", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmachbl<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA.  */
+{ "dmachbl", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmachbl<.f> 0,limm,c 0011011000011000F111CCCCCC111110.  */
+{ "dmachbl", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachbl<.f> 0,b,limm 00110bbb00011000FBBB111110111110.  */
+{ "dmachbl", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachbl<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ.  */
+{ "dmachbl", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachbl<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ.  */
+{ "dmachbl", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachbl<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA.  */
+{ "dmachbl", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f> 0,limm,u6 0011011001011000F111uuuuuu111110.  */
+{ "dmachbl", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ.  */
+{ "dmachbl", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbl<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS.  */
+{ "dmachbl", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachbl<.f> a,limm,limm 0011011000011000F111111110AAAAAA.  */
+{ "dmachbl", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbl<.f> 0,limm,limm 0011011000011000F111111110111110.  */
+{ "dmachbl", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbl<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ.  */
+{ "dmachbl", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachbm<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA.  */
+{ "dmachbm", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmachbm<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110.  */
+{ "dmachbm", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachbm<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ.  */
+{ "dmachbm", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachbm<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA.  */
+{ "dmachbm", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110.  */
+{ "dmachbm", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ.  */
+{ "dmachbm", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbm<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS.  */
+{ "dmachbm", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachbm<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA.  */
+{ "dmachbm", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmachbm<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA.  */
+{ "dmachbm", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmachbm<.f> 0,limm,c 0011011000011001F111CCCCCC111110.  */
+{ "dmachbm", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachbm<.f> 0,b,limm 00110bbb00011001FBBB111110111110.  */
+{ "dmachbm", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachbm<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ.  */
+{ "dmachbm", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachbm<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ.  */
+{ "dmachbm", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachbm<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA.  */
+{ "dmachbm", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f> 0,limm,u6 0011011001011001F111uuuuuu111110.  */
+{ "dmachbm", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ.  */
+{ "dmachbm", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbm<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS.  */
+{ "dmachbm", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachbm<.f> a,limm,limm 0011011000011001F111111110AAAAAA.  */
+{ "dmachbm", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbm<.f> 0,limm,limm 0011011000011001F111111110111110.  */
+{ "dmachbm", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbm<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ.  */
+{ "dmachbm", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachf<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA.  */
+{ "dmachf", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmachf<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110.  */
+{ "dmachf", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachf<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ.  */
+{ "dmachf", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachf<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA.  */
+{ "dmachf", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110.  */
+{ "dmachf", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ.  */
+{ "dmachf", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachf<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS.  */
+{ "dmachf", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachf<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA.  */
+{ "dmachf", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmachf<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA.  */
+{ "dmachf", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmachf<.f> 0,limm,c 0010111001101100F111CCCCCC111110.  */
+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachf<.f> 0,b,limm 00101bbb00101100FBBB111110111110.  */
+{ "dmachf", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachf<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ.  */
+{ "dmachf", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachf<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ.  */
+{ "dmachf", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachf<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA.  */
+{ "dmachf", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f> 0,limm,u6 0010111001101100F111uuuuuu111110.  */
+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ.  */
+{ "dmachf", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachf<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS.  */
+{ "dmachf", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachf<.f> a,limm,limm 0010111000101100F111111110AAAAAA.  */
+{ "dmachf", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachf<.f> 0,limm,limm 0010111000101100F111111110111110.  */
+{ "dmachf", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachf<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ.  */
+{ "dmachf", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachfr<.f> a,b,c 00101bbb00101101FBBBCCCCCCAAAAAA.  */
+{ "dmachfr", 0x282D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmachfr<.f> 0,b,c 00101bbb00101101FBBBCCCCCC111110.  */
+{ "dmachfr", 0x282D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachfr<.f><.cc> b,b,c 00101bbb11101101FBBBCCCCCC0QQQQQ.  */
+{ "dmachfr", 0x28ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachfr<.f> a,b,u6 00101bbb01101101FBBBuuuuuuAAAAAA.  */
+{ "dmachfr", 0x286D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f> 0,b,u6 00101bbb01101101FBBBuuuuuu111110.  */
+{ "dmachfr", 0x286D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f><.cc> b,b,u6 00101bbb11101101FBBBuuuuuu1QQQQQ.  */
+{ "dmachfr", 0x28ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachfr<.f> b,b,s12 00101bbb10101101FBBBssssssSSSSSS.  */
+{ "dmachfr", 0x28AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachfr<.f> a,limm,c 0010111000101101F111CCCCCCAAAAAA.  */
+{ "dmachfr", 0x2E2D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmachfr<.f> a,b,limm 00101bbb00101101FBBB111110AAAAAA.  */
+{ "dmachfr", 0x282D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmachfr<.f> 0,limm,c 0010111001101101F111CCCCCC111110.  */
+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachfr<.f> 0,b,limm 00101bbb00101101FBBB111110111110.  */
+{ "dmachfr", 0x282D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachfr<.f><.cc> b,b,limm 00101bbb11101101FBBB1111100QQQQQ.  */
+{ "dmachfr", 0x28ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachfr<.f><.cc> 0,limm,c 0010111011101101F111CCCCCC0QQQQQ.  */
+{ "dmachfr", 0x2EED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachfr<.f> a,limm,u6 0010111001101101F111uuuuuuAAAAAA.  */
+{ "dmachfr", 0x2E6D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f> 0,limm,u6 0010111001101101F111uuuuuu111110.  */
+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f><.cc> 0,limm,u6 0010111011101101F111uuuuuu1QQQQQ.  */
+{ "dmachfr", 0x2EED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachfr<.f> 0,limm,s12 0010111010101101F111ssssssSSSSSS.  */
+{ "dmachfr", 0x2EAD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachfr<.f> a,limm,limm 0010111000101101F111111110AAAAAA.  */
+{ "dmachfr", 0x2E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachfr<.f> 0,limm,limm 0010111000101101F111111110111110.  */
+{ "dmachfr", 0x2E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachfr<.f><.cc> 0,limm,limm 0010111011101101F1111111100QQQQQ.  */
+{ "dmachfr", 0x2EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA.  */
+{ "dmachu", 0x28130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }},
+
+/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110.  */
+{ "dmachu", 0x2813003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ.  */
+{ "dmachu", 0x28D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA.  */
+{ "dmachu", 0x28530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110.  */
+{ "dmachu", 0x2853003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ.  */
+{ "dmachu", 0x28D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS.  */
+{ "dmachu", 0x28930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA.  */
+{ "dmachu", 0x2E137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }},
+
+/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA.  */
+{ "dmachu", 0x28130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }},
+
+/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110.  */
+{ "dmachu", 0x2E13703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110.  */
+{ "dmachu", 0x28130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ.  */
+{ "dmachu", 0x28D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ.  */
+{ "dmachu", 0x2ED37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA.  */
+{ "dmachu", 0x2E537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110.  */
+{ "dmachu", 0x2E53703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ.  */
+{ "dmachu", 0x2ED37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS.  */
+{ "dmachu", 0x2E937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA.  */
+{ "dmachu", 0x2E137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110.  */
+{ "dmachu", 0x2E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ.  */
+{ "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacpf<.f> a,b,c 00101bbb00111011FBBBCCCCCCAAAAAA.  */
+{ "dmacpf", 0x283B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmacpf<.f><.cc> b,b,c 00101bbb11111011FBBBCCCCCC0QQQQQ.  */
+{ "dmacpf", 0x28FB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacpf<.f> 0,b,c 00101bbb00111011FBBBCCCCCC111110.  */
+{ "dmacpf", 0x283B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmacpf<.f> a,b,limm 00101bbb00111011FBBB111110AAAAAA.  */
+{ "dmacpf", 0x283B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmacpf<.f><.cc> b,b,limm 00101bbb11111011FBBB1111100QQQQQ.  */
+{ "dmacpf", 0x28FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA.  */
+{ "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110.  */
+{ "dmacwh", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ.  */
+{ "dmacwh", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA.  */
+{ "dmacwh", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110.  */
+{ "dmacwh", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ.  */
+{ "dmacwh", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS.  */
+{ "dmacwh", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA.  */
+{ "dmacwh", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA.  */
+{ "dmacwh", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110.  */
+{ "dmacwh", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110.  */
+{ "dmacwh", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ.  */
+{ "dmacwh", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ.  */
+{ "dmacwh", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA.  */
+{ "dmacwh", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110.  */
+{ "dmacwh", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ.  */
+{ "dmacwh", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS.  */
+{ "dmacwh", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA.  */
+{ "dmacwh", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110.  */
+{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ.  */
+{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA.  */
+{ "dmacwhu", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110.  */
+{ "dmacwhu", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ.  */
+{ "dmacwhu", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA.  */
+{ "dmacwhu", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110.  */
+{ "dmacwhu", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ.  */
+{ "dmacwhu", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS.  */
+{ "dmacwhu", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA.  */
+{ "dmacwhu", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA.  */
+{ "dmacwhu", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110.  */
+{ "dmacwhu", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110.  */
+{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ.  */
+{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ.  */
+{ "dmacwhu", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA.  */
+{ "dmacwhu", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110.  */
+{ "dmacwhu", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ.  */
+{ "dmacwhu", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS.  */
+{ "dmacwhu", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA.  */
+{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110.  */
+{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ.  */
+{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmb u3 00100011011011110001RRRuuu111111.  */
+{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM3_23 }, { 0 }},
+
+/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA.  */
+{ "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }},
+
+/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110.  */
+{ "dmpyh", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ.  */
+{ "dmpyh", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA.  */
+{ "dmpyh", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110.  */
+{ "dmpyh", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ.  */
+{ "dmpyh", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS.  */
+{ "dmpyh", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA.  */
+{ "dmpyh", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA.  */
+{ "dmpyh", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110.  */
+{ "dmpyh", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110.  */
+{ "dmpyh", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ.  */
+{ "dmpyh", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ.  */
+{ "dmpyh", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA.  */
+{ "dmpyh", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110.  */
+{ "dmpyh", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ.  */
+{ "dmpyh", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS.  */
+{ "dmpyh", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA.  */
+{ "dmpyh", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110.  */
+{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ.  */
+{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA.  */
+{ "dmpyhbl", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmpyhbl<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110.  */
+{ "dmpyhbl", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhbl<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ.  */
+{ "dmpyhbl", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA.  */
+{ "dmpyhbl", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110.  */
+{ "dmpyhbl", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ.  */
+{ "dmpyhbl", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS.  */
+{ "dmpyhbl", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhbl<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA.  */
+{ "dmpyhbl", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyhbl<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA.  */
+{ "dmpyhbl", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyhbl<.f> 0,limm,c 0011011000010110F111CCCCCC111110.  */
+{ "dmpyhbl", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhbl<.f> 0,b,limm 00110bbb00010110FBBB111110111110.  */
+{ "dmpyhbl", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhbl<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ.  */
+{ "dmpyhbl", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhbl<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ.  */
+{ "dmpyhbl", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA.  */
+{ "dmpyhbl", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f> 0,limm,u6 0011011001010110F111uuuuuu111110.  */
+{ "dmpyhbl", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ.  */
+{ "dmpyhbl", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS.  */
+{ "dmpyhbl", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhbl<.f> a,limm,limm 0011011000010110F111111110AAAAAA.  */
+{ "dmpyhbl", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbl<.f> 0,limm,limm 0011011000010110F111111110111110.  */
+{ "dmpyhbl", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbl<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ.  */
+{ "dmpyhbl", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA.  */
+{ "dmpyhbm", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmpyhbm<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110.  */
+{ "dmpyhbm", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhbm<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ.  */
+{ "dmpyhbm", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA.  */
+{ "dmpyhbm", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110.  */
+{ "dmpyhbm", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ.  */
+{ "dmpyhbm", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS.  */
+{ "dmpyhbm", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhbm<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA.  */
+{ "dmpyhbm", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyhbm<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA.  */
+{ "dmpyhbm", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyhbm<.f> 0,limm,c 0011011000010111F111CCCCCC111110.  */
+{ "dmpyhbm", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhbm<.f> 0,b,limm 00110bbb00010111FBBB111110111110.  */
+{ "dmpyhbm", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhbm<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ.  */
+{ "dmpyhbm", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhbm<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ.  */
+{ "dmpyhbm", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA.  */
+{ "dmpyhbm", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f> 0,limm,u6 0011011001010111F111uuuuuu111110.  */
+{ "dmpyhbm", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ.  */
+{ "dmpyhbm", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS.  */
+{ "dmpyhbm", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhbm<.f> a,limm,limm 0011011000010111F111111110AAAAAA.  */
+{ "dmpyhbm", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbm<.f> 0,limm,limm 0011011000010111F111111110111110.  */
+{ "dmpyhbm", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbm<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ.  */
+{ "dmpyhbm", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhf<.f> a,b,c 00101bbb00101010FBBBCCCCCCAAAAAA.  */
+{ "dmpyhf", 0x282A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmpyhf<.f> 0,b,c 00101bbb00101010FBBBCCCCCC111110.  */
+{ "dmpyhf", 0x282A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhf<.f><.cc> b,b,c 00101bbb11101010FBBBCCCCCC0QQQQQ.  */
+{ "dmpyhf", 0x28EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhf<.f> a,b,u6 00101bbb01101010FBBBuuuuuuAAAAAA.  */
+{ "dmpyhf", 0x286A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f> 0,b,u6 00101bbb01101010FBBBuuuuuu111110.  */
+{ "dmpyhf", 0x286A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f><.cc> b,b,u6 00101bbb11101010FBBBuuuuuu1QQQQQ.  */
+{ "dmpyhf", 0x28EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhf<.f> b,b,s12 00101bbb10101010FBBBssssssSSSSSS.  */
+{ "dmpyhf", 0x28AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhf<.f> a,limm,c 0010111000101010F111CCCCCCAAAAAA.  */
+{ "dmpyhf", 0x2E2A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyhf<.f> a,b,limm 00101bbb00101010FBBB111110AAAAAA.  */
+{ "dmpyhf", 0x282A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyhf<.f> 0,limm,c 0010111001101010F111CCCCCC111110.  */
+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhf<.f> 0,b,limm 00101bbb00101010FBBB111110111110.  */
+{ "dmpyhf", 0x282A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhf<.f><.cc> b,b,limm 00101bbb11101010FBBB1111100QQQQQ.  */
+{ "dmpyhf", 0x28EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhf<.f><.cc> 0,limm,c 0010111011101010F111CCCCCC0QQQQQ.  */
+{ "dmpyhf", 0x2EEA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhf<.f> a,limm,u6 0010111001101010F111uuuuuuAAAAAA.  */
+{ "dmpyhf", 0x2E6A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f> 0,limm,u6 0010111001101010F111uuuuuu111110.  */
+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f><.cc> 0,limm,u6 0010111011101010F111uuuuuu1QQQQQ.  */
+{ "dmpyhf", 0x2EEA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhf<.f> 0,limm,s12 0010111010101010F111ssssssSSSSSS.  */
+{ "dmpyhf", 0x2EAA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhf<.f> a,limm,limm 0010111000101010F111111110AAAAAA.  */
+{ "dmpyhf", 0x2E2A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhf<.f> 0,limm,limm 0010111000101010F111111110111110.  */
+{ "dmpyhf", 0x2E2A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhf<.f><.cc> 0,limm,limm 0010111011101010F1111111100QQQQQ.  */
+{ "dmpyhf", 0x2EEA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA.  */
+{ "dmpyhfr", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmpyhfr<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110.  */
+{ "dmpyhfr", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhfr<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ.  */
+{ "dmpyhfr", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA.  */
+{ "dmpyhfr", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110.  */
+{ "dmpyhfr", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ.  */
+{ "dmpyhfr", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS.  */
+{ "dmpyhfr", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhfr<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA.  */
+{ "dmpyhfr", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyhfr<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA.  */
+{ "dmpyhfr", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyhfr<.f> 0,limm,c 0010111001101011F111CCCCCC111110.  */
+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhfr<.f> 0,b,limm 00101bbb00101011FBBB111110111110.  */
+{ "dmpyhfr", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhfr<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ.  */
+{ "dmpyhfr", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhfr<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ.  */
+{ "dmpyhfr", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA.  */
+{ "dmpyhfr", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f> 0,limm,u6 0010111001101011F111uuuuuu111110.  */
+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ.  */
+{ "dmpyhfr", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS.  */
+{ "dmpyhfr", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhfr<.f> a,limm,limm 0010111000101011F111111110AAAAAA.  */
+{ "dmpyhfr", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhfr<.f> 0,limm,limm 0010111000101011F111111110111110.  */
+{ "dmpyhfr", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhfr<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ.  */
+{ "dmpyhfr", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA.  */
+{ "dmpyhu", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }},
+
+/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110.  */
+{ "dmpyhu", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ.  */
+{ "dmpyhu", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA.  */
+{ "dmpyhu", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110.  */
+{ "dmpyhu", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ.  */
+{ "dmpyhu", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS.  */
+{ "dmpyhu", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA.  */
+{ "dmpyhu", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA.  */
+{ "dmpyhu", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110.  */
+{ "dmpyhu", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110.  */
+{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ.  */
+{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ.  */
+{ "dmpyhu", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA.  */
+{ "dmpyhu", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110.  */
+{ "dmpyhu", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ.  */
+{ "dmpyhu", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS.  */
+{ "dmpyhu", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA.  */
+{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110.  */
+{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ.  */
+{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA.  */
+{ "dmpyhwf", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmpyhwf<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110.  */
+{ "dmpyhwf", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhwf<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ.  */
+{ "dmpyhwf", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA.  */
+{ "dmpyhwf", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110.  */
+{ "dmpyhwf", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ.  */
+{ "dmpyhwf", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS.  */
+{ "dmpyhwf", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhwf<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA.  */
+{ "dmpyhwf", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* dmpyhwf<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA.  */
+{ "dmpyhwf", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmpyhwf<.f> 0,limm,c 0010111001101000F111CCCCCC111110.  */
+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhwf<.f> 0,b,limm 00101bbb00101000FBBB111110111110.  */
+{ "dmpyhwf", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhwf<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ.  */
+{ "dmpyhwf", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhwf<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ.  */
+{ "dmpyhwf", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA.  */
+{ "dmpyhwf", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f> 0,limm,u6 0010111001101000F111uuuuuu111110.  */
+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ.  */
+{ "dmpyhwf", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS.  */
+{ "dmpyhwf", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhwf<.f> a,limm,limm 0010111000101000F111111110AAAAAA.  */
+{ "dmpyhwf", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhwf<.f> 0,limm,limm 0010111000101000F111111110111110.  */
+{ "dmpyhwf", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhwf<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ.  */
+{ "dmpyhwf", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA.  */
+{ "dmpywh", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110.  */
+{ "dmpywh", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ.  */
+{ "dmpywh", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA.  */
+{ "dmpywh", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110.  */
+{ "dmpywh", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ.  */
+{ "dmpywh", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS.  */
+{ "dmpywh", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA.  */
+{ "dmpywh", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA.  */
+{ "dmpywh", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110.  */
+{ "dmpywh", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110.  */
+{ "dmpywh", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ.  */
+{ "dmpywh", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ.  */
+{ "dmpywh", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA.  */
+{ "dmpywh", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110.  */
+{ "dmpywh", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ.  */
+{ "dmpywh", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS.  */
+{ "dmpywh", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA.  */
+{ "dmpywh", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110.  */
+{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ.  */
+{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA.  */
+{ "dmpywhu", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110.  */
+{ "dmpywhu", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ.  */
+{ "dmpywhu", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA.  */
+{ "dmpywhu", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110.  */
+{ "dmpywhu", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ.  */
+{ "dmpywhu", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS.  */
+{ "dmpywhu", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA.  */
+{ "dmpywhu", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA.  */
+{ "dmpywhu", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110.  */
+{ "dmpywhu", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110.  */
+{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ.  */
+{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ.  */
+{ "dmpywhu", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA.  */
+{ "dmpywhu", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110.  */
+{ "dmpywhu", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ.  */
+{ "dmpywhu", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS.  */
+{ "dmpywhu", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA.  */
+{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110.  */
+{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ.  */
+{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,b,c 00110bbb00001000FBBBCCCCCCAAAAAA.  */
+{ "dmulh11", 0x30080000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh11<.f> 0,b,c 00110bbb00001000FBBBCCCCCC111110.  */
+{ "dmulh11", 0x3008003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh11<.f><.cc> b,b,c 00110bbb11001000FBBBCCCCCC0QQQQQ.  */
+{ "dmulh11", 0x30C80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,b,c 00110bbb00110000FBBBCCCCCCAAAAAA.  */
+{ "dmulh11", 0x30300000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh11<.f> 0,b,c 00110bbb00110000FBBBCCCCCC111110.  */
+{ "dmulh11", 0x3030003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh11<.f><.cc> b,b,c 00110bbb11110000FBBBCCCCCC0QQQQQ.  */
+{ "dmulh11", 0x30F00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,b,u6 00110bbb01001000FBBBuuuuuuAAAAAA.  */
+{ "dmulh11", 0x30480000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f> 0,b,u6 00110bbb01001000FBBBuuuuuu111110.  */
+{ "dmulh11", 0x3048003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f><.cc> b,b,u6 00110bbb11001000FBBBuuuuuu1QQQQQ.  */
+{ "dmulh11", 0x30C80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,b,u6 00110bbb01110000FBBBuuuuuuAAAAAA.  */
+{ "dmulh11", 0x30700000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f> 0,b,u6 00110bbb01110000FBBBuuuuuu111110.  */
+{ "dmulh11", 0x3070003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f><.cc> b,b,u6 00110bbb11110000FBBBuuuuuu1QQQQQ.  */
+{ "dmulh11", 0x30F00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh11<.f> b,b,s12 00110bbb10001000FBBBssssssSSSSSS.  */
+{ "dmulh11", 0x30880000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh11<.f> b,b,s12 00110bbb10110000FBBBssssssSSSSSS.  */
+{ "dmulh11", 0x30B00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh11<.f> a,limm,c 0011011000001000F111CCCCCCAAAAAA.  */
+{ "dmulh11", 0x36087000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh11<.f> a,b,limm 00110bbb00001000FBBB111110AAAAAA.  */
+{ "dmulh11", 0x30080F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh11<.f> 0,limm,c 0011011000001000F111CCCCCC111110.  */
+{ "dmulh11", 0x3608703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh11<.f> 0,b,limm 00110bbb00001000FBBB111110111110.  */
+{ "dmulh11", 0x30080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh11<.f><.cc> 0,limm,c 0011011011001000F111CCCCCC0QQQQQ.  */
+{ "dmulh11", 0x36C87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh11<.f><.cc> b,b,limm 00110bbb11001000FBBB1111100QQQQQ.  */
+{ "dmulh11", 0x30C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,limm,c 0011011000110000F111CCCCCCAAAAAA.  */
+{ "dmulh11", 0x36307000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh11<.f> a,b,limm 00110bbb00110000FBBB111110AAAAAA.  */
+{ "dmulh11", 0x30300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh11<.f> 0,limm,c 0011011000110000F111CCCCCC111110.  */
+{ "dmulh11", 0x3630703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh11<.f> 0,b,limm 00110bbb00110000FBBB111110111110.  */
+{ "dmulh11", 0x30300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh11<.f><.cc> 0,limm,c 0011011011110000F111CCCCCC0QQQQQ.  */
+{ "dmulh11", 0x36F07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh11<.f><.cc> b,b,limm 00110bbb11110000FBBB1111100QQQQQ.  */
+{ "dmulh11", 0x30F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,limm,u6 0011011001001000F111uuuuuuAAAAAA.  */
+{ "dmulh11", 0x36487000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f> 0,limm,u6 0011011001001000F111uuuuuu111110.  */
+{ "dmulh11", 0x3648703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f><.cc> 0,limm,u6 0011011011001000F111uuuuuu1QQQQQ.  */
+{ "dmulh11", 0x36C87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,limm,u6 0011011001110000F111uuuuuuAAAAAA.  */
+{ "dmulh11", 0x36707000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f> 0,limm,u6 0011011001110000F111uuuuuu111110.  */
+{ "dmulh11", 0x3670703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh11<.f><.cc> 0,limm,u6 0011011011110000F111uuuuuu1QQQQQ.  */
+{ "dmulh11", 0x36F07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh11<.f> 0,limm,s12 0011011010001000F111ssssssSSSSSS.  */
+{ "dmulh11", 0x36887000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh11<.f> 0,limm,s12 0011011010110000F111ssssssSSSSSS.  */
+{ "dmulh11", 0x36B07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh11<.f> a,limm,limm 0011011000001000F111111110AAAAAA.  */
+{ "dmulh11", 0x36087F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh11<.f> 0,limm,limm 0011011000001000F111111110111110.  */
+{ "dmulh11", 0x36087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh11<.f><.cc> 0,limm,limm 0011011011001000F1111111100QQQQQ.  */
+{ "dmulh11", 0x36C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh11<.f> a,limm,limm 0011011000110000F111111110AAAAAA.  */
+{ "dmulh11", 0x36307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh11<.f> 0,limm,limm 0011011000110000F111111110111110.  */
+{ "dmulh11", 0x36307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh11<.f><.cc> 0,limm,limm 0011011011110000F1111111100QQQQQ.  */
+{ "dmulh11", 0x36F07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,b,c 00110bbb00001001FBBBCCCCCCAAAAAA.  */
+{ "dmulh12", 0x30090000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh12<.f> 0,b,c 00110bbb00001001FBBBCCCCCC111110.  */
+{ "dmulh12", 0x3009003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh12<.f><.cc> b,b,c 00110bbb11001001FBBBCCCCCC0QQQQQ.  */
+{ "dmulh12", 0x30C90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA.  */
+{ "dmulh12", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh12<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110.  */
+{ "dmulh12", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh12<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ.  */
+{ "dmulh12", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,b,u6 00110bbb01001001FBBBuuuuuuAAAAAA.  */
+{ "dmulh12", 0x30490000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f> 0,b,u6 00110bbb01001001FBBBuuuuuu111110.  */
+{ "dmulh12", 0x3049003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f><.cc> b,b,u6 00110bbb11001001FBBBuuuuuu1QQQQQ.  */
+{ "dmulh12", 0x30C90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA.  */
+{ "dmulh12", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110.  */
+{ "dmulh12", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ.  */
+{ "dmulh12", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh12<.f> b,b,s12 00110bbb10001001FBBBssssssSSSSSS.  */
+{ "dmulh12", 0x30890000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh12<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS.  */
+{ "dmulh12", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh12<.f> a,limm,c 0011011000001001F111CCCCCCAAAAAA.  */
+{ "dmulh12", 0x36097000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh12<.f> a,b,limm 00110bbb00001001FBBB111110AAAAAA.  */
+{ "dmulh12", 0x30090F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh12<.f> 0,limm,c 0011011000001001F111CCCCCC111110.  */
+{ "dmulh12", 0x3609703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh12<.f> 0,b,limm 00110bbb00001001FBBB111110111110.  */
+{ "dmulh12", 0x30090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh12<.f><.cc> 0,limm,c 0011011011001001F111CCCCCC0QQQQQ.  */
+{ "dmulh12", 0x36C97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh12<.f><.cc> b,b,limm 00110bbb11001001FBBB1111100QQQQQ.  */
+{ "dmulh12", 0x30C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA.  */
+{ "dmulh12", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh12<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA.  */
+{ "dmulh12", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh12<.f> 0,limm,c 0011011000110001F111CCCCCC111110.  */
+{ "dmulh12", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh12<.f> 0,b,limm 00110bbb00110001FBBB111110111110.  */
+{ "dmulh12", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh12<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ.  */
+{ "dmulh12", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh12<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ.  */
+{ "dmulh12", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,limm,u6 0011011001001001F111uuuuuuAAAAAA.  */
+{ "dmulh12", 0x36497000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f> 0,limm,u6 0011011001001001F111uuuuuu111110.  */
+{ "dmulh12", 0x3649703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f><.cc> 0,limm,u6 0011011011001001F111uuuuuu1QQQQQ.  */
+{ "dmulh12", 0x36C97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA.  */
+{ "dmulh12", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f> 0,limm,u6 0011011001110001F111uuuuuu111110.  */
+{ "dmulh12", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh12<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ.  */
+{ "dmulh12", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh12<.f> 0,limm,s12 0011011010001001F111ssssssSSSSSS.  */
+{ "dmulh12", 0x36897000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh12<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS.  */
+{ "dmulh12", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh12<.f> a,limm,limm 0011011000001001F111111110AAAAAA.  */
+{ "dmulh12", 0x36097F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh12<.f> 0,limm,limm 0011011000001001F111111110111110.  */
+{ "dmulh12", 0x36097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh12<.f><.cc> 0,limm,limm 0011011011001001F1111111100QQQQQ.  */
+{ "dmulh12", 0x36C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh12<.f> a,limm,limm 0011011000110001F111111110AAAAAA.  */
+{ "dmulh12", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh12<.f> 0,limm,limm 0011011000110001F111111110111110.  */
+{ "dmulh12", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh12<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ.  */
+{ "dmulh12", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA.  */
+{ "dmulh21", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh21<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110.  */
+{ "dmulh21", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh21<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ.  */
+{ "dmulh21", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,b,c 00110bbb00110010FBBBCCCCCCAAAAAA.  */
+{ "dmulh21", 0x30320000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh21<.f> 0,b,c 00110bbb00110010FBBBCCCCCC111110.  */
+{ "dmulh21", 0x3032003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh21<.f><.cc> b,b,c 00110bbb11110010FBBBCCCCCC0QQQQQ.  */
+{ "dmulh21", 0x30F20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA.  */
+{ "dmulh21", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110.  */
+{ "dmulh21", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ.  */
+{ "dmulh21", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,b,u6 00110bbb01110010FBBBuuuuuuAAAAAA.  */
+{ "dmulh21", 0x30720000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f> 0,b,u6 00110bbb01110010FBBBuuuuuu111110.  */
+{ "dmulh21", 0x3072003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f><.cc> b,b,u6 00110bbb11110010FBBBuuuuuu1QQQQQ.  */
+{ "dmulh21", 0x30F20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh21<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS.  */
+{ "dmulh21", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh21<.f> b,b,s12 00110bbb10110010FBBBssssssSSSSSS.  */
+{ "dmulh21", 0x30B20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh21<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA.  */
+{ "dmulh21", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh21<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA.  */
+{ "dmulh21", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh21<.f> 0,limm,c 0011011000001010F111CCCCCC111110.  */
+{ "dmulh21", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh21<.f> 0,b,limm 00110bbb00001010FBBB111110111110.  */
+{ "dmulh21", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh21<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ.  */
+{ "dmulh21", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh21<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ.  */
+{ "dmulh21", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,limm,c 0011011000110010F111CCCCCCAAAAAA.  */
+{ "dmulh21", 0x36327000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh21<.f> a,b,limm 00110bbb00110010FBBB111110AAAAAA.  */
+{ "dmulh21", 0x30320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh21<.f> 0,limm,c 0011011000110010F111CCCCCC111110.  */
+{ "dmulh21", 0x3632703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh21<.f> 0,b,limm 00110bbb00110010FBBB111110111110.  */
+{ "dmulh21", 0x30320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh21<.f><.cc> 0,limm,c 0011011011110010F111CCCCCC0QQQQQ.  */
+{ "dmulh21", 0x36F27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh21<.f><.cc> b,b,limm 00110bbb11110010FBBB1111100QQQQQ.  */
+{ "dmulh21", 0x30F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA.  */
+{ "dmulh21", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f> 0,limm,u6 0011011001001010F111uuuuuu111110.  */
+{ "dmulh21", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ.  */
+{ "dmulh21", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,limm,u6 0011011001110010F111uuuuuuAAAAAA.  */
+{ "dmulh21", 0x36727000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f> 0,limm,u6 0011011001110010F111uuuuuu111110.  */
+{ "dmulh21", 0x3672703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh21<.f><.cc> 0,limm,u6 0011011011110010F111uuuuuu1QQQQQ.  */
+{ "dmulh21", 0x36F27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh21<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS.  */
+{ "dmulh21", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh21<.f> 0,limm,s12 0011011010110010F111ssssssSSSSSS.  */
+{ "dmulh21", 0x36B27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh21<.f> a,limm,limm 0011011000001010F111111110AAAAAA.  */
+{ "dmulh21", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh21<.f> 0,limm,limm 0011011000001010F111111110111110.  */
+{ "dmulh21", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh21<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ.  */
+{ "dmulh21", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh21<.f> a,limm,limm 0011011000110010F111111110AAAAAA.  */
+{ "dmulh21", 0x36327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh21<.f> 0,limm,limm 0011011000110010F111111110111110.  */
+{ "dmulh21", 0x36327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh21<.f><.cc> 0,limm,limm 0011011011110010F1111111100QQQQQ.  */
+{ "dmulh21", 0x36F27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA.  */
+{ "dmulh22", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh22<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110.  */
+{ "dmulh22", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh22<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ.  */
+{ "dmulh22", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA.  */
+{ "dmulh22", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dmulh22<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110.  */
+{ "dmulh22", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dmulh22<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ.  */
+{ "dmulh22", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA.  */
+{ "dmulh22", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110.  */
+{ "dmulh22", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ.  */
+{ "dmulh22", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA.  */
+{ "dmulh22", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110.  */
+{ "dmulh22", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ.  */
+{ "dmulh22", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh22<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS.  */
+{ "dmulh22", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh22<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS.  */
+{ "dmulh22", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmulh22<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA.  */
+{ "dmulh22", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh22<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA.  */
+{ "dmulh22", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh22<.f> 0,limm,c 0011011000001011F111CCCCCC111110.  */
+{ "dmulh22", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh22<.f> 0,b,limm 00110bbb00001011FBBB111110111110.  */
+{ "dmulh22", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh22<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ.  */
+{ "dmulh22", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh22<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ.  */
+{ "dmulh22", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA.  */
+{ "dmulh22", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dmulh22<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA.  */
+{ "dmulh22", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dmulh22<.f> 0,limm,c 0011011000110011F111CCCCCC111110.  */
+{ "dmulh22", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dmulh22<.f> 0,b,limm 00110bbb00110011FBBB111110111110.  */
+{ "dmulh22", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dmulh22<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ.  */
+{ "dmulh22", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmulh22<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ.  */
+{ "dmulh22", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA.  */
+{ "dmulh22", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f> 0,limm,u6 0011011001001011F111uuuuuu111110.  */
+{ "dmulh22", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ.  */
+{ "dmulh22", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA.  */
+{ "dmulh22", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f> 0,limm,u6 0011011001110011F111uuuuuu111110.  */
+{ "dmulh22", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmulh22<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ.  */
+{ "dmulh22", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmulh22<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS.  */
+{ "dmulh22", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh22<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS.  */
+{ "dmulh22", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmulh22<.f> a,limm,limm 0011011000001011F111111110AAAAAA.  */
+{ "dmulh22", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh22<.f> 0,limm,limm 0011011000001011F111111110111110.  */
+{ "dmulh22", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh22<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ.  */
+{ "dmulh22", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulh22<.f> a,limm,limm 0011011000110011F111111110AAAAAA.  */
+{ "dmulh22", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh22<.f> 0,limm,limm 0011011000110011F111111110111110.  */
+{ "dmulh22", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmulh22<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ.  */
+{ "dmulh22", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmulpf<.f> a,b,c 00101bbb00111010FBBBCCCCCCAAAAAA.  */
+{ "dmulpf", 0x283A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* dmulpf<.f><.cc> b,b,c 00101bbb11111010FBBBCCCCCC0QQQQQ.  */
+{ "dmulpf", 0x28FA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dmulpf<.f> 0,b,c 00101bbb00111010FBBBCCCCCC111110.  */
+{ "dmulpf", 0x283A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmulpf<.f> a,b,limm 00101bbb00111010FBBB111110AAAAAA.  */
+{ "dmulpf", 0x283A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* dmulpf<.f><.cc> b,b,limm 00101bbb11111010FBBB1111100QQQQQ.  */
+{ "dmulpf", 0x28FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* drsubh11<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA.  */
+{ "drsubh11", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* drsubh11<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110.  */
+{ "drsubh11", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* drsubh11<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ.  */
+{ "drsubh11", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* drsubh11<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA.  */
+{ "drsubh11", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh11<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110.  */
+{ "drsubh11", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh11<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ.  */
+{ "drsubh11", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh11<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS.  */
+{ "drsubh11", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* drsubh11<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA.  */
+{ "drsubh11", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* drsubh11<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA.  */
+{ "drsubh11", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* drsubh11<.f> 0,limm,c 0011011000010100F111CCCCCC111110.  */
+{ "drsubh11", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* drsubh11<.f> 0,b,limm 00110bbb00010100FBBB111110111110.  */
+{ "drsubh11", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* drsubh11<.f><.cc> 0,limm,c 0011011011010100F111CCCCCC0QQQQQ.  */
+{ "drsubh11", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* drsubh11<.f><.cc> b,b,limm 00110bbb11010100FBBB1111100QQQQQ.  */
+{ "drsubh11", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* drsubh11<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA.  */
+{ "drsubh11", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh11<.f> 0,limm,u6 0011011001010100F111uuuuuu111110.  */
+{ "drsubh11", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh11<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ.  */
+{ "drsubh11", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh11<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS.  */
+{ "drsubh11", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* drsubh11<.f> a,limm,limm 0011011000010100F111111110AAAAAA.  */
+{ "drsubh11", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh11<.f> 0,limm,limm 0011011000010100F111111110111110.  */
+{ "drsubh11", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh11<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ.  */
+{ "drsubh11", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* drsubh12<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA.  */
+{ "drsubh12", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* drsubh12<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110.  */
+{ "drsubh12", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* drsubh12<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ.  */
+{ "drsubh12", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* drsubh12<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA.  */
+{ "drsubh12", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh12<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110.  */
+{ "drsubh12", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh12<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ.  */
+{ "drsubh12", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh12<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS.  */
+{ "drsubh12", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* drsubh12<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA.  */
+{ "drsubh12", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* drsubh12<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA.  */
+{ "drsubh12", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* drsubh12<.f> 0,limm,c 0011011000010101F111CCCCCC111110.  */
+{ "drsubh12", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* drsubh12<.f> 0,b,limm 00110bbb00010101FBBB111110111110.  */
+{ "drsubh12", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* drsubh12<.f><.cc> 0,limm,c 0011011011010101F111CCCCCC0QQQQQ.  */
+{ "drsubh12", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* drsubh12<.f><.cc> b,b,limm 00110bbb11010101FBBB1111100QQQQQ.  */
+{ "drsubh12", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* drsubh12<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA.  */
+{ "drsubh12", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh12<.f> 0,limm,u6 0011011001010101F111uuuuuu111110.  */
+{ "drsubh12", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh12<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ.  */
+{ "drsubh12", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh12<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS.  */
+{ "drsubh12", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* drsubh12<.f> a,limm,limm 0011011000010101F111111110AAAAAA.  */
+{ "drsubh12", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh12<.f> 0,limm,limm 0011011000010101F111111110111110.  */
+{ "drsubh12", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh12<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ.  */
+{ "drsubh12", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* drsubh21<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA.  */
+{ "drsubh21", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* drsubh21<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110.  */
+{ "drsubh21", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* drsubh21<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ.  */
+{ "drsubh21", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* drsubh21<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA.  */
+{ "drsubh21", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh21<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110.  */
+{ "drsubh21", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh21<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ.  */
+{ "drsubh21", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh21<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS.  */
+{ "drsubh21", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* drsubh21<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA.  */
+{ "drsubh21", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* drsubh21<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA.  */
+{ "drsubh21", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* drsubh21<.f> 0,limm,c 0011011000010110F111CCCCCC111110.  */
+{ "drsubh21", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* drsubh21<.f> 0,b,limm 00110bbb00010110FBBB111110111110.  */
+{ "drsubh21", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* drsubh21<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ.  */
+{ "drsubh21", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* drsubh21<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ.  */
+{ "drsubh21", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* drsubh21<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA.  */
+{ "drsubh21", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh21<.f> 0,limm,u6 0011011001010110F111uuuuuu111110.  */
+{ "drsubh21", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh21<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ.  */
+{ "drsubh21", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh21<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS.  */
+{ "drsubh21", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* drsubh21<.f> a,limm,limm 0011011000010110F111111110AAAAAA.  */
+{ "drsubh21", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh21<.f> 0,limm,limm 0011011000010110F111111110111110.  */
+{ "drsubh21", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh21<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ.  */
+{ "drsubh21", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* drsubh22<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA.  */
+{ "drsubh22", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* drsubh22<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110.  */
+{ "drsubh22", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* drsubh22<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ.  */
+{ "drsubh22", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* drsubh22<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA.  */
+{ "drsubh22", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh22<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110.  */
+{ "drsubh22", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* drsubh22<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ.  */
+{ "drsubh22", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh22<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS.  */
+{ "drsubh22", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* drsubh22<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA.  */
+{ "drsubh22", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* drsubh22<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA.  */
+{ "drsubh22", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* drsubh22<.f> 0,limm,c 0011011000010111F111CCCCCC111110.  */
+{ "drsubh22", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* drsubh22<.f> 0,b,limm 00110bbb00010111FBBB111110111110.  */
+{ "drsubh22", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* drsubh22<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ.  */
+{ "drsubh22", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* drsubh22<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ.  */
+{ "drsubh22", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* drsubh22<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA.  */
+{ "drsubh22", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh22<.f> 0,limm,u6 0011011001010111F111uuuuuu111110.  */
+{ "drsubh22", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* drsubh22<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ.  */
+{ "drsubh22", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* drsubh22<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS.  */
+{ "drsubh22", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* drsubh22<.f> a,limm,limm 0011011000010111F111111110AAAAAA.  */
+{ "drsubh22", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh22<.f> 0,limm,limm 0011011000010111F111111110111110.  */
+{ "drsubh22", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* drsubh22<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ.  */
+{ "drsubh22", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA.  */
+{ "dsubh11", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh11<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110.  */
+{ "dsubh11", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh11<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ.  */
+{ "dsubh11", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,b,c 00110bbb00111000FBBBCCCCCCAAAAAA.  */
+{ "dsubh11", 0x30380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh11<.f> 0,b,c 00110bbb00111000FBBBCCCCCC111110.  */
+{ "dsubh11", 0x3038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh11<.f><.cc> b,b,c 00110bbb11111000FBBBCCCCCC0QQQQQ.  */
+{ "dsubh11", 0x30F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA.  */
+{ "dsubh11", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110.  */
+{ "dsubh11", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ.  */
+{ "dsubh11", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,b,u6 00110bbb01111000FBBBuuuuuuAAAAAA.  */
+{ "dsubh11", 0x30780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f> 0,b,u6 00110bbb01111000FBBBuuuuuu111110.  */
+{ "dsubh11", 0x3078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f><.cc> b,b,u6 00110bbb11111000FBBBuuuuuu1QQQQQ.  */
+{ "dsubh11", 0x30F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh11<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS.  */
+{ "dsubh11", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh11<.f> b,b,s12 00110bbb10111000FBBBssssssSSSSSS.  */
+{ "dsubh11", 0x30B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh11<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA.  */
+{ "dsubh11", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh11<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA.  */
+{ "dsubh11", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh11<.f> 0,limm,c 0011011000010000F111CCCCCC111110.  */
+{ "dsubh11", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh11<.f> 0,b,limm 00110bbb00010000FBBB111110111110.  */
+{ "dsubh11", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh11<.f><.cc> 0,limm,c 0011011011010000F111CCCCCC0QQQQQ.  */
+{ "dsubh11", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh11<.f><.cc> b,b,limm 00110bbb11010000FBBB1111100QQQQQ.  */
+{ "dsubh11", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,limm,c 0011011000111000F111CCCCCCAAAAAA.  */
+{ "dsubh11", 0x36387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh11<.f> a,b,limm 00110bbb00111000FBBB111110AAAAAA.  */
+{ "dsubh11", 0x30380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh11<.f> 0,limm,c 0011011000111000F111CCCCCC111110.  */
+{ "dsubh11", 0x3638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh11<.f> 0,b,limm 00110bbb00111000FBBB111110111110.  */
+{ "dsubh11", 0x30380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh11<.f><.cc> 0,limm,c 0011011011111000F111CCCCCC0QQQQQ.  */
+{ "dsubh11", 0x36F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh11<.f><.cc> b,b,limm 00110bbb11111000FBBB1111100QQQQQ.  */
+{ "dsubh11", 0x30F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA.  */
+{ "dsubh11", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f> 0,limm,u6 0011011001010000F111uuuuuu111110.  */
+{ "dsubh11", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ.  */
+{ "dsubh11", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,limm,u6 0011011001111000F111uuuuuuAAAAAA.  */
+{ "dsubh11", 0x36787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f> 0,limm,u6 0011011001111000F111uuuuuu111110.  */
+{ "dsubh11", 0x3678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh11<.f><.cc> 0,limm,u6 0011011011111000F111uuuuuu1QQQQQ.  */
+{ "dsubh11", 0x36F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh11<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS.  */
+{ "dsubh11", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh11<.f> 0,limm,s12 0011011010111000F111ssssssSSSSSS.  */
+{ "dsubh11", 0x36B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh11<.f> a,limm,limm 0011011000010000F111111110AAAAAA.  */
+{ "dsubh11", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh11<.f> 0,limm,limm 0011011000010000F111111110111110.  */
+{ "dsubh11", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh11<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ.  */
+{ "dsubh11", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh11<.f> a,limm,limm 0011011000111000F111111110AAAAAA.  */
+{ "dsubh11", 0x36387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh11<.f> 0,limm,limm 0011011000111000F111111110111110.  */
+{ "dsubh11", 0x36387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh11<.f><.cc> 0,limm,limm 0011011011111000F1111111100QQQQQ.  */
+{ "dsubh11", 0x36F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,b,c 00110bbb00010001FBBBCCCCCCAAAAAA.  */
+{ "dsubh12", 0x30110000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh12<.f> 0,b,c 00110bbb00010001FBBBCCCCCC111110.  */
+{ "dsubh12", 0x3011003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh12<.f><.cc> b,b,c 00110bbb11010001FBBBCCCCCC0QQQQQ.  */
+{ "dsubh12", 0x30D10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,b,c 00110bbb00111001FBBBCCCCCCAAAAAA.  */
+{ "dsubh12", 0x30390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh12<.f> 0,b,c 00110bbb00111001FBBBCCCCCC111110.  */
+{ "dsubh12", 0x3039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh12<.f><.cc> b,b,c 00110bbb11111001FBBBCCCCCC0QQQQQ.  */
+{ "dsubh12", 0x30F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,b,u6 00110bbb01010001FBBBuuuuuuAAAAAA.  */
+{ "dsubh12", 0x30510000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f> 0,b,u6 00110bbb01010001FBBBuuuuuu111110.  */
+{ "dsubh12", 0x3051003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f><.cc> b,b,u6 00110bbb11010001FBBBuuuuuu1QQQQQ.  */
+{ "dsubh12", 0x30D10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,b,u6 00110bbb01111001FBBBuuuuuuAAAAAA.  */
+{ "dsubh12", 0x30790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f> 0,b,u6 00110bbb01111001FBBBuuuuuu111110.  */
+{ "dsubh12", 0x3079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f><.cc> b,b,u6 00110bbb11111001FBBBuuuuuu1QQQQQ.  */
+{ "dsubh12", 0x30F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh12<.f> b,b,s12 00110bbb10010001FBBBssssssSSSSSS.  */
+{ "dsubh12", 0x30910000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh12<.f> b,b,s12 00110bbb10111001FBBBssssssSSSSSS.  */
+{ "dsubh12", 0x30B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh12<.f> a,limm,c 0011011000010001F111CCCCCCAAAAAA.  */
+{ "dsubh12", 0x36117000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh12<.f> a,b,limm 00110bbb00010001FBBB111110AAAAAA.  */
+{ "dsubh12", 0x30110F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh12<.f> 0,limm,c 0011011000010001F111CCCCCC111110.  */
+{ "dsubh12", 0x3611703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh12<.f> 0,b,limm 00110bbb00010001FBBB111110111110.  */
+{ "dsubh12", 0x30110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh12<.f><.cc> 0,limm,c 0011011011010001F111CCCCCC0QQQQQ.  */
+{ "dsubh12", 0x36D17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh12<.f><.cc> b,b,limm 00110bbb11010001FBBB1111100QQQQQ.  */
+{ "dsubh12", 0x30D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,limm,c 0011011000111001F111CCCCCCAAAAAA.  */
+{ "dsubh12", 0x36397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh12<.f> a,b,limm 00110bbb00111001FBBB111110AAAAAA.  */
+{ "dsubh12", 0x30390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh12<.f> 0,limm,c 0011011000111001F111CCCCCC111110.  */
+{ "dsubh12", 0x3639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh12<.f> 0,b,limm 00110bbb00111001FBBB111110111110.  */
+{ "dsubh12", 0x30390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh12<.f><.cc> 0,limm,c 0011011011111001F111CCCCCC0QQQQQ.  */
+{ "dsubh12", 0x36F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh12<.f><.cc> b,b,limm 00110bbb11111001FBBB1111100QQQQQ.  */
+{ "dsubh12", 0x30F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,limm,u6 0011011001010001F111uuuuuuAAAAAA.  */
+{ "dsubh12", 0x36517000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f> 0,limm,u6 0011011001010001F111uuuuuu111110.  */
+{ "dsubh12", 0x3651703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f><.cc> 0,limm,u6 0011011011010001F111uuuuuu1QQQQQ.  */
+{ "dsubh12", 0x36D17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,limm,u6 0011011001111001F111uuuuuuAAAAAA.  */
+{ "dsubh12", 0x36797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f> 0,limm,u6 0011011001111001F111uuuuuu111110.  */
+{ "dsubh12", 0x3679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh12<.f><.cc> 0,limm,u6 0011011011111001F111uuuuuu1QQQQQ.  */
+{ "dsubh12", 0x36F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh12<.f> 0,limm,s12 0011011010010001F111ssssssSSSSSS.  */
+{ "dsubh12", 0x36917000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh12<.f> 0,limm,s12 0011011010111001F111ssssssSSSSSS.  */
+{ "dsubh12", 0x36B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh12<.f> a,limm,limm 0011011000010001F111111110AAAAAA.  */
+{ "dsubh12", 0x36117F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh12<.f> 0,limm,limm 0011011000010001F111111110111110.  */
+{ "dsubh12", 0x36117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh12<.f><.cc> 0,limm,limm 0011011011010001F1111111100QQQQQ.  */
+{ "dsubh12", 0x36D17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh12<.f> a,limm,limm 0011011000111001F111111110AAAAAA.  */
+{ "dsubh12", 0x36397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh12<.f> 0,limm,limm 0011011000111001F111111110111110.  */
+{ "dsubh12", 0x36397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh12<.f><.cc> 0,limm,limm 0011011011111001F1111111100QQQQQ.  */
+{ "dsubh12", 0x36F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA.  */
+{ "dsubh21", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh21<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110.  */
+{ "dsubh21", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh21<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ.  */
+{ "dsubh21", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,b,c 00110bbb00111010FBBBCCCCCCAAAAAA.  */
+{ "dsubh21", 0x303A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh21<.f> 0,b,c 00110bbb00111010FBBBCCCCCC111110.  */
+{ "dsubh21", 0x303A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh21<.f><.cc> b,b,c 00110bbb11111010FBBBCCCCCC0QQQQQ.  */
+{ "dsubh21", 0x30FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA.  */
+{ "dsubh21", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110.  */
+{ "dsubh21", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ.  */
+{ "dsubh21", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,b,u6 00110bbb01111010FBBBuuuuuuAAAAAA.  */
+{ "dsubh21", 0x307A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f> 0,b,u6 00110bbb01111010FBBBuuuuuu111110.  */
+{ "dsubh21", 0x307A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f><.cc> b,b,u6 00110bbb11111010FBBBuuuuuu1QQQQQ.  */
+{ "dsubh21", 0x30FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh21<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS.  */
+{ "dsubh21", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh21<.f> b,b,s12 00110bbb10111010FBBBssssssSSSSSS.  */
+{ "dsubh21", 0x30BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh21<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA.  */
+{ "dsubh21", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh21<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA.  */
+{ "dsubh21", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh21<.f> 0,limm,c 0011011000010010F111CCCCCC111110.  */
+{ "dsubh21", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh21<.f> 0,b,limm 00110bbb00010010FBBB111110111110.  */
+{ "dsubh21", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh21<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ.  */
+{ "dsubh21", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh21<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ.  */
+{ "dsubh21", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,limm,c 0011011000111010F111CCCCCCAAAAAA.  */
+{ "dsubh21", 0x363A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh21<.f> a,b,limm 00110bbb00111010FBBB111110AAAAAA.  */
+{ "dsubh21", 0x303A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh21<.f> 0,limm,c 0011011000111010F111CCCCCC111110.  */
+{ "dsubh21", 0x363A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh21<.f> 0,b,limm 00110bbb00111010FBBB111110111110.  */
+{ "dsubh21", 0x303A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh21<.f><.cc> 0,limm,c 0011011011111010F111CCCCCC0QQQQQ.  */
+{ "dsubh21", 0x36FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh21<.f><.cc> b,b,limm 00110bbb11111010FBBB1111100QQQQQ.  */
+{ "dsubh21", 0x30FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA.  */
+{ "dsubh21", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f> 0,limm,u6 0011011001010010F111uuuuuu111110.  */
+{ "dsubh21", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ.  */
+{ "dsubh21", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,limm,u6 0011011001111010F111uuuuuuAAAAAA.  */
+{ "dsubh21", 0x367A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f> 0,limm,u6 0011011001111010F111uuuuuu111110.  */
+{ "dsubh21", 0x367A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh21<.f><.cc> 0,limm,u6 0011011011111010F111uuuuuu1QQQQQ.  */
+{ "dsubh21", 0x36FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh21<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS.  */
+{ "dsubh21", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh21<.f> 0,limm,s12 0011011010111010F111ssssssSSSSSS.  */
+{ "dsubh21", 0x36BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh21<.f> a,limm,limm 0011011000010010F111111110AAAAAA.  */
+{ "dsubh21", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh21<.f> 0,limm,limm 0011011000010010F111111110111110.  */
+{ "dsubh21", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh21<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ.  */
+{ "dsubh21", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh21<.f> a,limm,limm 0011011000111010F111111110AAAAAA.  */
+{ "dsubh21", 0x363A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh21<.f> 0,limm,limm 0011011000111010F111111110111110.  */
+{ "dsubh21", 0x363A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh21<.f><.cc> 0,limm,limm 0011011011111010F1111111100QQQQQ.  */
+{ "dsubh21", 0x36FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA.  */
+{ "dsubh22", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh22<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110.  */
+{ "dsubh22", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh22<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ.  */
+{ "dsubh22", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,b,c 00110bbb00111011FBBBCCCCCCAAAAAA.  */
+{ "dsubh22", 0x303B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }},
+
+/* dsubh22<.f> 0,b,c 00110bbb00111011FBBBCCCCCC111110.  */
+{ "dsubh22", 0x303B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }},
+
+/* dsubh22<.f><.cc> b,b,c 00110bbb11111011FBBBCCCCCC0QQQQQ.  */
+{ "dsubh22", 0x30FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA.  */
+{ "dsubh22", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110.  */
+{ "dsubh22", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ.  */
+{ "dsubh22", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,b,u6 00110bbb01111011FBBBuuuuuuAAAAAA.  */
+{ "dsubh22", 0x307B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f> 0,b,u6 00110bbb01111011FBBBuuuuuu111110.  */
+{ "dsubh22", 0x307B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f><.cc> b,b,u6 00110bbb11111011FBBBuuuuuu1QQQQQ.  */
+{ "dsubh22", 0x30FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh22<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS.  */
+{ "dsubh22", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh22<.f> b,b,s12 00110bbb10111011FBBBssssssSSSSSS.  */
+{ "dsubh22", 0x30BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* dsubh22<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA.  */
+{ "dsubh22", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh22<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA.  */
+{ "dsubh22", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh22<.f> 0,limm,c 0011011000010011F111CCCCCC111110.  */
+{ "dsubh22", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh22<.f> 0,b,limm 00110bbb00010011FBBB111110111110.  */
+{ "dsubh22", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh22<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ.  */
+{ "dsubh22", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh22<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ.  */
+{ "dsubh22", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,limm,c 0011011000111011F111CCCCCCAAAAAA.  */
+{ "dsubh22", 0x363B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }},
+
+/* dsubh22<.f> a,b,limm 00110bbb00111011FBBB111110AAAAAA.  */
+{ "dsubh22", 0x303B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }},
+
+/* dsubh22<.f> 0,limm,c 0011011000111011F111CCCCCC111110.  */
+{ "dsubh22", 0x363B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }},
+
+/* dsubh22<.f> 0,b,limm 00110bbb00111011FBBB111110111110.  */
+{ "dsubh22", 0x303B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }},
+
+/* dsubh22<.f><.cc> 0,limm,c 0011011011111011F111CCCCCC0QQQQQ.  */
+{ "dsubh22", 0x36FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dsubh22<.f><.cc> b,b,limm 00110bbb11111011FBBB1111100QQQQQ.  */
+{ "dsubh22", 0x30FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA.  */
+{ "dsubh22", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f> 0,limm,u6 0011011001010011F111uuuuuu111110.  */
+{ "dsubh22", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ.  */
+{ "dsubh22", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,limm,u6 0011011001111011F111uuuuuuAAAAAA.  */
+{ "dsubh22", 0x367B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f> 0,limm,u6 0011011001111011F111uuuuuu111110.  */
+{ "dsubh22", 0x367B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dsubh22<.f><.cc> 0,limm,u6 0011011011111011F111uuuuuu1QQQQQ.  */
+{ "dsubh22", 0x36FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dsubh22<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS.  */
+{ "dsubh22", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh22<.f> 0,limm,s12 0011011010111011F111ssssssSSSSSS.  */
+{ "dsubh22", 0x36BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dsubh22<.f> a,limm,limm 0011011000010011F111111110AAAAAA.  */
+{ "dsubh22", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh22<.f> 0,limm,limm 0011011000010011F111111110111110.  */
+{ "dsubh22", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh22<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ.  */
+{ "dsubh22", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsubh22<.f> a,limm,limm 0011011000111011F111111110AAAAAA.  */
+{ "dsubh22", 0x363B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh22<.f> 0,limm,limm 0011011000111011F111111110111110.  */
+{ "dsubh22", 0x363B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dsubh22<.f><.cc> 0,limm,limm 0011011011111011F1111111100QQQQQ.  */
+{ "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsync  00100010011011110001RRRRRR111111.  */
+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+
+/* ei_s u10 010111uuuuuuuuuu.  */
+{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }},
+
+/* enter_s u6 110000UU111uuuu0.  */
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM6_11_S }, { 0 }},
+
+/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100.  */
+{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100.  */
+{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> b,limm 00100bbb00101111DBBB111110001100.  */
+{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,c 0010011000101111D111CCCCCC001100.  */
+{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100.  */
+{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,limm 0010011000101111D111111110001100.  */
+{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
+
+/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111.  */
+{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* extb<.f> 0,c 0010011000101111F111CCCCCC000111.  */
+{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111.  */
+{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111.  */
+{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* extb<.f> b,limm 00100bbb00101111FBBB111110000111.  */
+{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* extb<.f> 0,limm 0010011000101111F111111110000111.  */
+{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* extb_s b,c 01111bbbccc01111.  */
+{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000.  */
+{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* exth<.f> 0,c 0010011000101111F111CCCCCC001000.  */
+{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000.  */
+{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000.  */
+{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* exth<.f> b,limm 00100bbb00101111FBBB111110001000.  */
+{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* exth<.f> 0,limm 0010011000101111F111111110001000.  */
+{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* exth_s b,c 01111bbbccc10000.  */
+{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* extw<.f> b,c 00100bbb00101111FBBBCCCCCC001000.  */
+{ "extw", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* extw<.f> 0,c 0010011000101111F111CCCCCC001000.  */
+{ "extw", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* extw<.f> b,u6 00100bbb01101111FBBBuuuuuu001000.  */
+{ "extw", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* extw<.f> 0,u6 0010011001101111F111uuuuuu001000.  */
+{ "extw", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* extw<.f> b,limm 00100bbb00101111FBBB111110001000.  */
+{ "extw", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* extw<.f> 0,limm 0010011000101111F111111110001000.  */
+{ "extw", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* extw_s b,c 01111bbbccc10000.  */
+{ "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* fadd<.f> a,b,c 00110bbb00000001FBBBCCCCCCAAAAAA.  */
+{ "fadd", 0x30010000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, RC }, { C_F }},
+
+/* fadd<.f> 0,b,c 00110bbb00000001FBBBCCCCCC111110.  */
+{ "fadd", 0x3001003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, RC }, { C_F }},
+
+/* fadd<.f><.cc> b,b,c 00110bbb11000001FBBBCCCCCC0QQQQQ.  */
+{ "fadd", 0x30C10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fadd<.f> a,b,u6 00110bbb01000001FBBBuuuuuuAAAAAA.  */
+{ "fadd", 0x30410000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fadd<.f> 0,b,u6 00110bbb01000001FBBBuuuuuu111110.  */
+{ "fadd", 0x3041003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* fadd<.f><.cc> b,b,u6 00110bbb11000001FBBBuuuuuu1QQQQQ.  */
+{ "fadd", 0x30C10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fadd<.f> b,b,s12 00110bbb10000001FBBBssssssSSSSSS.  */
+{ "fadd", 0x30810000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fadd<.f> a,limm,c 0011011000000001F111CCCCCCAAAAAA.  */
+{ "fadd", 0x36017000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, RC }, { C_F }},
+
+/* fadd<.f> a,b,limm 00110bbb00000001FBBB111110AAAAAA.  */
+{ "fadd", 0x30010F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, LIMM }, { C_F }},
+
+/* fadd<.f> 0,limm,c 0011011000000001F111CCCCCC111110.  */
+{ "fadd", 0x3601703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F }},
+
+/* fadd<.f> 0,b,limm 00110bbb00000001FBBB111110111110.  */
+{ "fadd", 0x30010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, LIMM }, { C_F }},
+
+/* fadd<.f><.cc> 0,limm,c 0011011011000001F111CCCCCC0QQQQQ.  */
+{ "fadd", 0x36C17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* fadd<.f><.cc> b,b,limm 00110bbb11000001FBBB1111100QQQQQ.  */
+{ "fadd", 0x30C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* fadd<.f> a,limm,u6 0011011001000001F111uuuuuuAAAAAA.  */
+{ "fadd", 0x36417000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fadd<.f> 0,limm,u6 0011011001000001F111uuuuuu111110.  */
+{ "fadd", 0x3641703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fadd<.f><.cc> 0,limm,u6 0011011011000001F111uuuuuu1QQQQQ.  */
+{ "fadd", 0x36C17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* fadd<.f> 0,limm,s12 0011011010000001F111ssssssSSSSSS.  */
+{ "fadd", 0x36817000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* fadd<.f> a,limm,limm 0011011000000001F111111110AAAAAA.  */
+{ "fadd", 0x36017F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* fadd<.f> 0,limm,limm 0011011000000001F111111110111110.  */
+{ "fadd", 0x36017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* fadd<.f><.cc> 0,limm,limm 0011011011000001F1111111100QQQQQ.  */
+{ "fadd", 0x36C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* fbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001011.  */
+{ "fbfdw", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, RC }, { C_F }},
+
+/* fbfdw<.f> 0,c 0010111000101111F111CCCCCC001011.  */
+{ "fbfdw", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* fbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001011.  */
+{ "fbfdw", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* fbfdw<.f> 0,u6 0010111001101111F111uuuuuu001011.  */
+{ "fbfdw", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* fbfdw<.f> b,limm 00101bbb00101111FBBB111110001011.  */
+{ "fbfdw", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { RB, LIMM }, { C_F }},
+
+/* fbfdw<.f> 0,limm 0010111000101111F111111110001011.  */
+{ "fbfdw", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* fcvt32 a,b,c 00110bbb000010000BBBCCCCCCAAAAAA.  */
+{ "fcvt32", 0x30080000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }},
+
+/* fcvt32 0,b,c 00110bbb000010000BBBCCCCCC111110.  */
+{ "fcvt32", 0x3008003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }},
+
+/* fcvt32<.cc> b,b,c 00110bbb110010000BBBCCCCCC0QQQQQ.  */
+{ "fcvt32", 0x30C80000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }},
+
+/* fcvt32 a,b,u6 00110bbb010010000BBBuuuuuuAAAAAA.  */
+{ "fcvt32", 0x30480000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt32 0,b,u6 00110bbb010010000BBBuuuuuu111110.  */
+{ "fcvt32", 0x3048003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt32<.cc> b,b,u6 00110bbb110010000BBBuuuuuu1QQQQQ.  */
+{ "fcvt32", 0x30C80020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fcvt32 b,b,s12 00110bbb100010000BBBssssssSSSSSS.  */
+{ "fcvt32", 0x30880000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fcvt32 a,limm,c 00110110000010000111CCCCCCAAAAAA.  */
+{ "fcvt32", 0x36087000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }},
+
+/* fcvt32 a,b,limm 00110bbb000010000BBB111110AAAAAA.  */
+{ "fcvt32", 0x30080F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }},
+
+/* fcvt32 0,limm,c 00110110000010000111CCCCCC111110.  */
+{ "fcvt32", 0x3608703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }},
+
+/* fcvt32 0,b,limm 00110bbb000010000BBB111110111110.  */
+{ "fcvt32", 0x30080FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }},
+
+/* fcvt32<.cc> b,b,limm 00110bbb110010000BBB1111100QQQQQ.  */
+{ "fcvt32", 0x30C80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fcvt32<.cc> 0,limm,c 00110110110010000111CCCCCC0QQQQQ.  */
+{ "fcvt32", 0x36C87000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }},
+
+/* fcvt32 a,limm,u6 00110110010010000111uuuuuuAAAAAA.  */
+{ "fcvt32", 0x36487000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt32 0,limm,u6 00110110010010000111uuuuuu111110.  */
+{ "fcvt32", 0x3648703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt32<.cc> 0,limm,u6 00110110110010000111uuuuuu1QQQQQ.  */
+{ "fcvt32", 0x36C87020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fcvt32 0,limm,s12 00110110100010000111ssssssSSSSSS.  */
+{ "fcvt32", 0x36887000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fcvt32 a,limm,limm 00110110000010000111111110AAAAAA.  */
+{ "fcvt32", 0x36087F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt32 0,limm,limm 00110110000010000111111110111110.  */
+{ "fcvt32", 0x36087FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt32<.cc> 0,limm,limm 001101101100100001111111100QQQQQ.  */
+{ "fcvt32", 0x36C87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fcvt32_64 a,b,c 00110bbb000010010BBBCCCCCCAAAAAA.  */
+{ "fcvt32_64", 0x30090000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }},
+
+/* fcvt32_64 0,b,c 00110bbb000010010BBBCCCCCC111110.  */
+{ "fcvt32_64", 0x3009003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }},
+
+/* fcvt32_64<.cc> b,b,c 00110bbb110010010BBBCCCCCC0QQQQQ.  */
+{ "fcvt32_64", 0x30C90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }},
+
+/* fcvt32_64 a,b,u6 00110bbb010010010BBBuuuuuuAAAAAA.  */
+{ "fcvt32_64", 0x30490000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt32_64 0,b,u6 00110bbb010010010BBBuuuuuu111110.  */
+{ "fcvt32_64", 0x3049003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt32_64<.cc> b,b,u6 00110bbb110010010BBBuuuuuu1QQQQQ.  */
+{ "fcvt32_64", 0x30C90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fcvt32_64 b,b,s12 00110bbb100010010BBBssssssSSSSSS.  */
+{ "fcvt32_64", 0x30890000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fcvt32_64 a,limm,c 00110110000010010111CCCCCCAAAAAA.  */
+{ "fcvt32_64", 0x36097000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }},
+
+/* fcvt32_64 a,b,limm 00110bbb000010010BBB111110AAAAAA.  */
+{ "fcvt32_64", 0x30090F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }},
+
+/* fcvt32_64 0,limm,c 00110110000010010111CCCCCC111110.  */
+{ "fcvt32_64", 0x3609703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }},
+
+/* fcvt32_64 0,b,limm 00110bbb000010010BBB111110111110.  */
+{ "fcvt32_64", 0x30090FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }},
+
+/* fcvt32_64<.cc> b,b,limm 00110bbb110010010BBB1111100QQQQQ.  */
+{ "fcvt32_64", 0x30C90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fcvt32_64<.cc> 0,limm,c 00110110110010010111CCCCCC0QQQQQ.  */
+{ "fcvt32_64", 0x36C97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }},
+
+/* fcvt32_64 a,limm,u6 00110110010010010111uuuuuuAAAAAA.  */
+{ "fcvt32_64", 0x36497000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt32_64 0,limm,u6 00110110010010010111uuuuuu111110.  */
+{ "fcvt32_64", 0x3649703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt32_64<.cc> 0,limm,u6 00110110110010010111uuuuuu1QQQQQ.  */
+{ "fcvt32_64", 0x36C97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fcvt32_64 0,limm,s12 00110110100010010111ssssssSSSSSS.  */
+{ "fcvt32_64", 0x36897000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fcvt32_64 a,limm,limm 00110110000010010111111110AAAAAA.  */
+{ "fcvt32_64", 0x36097F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt32_64 0,limm,limm 00110110000010010111111110111110.  */
+{ "fcvt32_64", 0x36097FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt32_64<.cc> 0,limm,limm 001101101100100101111111100QQQQQ.  */
+{ "fcvt32_64", 0x36C97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fcvt64 a,b,c 00110bbb001110000BBBCCCCCCAAAAAA.  */
+{ "fcvt64", 0x30380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }},
+
+/* fcvt64 0,b,c 00110bbb001110000BBBCCCCCC111110.  */
+{ "fcvt64", 0x3038003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }},
+
+/* fcvt64<.cc> b,b,c 00110bbb111110000BBBCCCCCC0QQQQQ.  */
+{ "fcvt64", 0x30F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }},
+
+/* fcvt64 a,b,u6 00110bbb011110000BBBuuuuuuAAAAAA.  */
+{ "fcvt64", 0x30780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt64 0,b,u6 00110bbb011110000BBBuuuuuu111110.  */
+{ "fcvt64", 0x3078003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt64<.cc> b,b,u6 00110bbb111110000BBBuuuuuu1QQQQQ.  */
+{ "fcvt64", 0x30F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fcvt64 b,b,s12 00110bbb101110000BBBssssssSSSSSS.  */
+{ "fcvt64", 0x30B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fcvt64 a,limm,c 00110110001110000111CCCCCCAAAAAA.  */
+{ "fcvt64", 0x36387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }},
+
+/* fcvt64 a,b,limm 00110bbb001110000BBB111110AAAAAA.  */
+{ "fcvt64", 0x30380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }},
+
+/* fcvt64 0,limm,c 00110110001110000111CCCCCC111110.  */
+{ "fcvt64", 0x3638703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }},
+
+/* fcvt64 0,b,limm 00110bbb001110000BBB111110111110.  */
+{ "fcvt64", 0x30380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }},
+
+/* fcvt64<.cc> b,b,limm 00110bbb111110000BBB1111100QQQQQ.  */
+{ "fcvt64", 0x30F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fcvt64<.cc> 0,limm,c 00110110111110000111CCCCCC0QQQQQ.  */
+{ "fcvt64", 0x36F87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }},
+
+/* fcvt64 a,limm,u6 00110110011110000111uuuuuuAAAAAA.  */
+{ "fcvt64", 0x36787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt64 0,limm,u6 00110110011110000111uuuuuu111110.  */
+{ "fcvt64", 0x3678703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt64<.cc> 0,limm,u6 00110110111110000111uuuuuu1QQQQQ.  */
+{ "fcvt64", 0x36F87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fcvt64 0,limm,s12 00110110101110000111ssssssSSSSSS.  */
+{ "fcvt64", 0x36B87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fcvt64 a,limm,limm 00110110001110000111111110AAAAAA.  */
+{ "fcvt64", 0x36387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt64 0,limm,limm 00110110001110000111111110111110.  */
+{ "fcvt64", 0x36387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt64<.cc> 0,limm,limm 001101101111100001111111100QQQQQ.  */
+{ "fcvt64", 0x36F87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fcvt64_32 a,b,c 00110bbb001110010BBBCCCCCCAAAAAA.  */
+{ "fcvt64_32", 0x30390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }},
+
+/* fcvt64_32 0,b,c 00110bbb001110010BBBCCCCCC111110.  */
+{ "fcvt64_32", 0x3039003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }},
+
+/* fcvt64_32<.cc> b,b,c 00110bbb111110010BBBCCCCCC0QQQQQ.  */
+{ "fcvt64_32", 0x30F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }},
+
+/* fcvt64_32 a,b,u6 00110bbb011110010BBBuuuuuuAAAAAA.  */
+{ "fcvt64_32", 0x30790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt64_32 0,b,u6 00110bbb011110010BBBuuuuuu111110.  */
+{ "fcvt64_32", 0x3079003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fcvt64_32<.cc> b,b,u6 00110bbb111110010BBBuuuuuu1QQQQQ.  */
+{ "fcvt64_32", 0x30F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fcvt64_32 b,b,s12 00110bbb101110010BBBssssssSSSSSS.  */
+{ "fcvt64_32", 0x30B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fcvt64_32 a,limm,c 00110110001110010111CCCCCCAAAAAA.  */
+{ "fcvt64_32", 0x36397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }},
+
+/* fcvt64_32 a,b,limm 00110bbb001110010BBB111110AAAAAA.  */
+{ "fcvt64_32", 0x30390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }},
+
+/* fcvt64_32 0,limm,c 00110110001110010111CCCCCC111110.  */
+{ "fcvt64_32", 0x3639703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }},
+
+/* fcvt64_32 0,b,limm 00110bbb001110010BBB111110111110.  */
+{ "fcvt64_32", 0x30390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }},
+
+/* fcvt64_32<.cc> b,b,limm 00110bbb111110010BBB1111100QQQQQ.  */
+{ "fcvt64_32", 0x30F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fcvt64_32<.cc> 0,limm,c 00110110111110010111CCCCCC0QQQQQ.  */
+{ "fcvt64_32", 0x36F97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }},
+
+/* fcvt64_32 a,limm,u6 00110110011110010111uuuuuuAAAAAA.  */
+{ "fcvt64_32", 0x36797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt64_32 0,limm,u6 00110110011110010111uuuuuu111110.  */
+{ "fcvt64_32", 0x3679703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fcvt64_32<.cc> 0,limm,u6 00110110111110010111uuuuuu1QQQQQ.  */
+{ "fcvt64_32", 0x36F97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fcvt64_32 0,limm,s12 00110110101110010111ssssssSSSSSS.  */
+{ "fcvt64_32", 0x36B97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fcvt64_32 a,limm,limm 00110110001110010111111110AAAAAA.  */
+{ "fcvt64_32", 0x36397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt64_32 0,limm,limm 00110110001110010111111110111110.  */
+{ "fcvt64_32", 0x36397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fcvt64_32<.cc> 0,limm,limm 001101101111100101111111100QQQQQ.  */
+{ "fcvt64_32", 0x36F97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fdadd a,b,c 00110bbb001100010BBBCCCCCCAAAAAA.  */
+{ "fdadd", 0x30310000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }},
+
+/* fdadd 0,b,c 00110bbb001100010BBBCCCCCC111110.  */
+{ "fdadd", 0x3031003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }},
+
+/* fdadd<.cc> b,b,c 00110bbb111100010BBBCCCCCC0QQQQQ.  */
+{ "fdadd", 0x30F10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }},
+
+/* fdadd a,b,u6 00110bbb011100010BBBuuuuuuAAAAAA.  */
+{ "fdadd", 0x30710000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fdadd 0,b,u6 00110bbb011100010BBBuuuuuu111110.  */
+{ "fdadd", 0x3071003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fdadd<.cc> b,b,u6 00110bbb111100010BBBuuuuuu1QQQQQ.  */
+{ "fdadd", 0x30F10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fdadd b,b,s12 00110bbb101100010BBBssssssSSSSSS.  */
+{ "fdadd", 0x30B10000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fdadd a,limm,c 00110110001100010111CCCCCCAAAAAA.  */
+{ "fdadd", 0x36317000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }},
+
+/* fdadd a,b,limm 00110bbb001100010BBB111110AAAAAA.  */
+{ "fdadd", 0x30310F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }},
+
+/* fdadd 0,limm,c 00110110001100010111CCCCCC111110.  */
+{ "fdadd", 0x3631703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }},
+
+/* fdadd 0,b,limm 00110bbb001100010BBB111110111110.  */
+{ "fdadd", 0x30310FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }},
+
+/* fdadd<.cc> b,b,limm 00110bbb111100010BBB1111100QQQQQ.  */
+{ "fdadd", 0x30F10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fdadd<.cc> 0,limm,c 00110110111100010111CCCCCC0QQQQQ.  */
+{ "fdadd", 0x36F17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fdadd a,limm,u6 00110110011100010111uuuuuuAAAAAA.  */
+{ "fdadd", 0x36717000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdadd 0,limm,u6 00110110011100010111uuuuuu111110.  */
+{ "fdadd", 0x3671703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdadd<.cc> 0,limm,u6 00110110111100010111uuuuuu1QQQQQ.  */
+{ "fdadd", 0x36F17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdadd 0,limm,s12 00110110101100010111ssssssSSSSSS.  */
+{ "fdadd", 0x36B17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fdadd a,limm,limm 00110110001100010111111110AAAAAA.  */
+{ "fdadd", 0x36317F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fdadd 0,limm,limm 00110110001100010111111110111110.  */
+{ "fdadd", 0x36317FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fdadd<.cc> 0,limm,limm 001101101111000101111111100QQQQQ.  */
+{ "fdadd", 0x36F17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fdcmp b,c 00110bbb001100111BBBCCCCCC000000.  */
+{ "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }},
+
+/* fdcmp<.cc> b,c 00110bbb111100111BBBCCCCCC0QQQQQ.  */
+{ "fdcmp", 0x30F38000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { C_CC }},
+
+/* fdcmp b,u6 00110bbb011100111BBBuuuuuu000000.  */
+{ "fdcmp", 0x30738000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { 0 }},
+
+/* fdcmp<.cc> b,u6 00110bbb111100111BBBuuuuuu1QQQQQ.  */
+{ "fdcmp", 0x30F38020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { C_CC }},
+
+/* fdcmp b,s12 00110bbb101100111BBBssssssSSSSSS.  */
+{ "fdcmp", 0x30B38000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, SIMM12_20 }, { 0 }},
+
+/* fdcmp limm,c 00110110001100111111CCCCCC000000.  */
+{ "fdcmp", 0x3633F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { 0 }},
+
+/* fdcmp b,limm 00110bbb001100111BBB111110000000.  */
+{ "fdcmp", 0x30338F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { 0 }},
+
+/* fdcmp<.cc> b,limm 00110bbb111100111BBB1111100QQQQQ.  */
+{ "fdcmp", 0x30F38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { C_CC }},
+
+/* fdcmp<.cc> limm,c 00110110111100111111CCCCCC0QQQQQ.  */
+{ "fdcmp", 0x36F3F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { C_CC }},
+
+/* fdcmp limm,u6 00110110011100111111uuuuuu000000.  */
+{ "fdcmp", 0x3673F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { 0 }},
+
+/* fdcmp<.cc> limm,u6 00110110111100111111uuuuuu1QQQQQ.  */
+{ "fdcmp", 0x36F3F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdcmp limm,s12 00110110101100111111ssssssSSSSSS.  */
+{ "fdcmp", 0x36B3F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, SIMM12_20 }, { 0 }},
+
+/* fdcmp limm,limm 00110110001100111111111110000000.  */
+{ "fdcmp", 0x3633FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { 0 }},
+
+/* fdcmp<.cc> limm,limm 001101101111001111111111100QQQQQ.  */
+{ "fdcmp", 0x36F3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { C_CC }},
+
+/* fdcmpf b,c 00110bbb001101001BBBCCCCCC000000.  */
+{ "fdcmpf", 0x30348000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }},
+
+/* fdcmpf<.cc> b,c 00110bbb111101001BBBCCCCCC0QQQQQ.  */
+{ "fdcmpf", 0x30F48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { C_CC }},
+
+/* fdcmpf b,u6 00110bbb011101001BBBuuuuuu000000.  */
+{ "fdcmpf", 0x30748000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { 0 }},
+
+/* fdcmpf<.cc> b,u6 00110bbb111101001BBBuuuuuu1QQQQQ.  */
+{ "fdcmpf", 0x30F48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { C_CC }},
+
+/* fdcmpf b,s12 00110bbb101101001BBBssssssSSSSSS.  */
+{ "fdcmpf", 0x30B48000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, SIMM12_20 }, { 0 }},
+
+/* fdcmpf limm,c 00110110001101001111CCCCCC000000.  */
+{ "fdcmpf", 0x3634F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { 0 }},
+
+/* fdcmpf b,limm 00110bbb001101001BBB111110000000.  */
+{ "fdcmpf", 0x30348F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { 0 }},
+
+/* fdcmpf<.cc> b,limm 00110bbb111101001BBB1111100QQQQQ.  */
+{ "fdcmpf", 0x30F48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { C_CC }},
+
+/* fdcmpf<.cc> limm,c 00110110111101001111CCCCCC0QQQQQ.  */
+{ "fdcmpf", 0x36F4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { C_CC }},
+
+/* fdcmpf limm,u6 00110110011101001111uuuuuu000000.  */
+{ "fdcmpf", 0x3674F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { 0 }},
+
+/* fdcmpf<.cc> limm,u6 00110110111101001111uuuuuu1QQQQQ.  */
+{ "fdcmpf", 0x36F4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdcmpf limm,s12 00110110101101001111ssssssSSSSSS.  */
+{ "fdcmpf", 0x36B4F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, SIMM12_20 }, { 0 }},
+
+/* fdcmpf limm,limm 00110110001101001111111110000000.  */
+{ "fdcmpf", 0x3634FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { 0 }},
+
+/* fdcmpf<.cc> limm,limm 001101101111010011111111100QQQQQ.  */
+{ "fdcmpf", 0x36F4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { C_CC }},
+
+/* fddiv a,b,c 00110bbb001101110BBBCCCCCCAAAAAA.  */
+{ "fddiv", 0x30370000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }},
+
+/* fddiv 0,b,c 00110bbb001101110BBBCCCCCC111110.  */
+{ "fddiv", 0x3037003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }},
+
+/* fddiv<.cc> b,b,c 00110bbb111101110BBBCCCCCC0QQQQQ.  */
+{ "fddiv", 0x30F70000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }},
+
+/* fddiv a,b,u6 00110bbb011101110BBBuuuuuuAAAAAA.  */
+{ "fddiv", 0x30770000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fddiv 0,b,u6 00110bbb011101110BBBuuuuuu111110.  */
+{ "fddiv", 0x3077003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fddiv<.cc> b,b,u6 00110bbb111101110BBBuuuuuu1QQQQQ.  */
+{ "fddiv", 0x30F70020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fddiv b,b,s12 00110bbb101101110BBBssssssSSSSSS.  */
+{ "fddiv", 0x30B70000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fddiv a,limm,c 00110110001101110111CCCCCCAAAAAA.  */
+{ "fddiv", 0x36377000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }},
+
+/* fddiv a,b,limm 00110bbb001101110BBB111110AAAAAA.  */
+{ "fddiv", 0x30370F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }},
+
+/* fddiv 0,limm,c 00110110001101110111CCCCCC111110.  */
+{ "fddiv", 0x3637703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }},
+
+/* fddiv 0,b,limm 00110bbb001101110BBB111110111110.  */
+{ "fddiv", 0x30370FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }},
+
+/* fddiv<.cc> b,b,limm 00110bbb111101110BBB1111100QQQQQ.  */
+{ "fddiv", 0x30F70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fddiv<.cc> 0,limm,c 00110110111101110111CCCCCC0QQQQQ.  */
+{ "fddiv", 0x36F77000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fddiv a,limm,u6 00110110011101110111uuuuuuAAAAAA.  */
+{ "fddiv", 0x36777000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fddiv 0,limm,u6 00110110011101110111uuuuuu111110.  */
+{ "fddiv", 0x3677703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fddiv<.cc> 0,limm,u6 00110110111101110111uuuuuu1QQQQQ.  */
+{ "fddiv", 0x36F77020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fddiv 0,limm,s12 00110110101101110111ssssssSSSSSS.  */
+{ "fddiv", 0x36B77000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fddiv a,limm,limm 00110110001101110111111110AAAAAA.  */
+{ "fddiv", 0x36377F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fddiv 0,limm,limm 00110110001101110111111110111110.  */
+{ "fddiv", 0x36377FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fddiv<.cc> 0,limm,limm 001101101111011101111111100QQQQQ.  */
+{ "fddiv", 0x36F77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fdmadd a,b,c 00110bbb001101010BBBCCCCCCAAAAAA.  */
+{ "fdmadd", 0x30350000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }},
+
+/* fdmadd 0,b,c 00110bbb001101010BBBCCCCCC111110.  */
+{ "fdmadd", 0x3035003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }},
+
+/* fdmadd<.cc> b,b,c 00110bbb111101010BBBCCCCCC0QQQQQ.  */
+{ "fdmadd", 0x30F50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }},
+
+/* fdmadd a,b,u6 00110bbb011101010BBBuuuuuuAAAAAA.  */
+{ "fdmadd", 0x30750000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fdmadd 0,b,u6 00110bbb011101010BBBuuuuuu111110.  */
+{ "fdmadd", 0x3075003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fdmadd<.cc> b,b,u6 00110bbb111101010BBBuuuuuu1QQQQQ.  */
+{ "fdmadd", 0x30F50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fdmadd b,b,s12 00110bbb101101010BBBssssssSSSSSS.  */
+{ "fdmadd", 0x30B50000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fdmadd a,limm,c 00110110001101010111CCCCCCAAAAAA.  */
+{ "fdmadd", 0x36357000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }},
+
+/* fdmadd a,b,limm 00110bbb001101010BBB111110AAAAAA.  */
+{ "fdmadd", 0x30350F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }},
+
+/* fdmadd 0,limm,c 00110110001101010111CCCCCC111110.  */
+{ "fdmadd", 0x3635703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }},
+
+/* fdmadd 0,b,limm 00110bbb001101010BBB111110111110.  */
+{ "fdmadd", 0x30350FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }},
+
+/* fdmadd<.cc> b,b,limm 00110bbb111101010BBB1111100QQQQQ.  */
+{ "fdmadd", 0x30F50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fdmadd<.cc> 0,limm,c 00110110111101010111CCCCCC0QQQQQ.  */
+{ "fdmadd", 0x36F57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fdmadd a,limm,u6 00110110011101010111uuuuuuAAAAAA.  */
+{ "fdmadd", 0x36757000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdmadd 0,limm,u6 00110110011101010111uuuuuu111110.  */
+{ "fdmadd", 0x3675703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdmadd<.cc> 0,limm,u6 00110110111101010111uuuuuu1QQQQQ.  */
+{ "fdmadd", 0x36F57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdmadd 0,limm,s12 00110110101101010111ssssssSSSSSS.  */
+{ "fdmadd", 0x36B57000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fdmadd a,limm,limm 00110110001101010111111110AAAAAA.  */
+{ "fdmadd", 0x36357F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fdmadd 0,limm,limm 00110110001101010111111110111110.  */
+{ "fdmadd", 0x36357FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fdmadd<.cc> 0,limm,limm 001101101111010101111111100QQQQQ.  */
+{ "fdmadd", 0x36F57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fdmsub a,b,c 00110bbb001101100BBBCCCCCCAAAAAA.  */
+{ "fdmsub", 0x30360000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }},
+
+/* fdmsub 0,b,c 00110bbb001101100BBBCCCCCC111110.  */
+{ "fdmsub", 0x3036003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }},
+
+/* fdmsub<.cc> b,b,c 00110bbb111101100BBBCCCCCC0QQQQQ.  */
+{ "fdmsub", 0x30F60000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }},
+
+/* fdmsub a,b,u6 00110bbb011101100BBBuuuuuuAAAAAA.  */
+{ "fdmsub", 0x30760000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fdmsub 0,b,u6 00110bbb011101100BBBuuuuuu111110.  */
+{ "fdmsub", 0x3076003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fdmsub<.cc> b,b,u6 00110bbb111101100BBBuuuuuu1QQQQQ.  */
+{ "fdmsub", 0x30F60020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fdmsub b,b,s12 00110bbb101101100BBBssssssSSSSSS.  */
+{ "fdmsub", 0x30B60000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fdmsub a,limm,c 00110110001101100111CCCCCCAAAAAA.  */
+{ "fdmsub", 0x36367000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }},
+
+/* fdmsub a,b,limm 00110bbb001101100BBB111110AAAAAA.  */
+{ "fdmsub", 0x30360F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }},
+
+/* fdmsub 0,limm,c 00110110001101100111CCCCCC111110.  */
+{ "fdmsub", 0x3636703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }},
+
+/* fdmsub 0,b,limm 00110bbb001101100BBB111110111110.  */
+{ "fdmsub", 0x30360FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }},
+
+/* fdmsub<.cc> b,b,limm 00110bbb111101100BBB1111100QQQQQ.  */
+{ "fdmsub", 0x30F60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fdmsub<.cc> 0,limm,c 00110110111101100111CCCCCC0QQQQQ.  */
+{ "fdmsub", 0x36F67000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fdmsub a,limm,u6 00110110011101100111uuuuuuAAAAAA.  */
+{ "fdmsub", 0x36767000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdmsub 0,limm,u6 00110110011101100111uuuuuu111110.  */
+{ "fdmsub", 0x3676703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdmsub<.cc> 0,limm,u6 00110110111101100111uuuuuu1QQQQQ.  */
+{ "fdmsub", 0x36F67020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdmsub 0,limm,s12 00110110101101100111ssssssSSSSSS.  */
+{ "fdmsub", 0x36B67000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fdmsub a,limm,limm 00110110001101100111111110AAAAAA.  */
+{ "fdmsub", 0x36367F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fdmsub 0,limm,limm 00110110001101100111111110111110.  */
+{ "fdmsub", 0x36367FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fdmsub<.cc> 0,limm,limm 001101101111011001111111100QQQQQ.  */
+{ "fdmsub", 0x36F67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fdmul a,b,c 00110bbb001100000BBBCCCCCCAAAAAA.  */
+{ "fdmul", 0x30300000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }},
+
+/* fdmul 0,b,c 00110bbb001100000BBBCCCCCC111110.  */
+{ "fdmul", 0x3030003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }},
+
+/* fdmul<.cc> b,b,c 00110bbb111100000BBBCCCCCC0QQQQQ.  */
+{ "fdmul", 0x30F00000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }},
+
+/* fdmul a,b,u6 00110bbb011100000BBBuuuuuuAAAAAA.  */
+{ "fdmul", 0x30700000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fdmul 0,b,u6 00110bbb011100000BBBuuuuuu111110.  */
+{ "fdmul", 0x3070003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fdmul<.cc> b,b,u6 00110bbb111100000BBBuuuuuu1QQQQQ.  */
+{ "fdmul", 0x30F00020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fdmul b,b,s12 00110bbb101100000BBBssssssSSSSSS.  */
+{ "fdmul", 0x30B00000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fdmul a,limm,c 00110110001100000111CCCCCCAAAAAA.  */
+{ "fdmul", 0x36307000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }},
+
+/* fdmul a,b,limm 00110bbb001100000BBB111110AAAAAA.  */
+{ "fdmul", 0x30300F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }},
+
+/* fdmul 0,limm,c 00110110001100000111CCCCCC111110.  */
+{ "fdmul", 0x3630703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }},
+
+/* fdmul 0,b,limm 00110bbb001100000BBB111110111110.  */
+{ "fdmul", 0x30300FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }},
+
+/* fdmul<.cc> b,b,limm 00110bbb111100000BBB1111100QQQQQ.  */
+{ "fdmul", 0x30F00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fdmul<.cc> 0,limm,c 00110110111100000111CCCCCC0QQQQQ.  */
+{ "fdmul", 0x36F07000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fdmul a,limm,u6 00110110011100000111uuuuuuAAAAAA.  */
+{ "fdmul", 0x36707000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdmul 0,limm,u6 00110110011100000111uuuuuu111110.  */
+{ "fdmul", 0x3670703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdmul<.cc> 0,limm,u6 00110110111100000111uuuuuu1QQQQQ.  */
+{ "fdmul", 0x36F07020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdmul 0,limm,s12 00110110101100000111ssssssSSSSSS.  */
+{ "fdmul", 0x36B07000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fdmul a,limm,limm 00110110001100000111111110AAAAAA.  */
+{ "fdmul", 0x36307F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fdmul 0,limm,limm 00110110001100000111111110111110.  */
+{ "fdmul", 0x36307FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fdmul<.cc> 0,limm,limm 001101101111000001111111100QQQQQ.  */
+{ "fdmul", 0x36F07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fdsqrt b,c 00110bbb001011110BBBCCCCCC000001.  */
+{ "fdsqrt", 0x302F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }},
+
+/* fdsqrt 0,c 00110110001011110111CCCCCC000001.  */
+{ "fdsqrt", 0x362F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RC }, { 0 }},
+
+/* fdsqrt b,u6 00110bbb011011110BBBuuuuuu000001.  */
+{ "fdsqrt", 0x306F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { 0 }},
+
+/* fdsqrt 0,u6 00110110011011110111uuuuuu000001.  */
+{ "fdsqrt", 0x366F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, UIMM6_20 }, { 0 }},
+
+/* fdsqrt b,limm 00110bbb001011110BBB111110000001.  */
+{ "fdsqrt", 0x302F0F81, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { 0 }},
+
+/* fdsqrt 0,limm 00110110001011110111111110000001.  */
+{ "fdsqrt", 0x362F7F81, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM }, { 0 }},
+
+/* fdsub a,b,c 00110bbb001100100BBBCCCCCCAAAAAA.  */
+{ "fdsub", 0x30320000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }},
+
+/* fdsub 0,b,c 00110bbb001100100BBBCCCCCC111110.  */
+{ "fdsub", 0x3032003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }},
+
+/* fdsub<.cc> b,b,c 00110bbb111100100BBBCCCCCC0QQQQQ.  */
+{ "fdsub", 0x30F20000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }},
+
+/* fdsub a,b,u6 00110bbb011100100BBBuuuuuuAAAAAA.  */
+{ "fdsub", 0x30720000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fdsub 0,b,u6 00110bbb011100100BBBuuuuuu111110.  */
+{ "fdsub", 0x3072003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fdsub<.cc> b,b,u6 00110bbb111100100BBBuuuuuu1QQQQQ.  */
+{ "fdsub", 0x30F20020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fdsub b,b,s12 00110bbb101100100BBBssssssSSSSSS.  */
+{ "fdsub", 0x30B20000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fdsub a,limm,c 00110110001100100111CCCCCCAAAAAA.  */
+{ "fdsub", 0x36327000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }},
+
+/* fdsub a,b,limm 00110bbb001100100BBB111110AAAAAA.  */
+{ "fdsub", 0x30320F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }},
+
+/* fdsub 0,limm,c 00110110001100100111CCCCCC111110.  */
+{ "fdsub", 0x3632703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }},
+
+/* fdsub 0,b,limm 00110bbb001100100BBB111110111110.  */
+{ "fdsub", 0x30320FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }},
+
+/* fdsub<.cc> b,b,limm 00110bbb111100100BBB1111100QQQQQ.  */
+{ "fdsub", 0x30F20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fdsub<.cc> 0,limm,c 00110110111100100111CCCCCC0QQQQQ.  */
+{ "fdsub", 0x36F27000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fdsub a,limm,u6 00110110011100100111uuuuuuAAAAAA.  */
+{ "fdsub", 0x36727000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdsub 0,limm,u6 00110110011100100111uuuuuu111110.  */
+{ "fdsub", 0x3672703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fdsub<.cc> 0,limm,u6 00110110111100100111uuuuuu1QQQQQ.  */
+{ "fdsub", 0x36F27020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fdsub 0,limm,s12 00110110101100100111ssssssSSSSSS.  */
+{ "fdsub", 0x36B27000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fdsub a,limm,limm 00110110001100100111111110AAAAAA.  */
+{ "fdsub", 0x36327F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fdsub 0,limm,limm 00110110001100100111111110111110.  */
+{ "fdsub", 0x36327FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fdsub<.cc> 0,limm,limm 001101101111001001111111100QQQQQ.  */
+{ "fdsub", 0x36F27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010.  */
+{ "ffs", 0x282F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010.  */
+{ "ffs", 0x2E2F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010.  */
+{ "ffs", 0x286F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010.  */
+{ "ffs", 0x2E6F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010.  */
+{ "ffs", 0x282F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* ffs<.f> 0,limm 0010111000101111F111111110010010.  */
+{ "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* flag c 00100RRR001010010RRRCCCCCCRRRRRR.  */
+{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
+
+/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ.  */
+{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { C_CC }},
+
+/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR.  */
+{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ.  */
+{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { C_CC }},
+
+/* flag s12 00100RRR101010010RRRssssssSSSSSS.  */
+{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { SIMM12_20 }, { 0 }},
+
+/* flag limm 00100RRR001010010RRR111110RRRRRR.  */
+{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ.  */
+{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { C_CC }},
+
+/* flagacc c 00101100001011111000CCCCCC111111.  */
+{ "flagacc", 0x2C2F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }},
+
+/* flagacc u6 00101100011011111000uuuuuu111111.  */
+{ "flagacc", 0x2C6F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011.  */
+{ "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* fls<.f> 0,c 0010111000101111F111CCCCCC010011.  */
+{ "fls", 0x2E2F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011.  */
+{ "fls", 0x286F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011.  */
+{ "fls", 0x2E6F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* fls<.f> b,limm 00101bbb00101111FBBB111110010011.  */
+{ "fls", 0x282F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* fls<.f> 0,limm 0010111000101111F111111110010011.  */
+{ "fls", 0x2E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* fmul<.f> a,b,c 00110bbb00000000FBBBCCCCCCAAAAAA.  */
+{ "fmul", 0x30000000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, RC }, { C_F }},
+
+/* fmul<.f> 0,b,c 00110bbb00000000FBBBCCCCCC111110.  */
+{ "fmul", 0x3000003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, RC }, { C_F }},
+
+/* fmul<.f><.cc> b,b,c 00110bbb11000000FBBBCCCCCC0QQQQQ.  */
+{ "fmul", 0x30C00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fmul<.f> a,b,u6 00110bbb01000000FBBBuuuuuuAAAAAA.  */
+{ "fmul", 0x30400000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fmul<.f> 0,b,u6 00110bbb01000000FBBBuuuuuu111110.  */
+{ "fmul", 0x3040003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* fmul<.f><.cc> b,b,u6 00110bbb11000000FBBBuuuuuu1QQQQQ.  */
+{ "fmul", 0x30C00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmul<.f> b,b,s12 00110bbb10000000FBBBssssssSSSSSS.  */
+{ "fmul", 0x30800000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fmul<.f> a,limm,c 0011011000000000F111CCCCCCAAAAAA.  */
+{ "fmul", 0x36007000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, RC }, { C_F }},
+
+/* fmul<.f> a,b,limm 00110bbb00000000FBBB111110AAAAAA.  */
+{ "fmul", 0x30000F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, LIMM }, { C_F }},
+
+/* fmul<.f> 0,limm,c 0011011000000000F111CCCCCC111110.  */
+{ "fmul", 0x3600703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F }},
+
+/* fmul<.f> 0,b,limm 00110bbb00000000FBBB111110111110.  */
+{ "fmul", 0x30000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, LIMM }, { C_F }},
+
+/* fmul<.f><.cc> 0,limm,c 0011011011000000F111CCCCCC0QQQQQ.  */
+{ "fmul", 0x36C07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* fmul<.f><.cc> b,b,limm 00110bbb11000000FBBB1111100QQQQQ.  */
+{ "fmul", 0x30C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* fmul<.f> a,limm,u6 0011011001000000F111uuuuuuAAAAAA.  */
+{ "fmul", 0x36407000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmul<.f> 0,limm,u6 0011011001000000F111uuuuuu111110.  */
+{ "fmul", 0x3640703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmul<.f><.cc> 0,limm,u6 0011011011000000F111uuuuuu1QQQQQ.  */
+{ "fmul", 0x36C07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmul<.f> 0,limm,s12 0011011010000000F111ssssssSSSSSS.  */
+{ "fmul", 0x36807000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* fmul<.f> a,limm,limm 0011011000000000F111111110AAAAAA.  */
+{ "fmul", 0x36007F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* fmul<.f> 0,limm,limm 0011011000000000F111111110111110.  */
+{ "fmul", 0x36007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* fmul<.f><.cc> 0,limm,limm 0011011011000000F1111111100QQQQQ.  */
+{ "fmul", 0x36C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* fsadd a,b,c 00110bbb000000010BBBCCCCCCAAAAAA.  */
+{ "fsadd", 0x30010000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }},
+
+/* fsadd 0,b,c 00110bbb000000010BBBCCCCCC111110.  */
+{ "fsadd", 0x3001003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }},
+
+/* fsadd<.cc> b,b,c 00110bbb110000010BBBCCCCCC0QQQQQ.  */
+{ "fsadd", 0x30C10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }},
+
+/* fsadd a,b,u6 00110bbb010000010BBBuuuuuuAAAAAA.  */
+{ "fsadd", 0x30410000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fsadd 0,b,u6 00110bbb010000010BBBuuuuuu111110.  */
+{ "fsadd", 0x3041003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fsadd<.cc> b,b,u6 00110bbb110000010BBBuuuuuu1QQQQQ.  */
+{ "fsadd", 0x30C10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fsadd b,b,s12 00110bbb100000010BBBssssssSSSSSS.  */
+{ "fsadd", 0x30810000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fsadd a,limm,c 00110110000000010111CCCCCCAAAAAA.  */
+{ "fsadd", 0x36017000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }},
+
+/* fsadd a,b,limm 00110bbb000000010BBB111110AAAAAA.  */
+{ "fsadd", 0x30010F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }},
+
+/* fsadd 0,limm,c 00110110000000010111CCCCCC111110.  */
+{ "fsadd", 0x3601703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }},
+
+/* fsadd 0,b,limm 00110bbb000000010BBB111110111110.  */
+{ "fsadd", 0x30010FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }},
+
+/* fsadd<.cc> b,b,limm 00110bbb110000010BBB1111100QQQQQ.  */
+{ "fsadd", 0x30C10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fsadd<.cc> 0,limm,c 00110110110000010111CCCCCC0QQQQQ.  */
+{ "fsadd", 0x36C17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fsadd a,limm,u6 00110110010000010111uuuuuuAAAAAA.  */
+{ "fsadd", 0x36417000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsadd 0,limm,u6 00110110010000010111uuuuuu111110.  */
+{ "fsadd", 0x3641703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsadd<.cc> 0,limm,u6 00110110110000010111uuuuuu1QQQQQ.  */
+{ "fsadd", 0x36C17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fsadd 0,limm,s12 00110110100000010111ssssssSSSSSS.  */
+{ "fsadd", 0x36817000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fsadd a,limm,limm 00110110000000010111111110AAAAAA.  */
+{ "fsadd", 0x36017F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fsadd 0,limm,limm 00110110000000010111111110111110.  */
+{ "fsadd", 0x36017FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fsadd<.cc> 0,limm,limm 001101101100000101111111100QQQQQ.  */
+{ "fsadd", 0x36C17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fscmp b,c 00110bbb000000111BBBCCCCCC000000.  */
+{ "fscmp", 0x30038000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { 0 }},
+
+/* fscmp<.cc> b,c 00110bbb110000111BBBCCCCCC0QQQQQ.  */
+{ "fscmp", 0x30C38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { C_CC }},
+
+/* fscmp b,u6 00110bbb010000111BBBuuuuuu000000.  */
+{ "fscmp", 0x30438000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { 0 }},
+
+/* fscmp<.cc> b,u6 00110bbb110000111BBBuuuuuu1QQQQQ.  */
+{ "fscmp", 0x30C38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { C_CC }},
+
+/* fscmp b,s12 00110bbb100000111BBBssssssSSSSSS.  */
+{ "fscmp", 0x30838000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, SIMM12_20 }, { 0 }},
+
+/* fscmp limm,c 00110110000000111111CCCCCC000000.  */
+{ "fscmp", 0x3603F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { 0 }},
+
+/* fscmp b,limm 00110bbb000000111BBB111110000000.  */
+{ "fscmp", 0x30038F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { 0 }},
+
+/* fscmp<.cc> b,limm 00110bbb110000111BBB1111100QQQQQ.  */
+{ "fscmp", 0x30C38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { C_CC }},
+
+/* fscmp<.cc> limm,c 00110110110000111111CCCCCC0QQQQQ.  */
+{ "fscmp", 0x36C3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { C_CC }},
+
+/* fscmp limm,u6 00110110010000111111uuuuuu000000.  */
+{ "fscmp", 0x3643F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { 0 }},
+
+/* fscmp<.cc> limm,u6 00110110110000111111uuuuuu1QQQQQ.  */
+{ "fscmp", 0x36C3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* fscmp limm,s12 00110110100000111111ssssssSSSSSS.  */
+{ "fscmp", 0x3683F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, SIMM12_20 }, { 0 }},
+
+/* fscmp limm,limm 00110110000000111111111110000000.  */
+{ "fscmp", 0x3603FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { 0 }},
+
+/* fscmp<.cc> limm,limm 001101101100001111111111100QQQQQ.  */
+{ "fscmp", 0x36C3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { C_CC }},
+
+/* fscmpf b,c 00110bbb000001001BBBCCCCCC000000.  */
+{ "fscmpf", 0x30048000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { 0 }},
+
+/* fscmpf<.cc> b,c 00110bbb110001001BBBCCCCCC0QQQQQ.  */
+{ "fscmpf", 0x30C48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { C_CC }},
+
+/* fscmpf b,u6 00110bbb010001001BBBuuuuuu000000.  */
+{ "fscmpf", 0x30448000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { 0 }},
+
+/* fscmpf<.cc> b,u6 00110bbb110001001BBBuuuuuu1QQQQQ.  */
+{ "fscmpf", 0x30C48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { C_CC }},
+
+/* fscmpf b,s12 00110bbb100001001BBBssssssSSSSSS.  */
+{ "fscmpf", 0x30848000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, SIMM12_20 }, { 0 }},
+
+/* fscmpf limm,c 00110110000001001111CCCCCC000000.  */
+{ "fscmpf", 0x3604F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { 0 }},
+
+/* fscmpf b,limm 00110bbb000001001BBB111110000000.  */
+{ "fscmpf", 0x30048F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { 0 }},
+
+/* fscmpf<.cc> b,limm 00110bbb110001001BBB1111100QQQQQ.  */
+{ "fscmpf", 0x30C48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { C_CC }},
+
+/* fscmpf<.cc> limm,c 00110110110001001111CCCCCC0QQQQQ.  */
+{ "fscmpf", 0x36C4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { C_CC }},
+
+/* fscmpf limm,u6 00110110010001001111uuuuuu000000.  */
+{ "fscmpf", 0x3644F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { 0 }},
+
+/* fscmpf<.cc> limm,u6 00110110110001001111uuuuuu1QQQQQ.  */
+{ "fscmpf", 0x36C4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* fscmpf limm,s12 00110110100001001111ssssssSSSSSS.  */
+{ "fscmpf", 0x3684F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, SIMM12_20 }, { 0 }},
+
+/* fscmpf limm,limm 00110110000001001111111110000000.  */
+{ "fscmpf", 0x3604FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { 0 }},
+
+/* fscmpf<.cc> limm,limm 001101101100010011111111100QQQQQ.  */
+{ "fscmpf", 0x36C4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { C_CC }},
+
+/* fsdiv a,b,c 00110bbb000001110BBBCCCCCCAAAAAA.  */
+{ "fsdiv", 0x30070000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }},
+
+/* fsdiv 0,b,c 00110bbb000001110BBBCCCCCC111110.  */
+{ "fsdiv", 0x3007003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }},
+
+/* fsdiv<.cc> b,b,c 00110bbb110001110BBBCCCCCC0QQQQQ.  */
+{ "fsdiv", 0x30C70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }},
+
+/* fsdiv a,b,u6 00110bbb010001110BBBuuuuuuAAAAAA.  */
+{ "fsdiv", 0x30470000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fsdiv 0,b,u6 00110bbb010001110BBBuuuuuu111110.  */
+{ "fsdiv", 0x3047003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fsdiv<.cc> b,b,u6 00110bbb110001110BBBuuuuuu1QQQQQ.  */
+{ "fsdiv", 0x30C70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fsdiv b,b,s12 00110bbb100001110BBBssssssSSSSSS.  */
+{ "fsdiv", 0x30870000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fsdiv a,limm,c 00110110000001110111CCCCCCAAAAAA.  */
+{ "fsdiv", 0x36077000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }},
+
+/* fsdiv a,b,limm 00110bbb000001110BBB111110AAAAAA.  */
+{ "fsdiv", 0x30070F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }},
+
+/* fsdiv 0,limm,c 00110110000001110111CCCCCC111110.  */
+{ "fsdiv", 0x3607703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }},
+
+/* fsdiv 0,b,limm 00110bbb000001110BBB111110111110.  */
+{ "fsdiv", 0x30070FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }},
+
+/* fsdiv<.cc> b,b,limm 00110bbb110001110BBB1111100QQQQQ.  */
+{ "fsdiv", 0x30C70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fsdiv<.cc> 0,limm,c 00110110110001110111CCCCCC0QQQQQ.  */
+{ "fsdiv", 0x36C77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fsdiv a,limm,u6 00110110010001110111uuuuuuAAAAAA.  */
+{ "fsdiv", 0x36477000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsdiv 0,limm,u6 00110110010001110111uuuuuu111110.  */
+{ "fsdiv", 0x3647703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsdiv<.cc> 0,limm,u6 00110110110001110111uuuuuu1QQQQQ.  */
+{ "fsdiv", 0x36C77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fsdiv 0,limm,s12 00110110100001110111ssssssSSSSSS.  */
+{ "fsdiv", 0x36877000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fsdiv a,limm,limm 00110110000001110111111110AAAAAA.  */
+{ "fsdiv", 0x36077F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fsdiv 0,limm,limm 00110110000001110111111110111110.  */
+{ "fsdiv", 0x36077FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fsdiv<.cc> 0,limm,limm 001101101100011101111111100QQQQQ.  */
+{ "fsdiv", 0x36C77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fsmadd a,b,c 00110bbb000001010BBBCCCCCCAAAAAA.  */
+{ "fsmadd", 0x30050000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }},
+
+/* fsmadd 0,b,c 00110bbb000001010BBBCCCCCC111110.  */
+{ "fsmadd", 0x3005003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }},
+
+/* fsmadd<.cc> b,b,c 00110bbb110001010BBBCCCCCC0QQQQQ.  */
+{ "fsmadd", 0x30C50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }},
+
+/* fsmadd a,b,u6 00110bbb010001010BBBuuuuuuAAAAAA.  */
+{ "fsmadd", 0x30450000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fsmadd 0,b,u6 00110bbb010001010BBBuuuuuu111110.  */
+{ "fsmadd", 0x3045003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fsmadd<.cc> b,b,u6 00110bbb110001010BBBuuuuuu1QQQQQ.  */
+{ "fsmadd", 0x30C50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fsmadd b,b,s12 00110bbb100001010BBBssssssSSSSSS.  */
+{ "fsmadd", 0x30850000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fsmadd a,limm,c 00110110000001010111CCCCCCAAAAAA.  */
+{ "fsmadd", 0x36057000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }},
+
+/* fsmadd a,b,limm 00110bbb000001010BBB111110AAAAAA.  */
+{ "fsmadd", 0x30050F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }},
+
+/* fsmadd 0,limm,c 00110110000001010111CCCCCC111110.  */
+{ "fsmadd", 0x3605703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }},
+
+/* fsmadd 0,b,limm 00110bbb000001010BBB111110111110.  */
+{ "fsmadd", 0x30050FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }},
+
+/* fsmadd<.cc> b,b,limm 00110bbb110001010BBB1111100QQQQQ.  */
+{ "fsmadd", 0x30C50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fsmadd<.cc> 0,limm,c 00110110110001010111CCCCCC0QQQQQ.  */
+{ "fsmadd", 0x36C57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fsmadd a,limm,u6 00110110010001010111uuuuuuAAAAAA.  */
+{ "fsmadd", 0x36457000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsmadd 0,limm,u6 00110110010001010111uuuuuu111110.  */
+{ "fsmadd", 0x3645703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsmadd<.cc> 0,limm,u6 00110110110001010111uuuuuu1QQQQQ.  */
+{ "fsmadd", 0x36C57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fsmadd 0,limm,s12 00110110100001010111ssssssSSSSSS.  */
+{ "fsmadd", 0x36857000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fsmadd a,limm,limm 00110110000001010111111110AAAAAA.  */
+{ "fsmadd", 0x36057F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fsmadd 0,limm,limm 00110110000001010111111110111110.  */
+{ "fsmadd", 0x36057FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fsmadd<.cc> 0,limm,limm 001101101100010101111111100QQQQQ.  */
+{ "fsmadd", 0x36C57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fsmsub a,b,c 00110bbb000001100BBBCCCCCCAAAAAA.  */
+{ "fsmsub", 0x30060000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }},
+
+/* fsmsub 0,b,c 00110bbb000001100BBBCCCCCC111110.  */
+{ "fsmsub", 0x3006003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }},
+
+/* fsmsub<.cc> b,b,c 00110bbb110001100BBBCCCCCC0QQQQQ.  */
+{ "fsmsub", 0x30C60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }},
+
+/* fsmsub a,b,u6 00110bbb010001100BBBuuuuuuAAAAAA.  */
+{ "fsmsub", 0x30460000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fsmsub 0,b,u6 00110bbb010001100BBBuuuuuu111110.  */
+{ "fsmsub", 0x3046003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fsmsub<.cc> b,b,u6 00110bbb110001100BBBuuuuuu1QQQQQ.  */
+{ "fsmsub", 0x30C60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fsmsub b,b,s12 00110bbb100001100BBBssssssSSSSSS.  */
+{ "fsmsub", 0x30860000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fsmsub a,limm,c 00110110000001100111CCCCCCAAAAAA.  */
+{ "fsmsub", 0x36067000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }},
+
+/* fsmsub a,b,limm 00110bbb000001100BBB111110AAAAAA.  */
+{ "fsmsub", 0x30060F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }},
+
+/* fsmsub 0,limm,c 00110110000001100111CCCCCC111110.  */
+{ "fsmsub", 0x3606703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }},
+
+/* fsmsub 0,b,limm 00110bbb000001100BBB111110111110.  */
+{ "fsmsub", 0x30060FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }},
+
+/* fsmsub<.cc> b,b,limm 00110bbb110001100BBB1111100QQQQQ.  */
+{ "fsmsub", 0x30C60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fsmsub<.cc> 0,limm,c 00110110110001100111CCCCCC0QQQQQ.  */
+{ "fsmsub", 0x36C67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fsmsub a,limm,u6 00110110010001100111uuuuuuAAAAAA.  */
+{ "fsmsub", 0x36467000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsmsub 0,limm,u6 00110110010001100111uuuuuu111110.  */
+{ "fsmsub", 0x3646703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsmsub<.cc> 0,limm,u6 00110110110001100111uuuuuu1QQQQQ.  */
+{ "fsmsub", 0x36C67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fsmsub 0,limm,s12 00110110100001100111ssssssSSSSSS.  */
+{ "fsmsub", 0x36867000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fsmsub a,limm,limm 00110110000001100111111110AAAAAA.  */
+{ "fsmsub", 0x36067F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fsmsub 0,limm,limm 00110110000001100111111110111110.  */
+{ "fsmsub", 0x36067FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fsmsub<.cc> 0,limm,limm 001101101100011001111111100QQQQQ.  */
+{ "fsmsub", 0x36C67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fsmul a,b,c 00110bbb000000000BBBCCCCCCAAAAAA.  */
+{ "fsmul", 0x30000000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }},
+
+/* fsmul 0,b,c 00110bbb000000000BBBCCCCCC111110.  */
+{ "fsmul", 0x3000003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }},
+
+/* fsmul<.cc> b,b,c 00110bbb110000000BBBCCCCCC0QQQQQ.  */
+{ "fsmul", 0x30C00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }},
+
+/* fsmul a,b,u6 00110bbb010000000BBBuuuuuuAAAAAA.  */
+{ "fsmul", 0x30400000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fsmul 0,b,u6 00110bbb010000000BBBuuuuuu111110.  */
+{ "fsmul", 0x3040003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fsmul<.cc> b,b,u6 00110bbb110000000BBBuuuuuu1QQQQQ.  */
+{ "fsmul", 0x30C00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fsmul b,b,s12 00110bbb100000000BBBssssssSSSSSS.  */
+{ "fsmul", 0x30800000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fsmul a,limm,c 00110110000000000111CCCCCCAAAAAA.  */
+{ "fsmul", 0x36007000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }},
+
+/* fsmul a,b,limm 00110bbb000000000BBB111110AAAAAA.  */
+{ "fsmul", 0x30000F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }},
+
+/* fsmul 0,limm,c 00110110000000000111CCCCCC111110.  */
+{ "fsmul", 0x3600703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }},
+
+/* fsmul 0,b,limm 00110bbb000000000BBB111110111110.  */
+{ "fsmul", 0x30000FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }},
+
+/* fsmul<.cc> b,b,limm 00110bbb110000000BBB1111100QQQQQ.  */
+{ "fsmul", 0x30C00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fsmul<.cc> 0,limm,c 00110110110000000111CCCCCC0QQQQQ.  */
+{ "fsmul", 0x36C07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fsmul a,limm,u6 00110110010000000111uuuuuuAAAAAA.  */
+{ "fsmul", 0x36407000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsmul 0,limm,u6 00110110010000000111uuuuuu111110.  */
+{ "fsmul", 0x3640703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fsmul<.cc> 0,limm,u6 00110110110000000111uuuuuu1QQQQQ.  */
+{ "fsmul", 0x36C07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fsmul 0,limm,s12 00110110100000000111ssssssSSSSSS.  */
+{ "fsmul", 0x36807000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fsmul a,limm,limm 00110110000000000111111110AAAAAA.  */
+{ "fsmul", 0x36007F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fsmul 0,limm,limm 00110110000000000111111110111110.  */
+{ "fsmul", 0x36007FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fsmul<.cc> 0,limm,limm 001101101100000001111111100QQQQQ.  */
+{ "fsmul", 0x36C07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fssqrt b,c 00110bbb001011110BBBCCCCCC000000.  */
+{ "fssqrt", 0x302F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { 0 }},
+
+/* fssqrt 0,c 00110110001011110111CCCCCC000000.  */
+{ "fssqrt", 0x362F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RC }, { 0 }},
+
+/* fssqrt b,u6 00110bbb011011110BBBuuuuuu000000.  */
+{ "fssqrt", 0x306F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { 0 }},
+
+/* fssqrt 0,u6 00110110011011110111uuuuuu000000.  */
+{ "fssqrt", 0x366F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, UIMM6_20 }, { 0 }},
+
+/* fssqrt b,limm 00110bbb001011110BBB111110000000.  */
+{ "fssqrt", 0x302F0F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { 0 }},
+
+/* fssqrt 0,limm 00110110001011110111111110000000.  */
+{ "fssqrt", 0x362F7F80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM }, { 0 }},
+
+/* fssub a,b,c 00110bbb000000100BBBCCCCCCAAAAAA.  */
+{ "fssub", 0x30020000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }},
+
+/* fssub 0,b,c 00110bbb000000100BBBCCCCCC111110.  */
+{ "fssub", 0x3002003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }},
+
+/* fssub<.cc> b,b,c 00110bbb110000100BBBCCCCCC0QQQQQ.  */
+{ "fssub", 0x30C20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }},
+
+/* fssub a,b,u6 00110bbb010000100BBBuuuuuuAAAAAA.  */
+{ "fssub", 0x30420000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* fssub 0,b,u6 00110bbb010000100BBBuuuuuu111110.  */
+{ "fssub", 0x3042003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* fssub<.cc> b,b,u6 00110bbb110000100BBBuuuuuu1QQQQQ.  */
+{ "fssub", 0x30C20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* fssub b,b,s12 00110bbb100000100BBBssssssSSSSSS.  */
+{ "fssub", 0x30820000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* fssub a,limm,c 00110110000000100111CCCCCCAAAAAA.  */
+{ "fssub", 0x36027000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }},
+
+/* fssub a,b,limm 00110bbb000000100BBB111110AAAAAA.  */
+{ "fssub", 0x30020F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }},
+
+/* fssub 0,limm,c 00110110000000100111CCCCCC111110.  */
+{ "fssub", 0x3602703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }},
+
+/* fssub 0,b,limm 00110bbb000000100BBB111110111110.  */
+{ "fssub", 0x30020FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }},
+
+/* fssub<.cc> b,b,limm 00110bbb110000100BBB1111100QQQQQ.  */
+{ "fssub", 0x30C20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }},
+
+/* fssub<.cc> 0,limm,c 00110110110000100111CCCCCC0QQQQQ.  */
+{ "fssub", 0x36C27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }},
+
+/* fssub a,limm,u6 00110110010000100111uuuuuuAAAAAA.  */
+{ "fssub", 0x36427000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fssub 0,limm,u6 00110110010000100111uuuuuu111110.  */
+{ "fssub", 0x3642703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* fssub<.cc> 0,limm,u6 00110110110000100111uuuuuu1QQQQQ.  */
+{ "fssub", 0x36C27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* fssub 0,limm,s12 00110110100000100111ssssssSSSSSS.  */
+{ "fssub", 0x36827000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* fssub a,limm,limm 00110110000000100111111110AAAAAA.  */
+{ "fssub", 0x36027F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* fssub 0,limm,limm 00110110000000100111111110111110.  */
+{ "fssub", 0x36027FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* fssub<.cc> 0,limm,limm 001101101100001001111111100QQQQQ.  */
+{ "fssub", 0x36C27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* fsub<.f> a,b,c 00110bbb00000010FBBBCCCCCCAAAAAA.  */
+{ "fsub", 0x30020000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, RC }, { C_F }},
+
+/* fsub<.f> 0,b,c 00110bbb00000010FBBBCCCCCC111110.  */
+{ "fsub", 0x3002003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, RC }, { C_F }},
+
+/* fsub<.f><.cc> b,b,c 00110bbb11000010FBBBCCCCCC0QQQQQ.  */
+{ "fsub", 0x30C20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fsub<.f> a,b,u6 00110bbb01000010FBBBuuuuuuAAAAAA.  */
+{ "fsub", 0x30420000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fsub<.f> 0,b,u6 00110bbb01000010FBBBuuuuuu111110.  */
+{ "fsub", 0x3042003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* fsub<.f><.cc> b,b,u6 00110bbb11000010FBBBuuuuuu1QQQQQ.  */
+{ "fsub", 0x30C20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fsub<.f> b,b,s12 00110bbb10000010FBBBssssssSSSSSS.  */
+{ "fsub", 0x30820000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fsub<.f> a,limm,c 0011011000000010F111CCCCCCAAAAAA.  */
+{ "fsub", 0x36027000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, RC }, { C_F }},
+
+/* fsub<.f> a,b,limm 00110bbb00000010FBBB111110AAAAAA.  */
+{ "fsub", 0x30020F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, LIMM }, { C_F }},
+
+/* fsub<.f> 0,limm,c 0011011000000010F111CCCCCC111110.  */
+{ "fsub", 0x3602703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F }},
+
+/* fsub<.f> 0,b,limm 00110bbb00000010FBBB111110111110.  */
+{ "fsub", 0x30020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, LIMM }, { C_F }},
+
+/* fsub<.f><.cc> 0,limm,c 0011011011000010F111CCCCCC0QQQQQ.  */
+{ "fsub", 0x36C27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* fsub<.f><.cc> b,b,limm 00110bbb11000010FBBB1111100QQQQQ.  */
+{ "fsub", 0x30C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* fsub<.f> a,limm,u6 0011011001000010F111uuuuuuAAAAAA.  */
+{ "fsub", 0x36427000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fsub<.f> 0,limm,u6 0011011001000010F111uuuuuu111110.  */
+{ "fsub", 0x3642703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fsub<.f><.cc> 0,limm,u6 0011011011000010F111uuuuuu1QQQQQ.  */
+{ "fsub", 0x36C27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* fsub<.f> 0,limm,s12 0011011010000010F111ssssssSSSSSS.  */
+{ "fsub", 0x36827000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* fsub<.f> a,limm,limm 0011011000000010F111111110AAAAAA.  */
+{ "fsub", 0x36027F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* fsub<.f> 0,limm,limm 0011011000000010F111111110111110.  */
+{ "fsub", 0x36027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* fsub<.f><.cc> 0,limm,limm 0011011011000010F1111111100QQQQQ.  */
+{ "fsub", 0x36C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* fxtr<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA.  */
+{ "fxtr", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* fxtr<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ.  */
+{ "fxtr", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fxtr<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA.  */
+{ "fxtr", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fxtr<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ.  */
+{ "fxtr", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fxtr<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS.  */
+{ "fxtr", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fxtr<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA.  */
+{ "fxtr", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* fxtr<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA.  */
+{ "fxtr", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* fxtr<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ.  */
+{ "fxtr", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* getacc b,c 00101bbb001011110BBBCCCCCC011000.  */
+{ "getacc", 0x282F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* getacc 0,c 00101110001011110111CCCCCC011000.  */
+{ "getacc", 0x2E2F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* getacc b,u6 00101bbb011011110BBBuuuuuu011000.  */
+{ "getacc", 0x286F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* getacc 0,u6 00101110011011110111uuuuuu011000.  */
+{ "getacc", 0x2E6F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* getacc b,limm 00101bbb001011110BBB111110011000.  */
+{ "getacc", 0x282F0F98, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* getacc 0,limm 00101110001011110111111110011000.  */
+{ "getacc", 0x2E2F7F98, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* iaddr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA.  */
+{ "iaddr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* iaddr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ.  */
+{ "iaddr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* iaddr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA.  */
+{ "iaddr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* iaddr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ.  */
+{ "iaddr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* iaddr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS.  */
+{ "iaddr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* iaddr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA.  */
+{ "iaddr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* iaddr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA.  */
+{ "iaddr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ.  */
+{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* invld042e  00100RRRRR101110RRRRRRRRRRRRRRRR.  */
+{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f0e  00100RRRRR101111RRRRRRRRRR00111R.  */
+{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f12  00100RRRRR101111RRRRRRRRRR01001R.  */
+{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f14  00100RRRRR101111RRRRRRRRRR0101RR.  */
+{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f18  00100RRRRR101111RRRRRRRRRR011RRR.  */
+{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f20  00100RRRRR101111RRRRRRRRRR10RRRR.  */
+{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f30  00100RRRRR101111RRRRRRRRRR110RRR.  */
+{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f38  00100RRRRR101111RRRRRRRRRR1110RR.  */
+{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f3c  00100RRRRR101111RRRRRRRRRR11110R.  */
+{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f3e  00100RRRRR101111RRRRRRRRRR111110.  */
+{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f3f08  00100RRRRR101111R001RRRRRR111111.  */
+{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f3f10  00100RRRRR101111R01RRRRRRR111111.  */
+{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld042f3f20  00100RRRRR101111R1RRRRRRRR111111.  */
+{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld0506  00101RRRRR00011RRRRRRRRRRRRRRRRR.  */
+{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld050a  00101RRRRR00101RRRRRRRRRRRRRRRRR.  */
+{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld050c  00101RRRRR00110RRRRRRRRRRRRRRRRR.  */
+{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld051e  00101RRRRR01111RRRRRRRRRRRRRRRRR.  */
+{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld0520  00101RRRRR100RRRRRRRRRRRRRRRRRRR.  */
+{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld0528  00101RRRRR1010RRRRRRRRRRRRRRRRRR.  */
+{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052c  00101RRRRR10110RRRRRRRRRRRRRRRRR.  */
+{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052e  00101RRRRR101110RRRRRRRRRRRRRRRR.  */
+{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f02  00101RRRRR101111RRRRRRRRRR00001R.  */
+{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f04  00101RRRRR101111RRRRRRRRRR0001RR.  */
+{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f14  00101RRRRR101111RRRRRRRRRR0101RR.  */
+{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f18  00101RRRRR101111RRRRRRRRRR011RRR.  */
+{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f20  00101RRRRR101111RRRRRRRRRR10RRRR.  */
+{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f30  00101RRRRR101111RRRRRRRRRR110RRR.  */
+{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f38  00101RRRRR101111RRRRRRRRRR1110RR.  */
+{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f3c  00101RRRRR101111RRRRRRRRRR11110R.  */
+{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f3e  00101RRRRR101111RRRRRRRRRR111110.  */
+{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld052f3f00  00101RRRRR101111RRRRRRRRRR111111.  */
+{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* invld07  00111RRRRRRRRRRRRRRRRRRRRRRRRRRR.  */
+{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+
+/* j c 00100RRR001000000RRRCCCCCCRRRRRR.  */
+{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* j BLINK 00100RRR001000000RRR011111RRRRRR.  */
+{ "j", 0x202007C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 }},
+
+/* j.F ILINK1 00100RRR001000001RRR011101RRRRRR.  */
+{ "j", 0x20208740, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK1, BRAKETdup }, { C_FHARD }},
+
+/* j.F ILINK2 00100RRR001000001RRR011110RRRRRR.  */
+{ "j", 0x20208780, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK2, BRAKETdup }, { C_FHARD }},
+
+/* jcc c 00100RRR111000000RRRCCCCCC0QQQQQ.  */
+{ "j", 0x20E00000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jcc BLINK 00100RRR111000000RRR0111110QQQQQ.  */
+{ "j", 0x20E007C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC }},
+
+/* j.Fcc ILINK1 00100RRR111000001RRR0111010QQQQQ.  */
+{ "j", 0x20E08740, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK1, BRAKETdup }, { C_FHARD, C_CC }},
+
+/* j.Fcc ILINK2 00100RRR111000001RRR0111100QQQQQ.  */
+{ "j", 0x20E08780, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK2, BRAKETdup }, { C_FHARD, C_CC }},
+
+/* j.D c 00100RRR001000010RRRCCCCCCRRRRRR.  */
+{ "j", 0x20210000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* j.D BLINK 00100RRR001000010RRR011111RRRRRR.  */
+{ "j", 0x202107C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD }},
+
+/* jcc.D c 00100RRR111000010RRRCCCCCC0QQQQQ.  */
+{ "j", 0x20E10000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* jcc.D BLINK 00100RRR111000010RRR0111110QQQQQ.  */
+{ "j", 0x20E107C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* j c 00100RRR00100000RRRRCCCCCCRRRRRR.  */
+{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* j BLINK 00100RRR00100000RRRR011111RRRRRR.  */
+{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 }},
+
+/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ.  */
+{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jcc BLINK 00100RRR11100000RRRR0111110QQQQQ.  */
+{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC }},
+
+/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR.  */
+{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* j.D BLINK 00100RRR00100001RRRR011111RRRRRR.  */
+{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD }},
+
+/* jcc.D c 00100RRR11100001RRRRCCCCCC0QQQQQ.  */
+{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* jcc.D BLINK 00100RRR11100001RRRR0111110QQQQQ.  */
+{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* j s12 00100RRR101000000RRRssssssSSSSSS.  */
+{ "j", 0x20A00000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* j.D s12 00100RRR101000010RRRssssssSSSSSS.  */
+{ "j", 0x20A10000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* j s12 00100RRR10100000RRRRssssssSSSSSS.  */
+{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* j.D s12 00100RRR10100001RRRRssssssSSSSSS.  */
+{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* j u6 00100RRR011000000RRRuuuuuuRRRRRR.  */
+{ "j", 0x20600000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jcc u6 00100RRR111000000RRRuuuuuu1QQQQQ.  */
+{ "j", 0x20E00020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC }},
+
+/* j.D u6 00100RRR011000010RRRuuuuuuRRRRRR.  */
+{ "j", 0x20610000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* jcc.D u6 00100RRR111000010RRRuuuuuu1QQQQQ.  */
+{ "j", 0x20E10020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR.  */
+{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ.  */
+{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC }},
+
+/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR.  */
+{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* jcc.D u6 00100RRR11100001RRRRuuuuuu1QQQQQ.  */
+{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* j limm 00100RRR001000000RRR111110RRRRRR.  */
+{ "j", 0x20200F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jcc limm 00100RRR111000000RRR1111100QQQQQ.  */
+{ "j", 0x20E00F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { C_CC }},
+
+/* j limm 00100RRR00100000RRRR111110RRRRRR.  */
+{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jcc limm 00100RRR11100000RRRR1111100QQQQQ.  */
+{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }},
+
+/* jeq_s BLINK 0111110011100000.  */
+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* jeq_s BLINK 0111110011100000.  */
+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* jl c 00100RRR001000100RRRCCCCCCRRRRRR.  */
+{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* jlcc c 00100RRR111000100RRRCCCCCC0QQQQQ.  */
+{ "jl", 0x20E20000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jl.D c 00100RRR001000110RRRCCCCCCRRRRRR.  */
+{ "jl", 0x20230000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* jlcc.D c 00100RRR111000110RRRCCCCCC0QQQQQ.  */
+{ "jl", 0x20E30000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR.  */
+{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ.  */
+{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR.  */
+{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* jlcc.D c 00100RRR11100011RRRRCCCCCC0QQQQQ.  */
+{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* jl s12 00100RRR101000100RRRssssssSSSSSS.  */
+{ "jl", 0x20A20000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* jl.D s12 00100RRR101000110RRRssssssSSSSSS.  */
+{ "jl", 0x20A30000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* jl s12 00100RRR10100010RRRRssssssSSSSSS.  */
+{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS.  */
+{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* jl u6 00100RRR011000100RRRuuuuuuRRRRRR.  */
+{ "jl", 0x20620000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jlcc u6 00100RRR111000100RRRuuuuuu1QQQQQ.  */
+{ "jl", 0x20E20020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC }},
+
+/* jl.D u6 00100RRR011000110RRRuuuuuuRRRRRR.  */
+{ "jl", 0x20630000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* jlcc.D u6 00100RRR111000110RRRuuuuuu1QQQQQ.  */
+{ "jl", 0x20E30020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR.  */
+{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ.  */
+{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC }},
+
+/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR.  */
+{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* jlcc.D u6 00100RRR11100011RRRRuuuuuu1QQQQQ.  */
+{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* jl limm 00100RRR001000100RRR111110RRRRRR.  */
+{ "jl", 0x20220F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jlcc limm 00100RRR111000100RRR1111100QQQQQ.  */
+{ "jl", 0x20E20F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { C_CC }},
+
+/* jl limm 00100RRR00100010RRRR111110RRRRRR.  */
+{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ.  */
+{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }},
+
+/* jli_s u10 010110uuuuuuuuuu.  */
+{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD1, { UIMM10_6_S }, { 0 }},
+
+/* jl_s b 01111bbb01000000.  */
+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* jl_s.D b 01111bbb01100000.  */
+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* jl_s b 01111bbb01000000.  */
+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* jl_s.D b 01111bbb01100000.  */
+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* jne_s BLINK 0111110111100000.  */
+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* jne_s BLINK 0111110111100000.  */
+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* j_s b 01111bbb00000000.  */
+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* j_s.D b 01111bbb00100000.  */
+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* j_s BLINK 0111111011100000.  */
+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* j_s.D BLINK 0111111111100000.  */
+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD }},
+
+/* j_s b 01111bbb00000000.  */
+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* j_s.D b 01111bbb00100000.  */
+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* j_s BLINK 0111111011100000.  */
+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* j_s.D BLINK 0111111111100000.  */
+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD }},
+
+/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR.  */
+{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
+
+/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ.  */
+{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { C_CC }},
+
+/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR.  */
+{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ.  */
+{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { C_CC }},
+
+/* kflag s12 00100RRR101010011RRRssssssSSSSSS.  */
+{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { SIMM12_20 }, { 0 }},
+
+/* kflag limm 00100RRR001010011RRR111110RRRRRR.  */
+{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ.  */
+{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { C_CC }},
+
+/* ld<.di><.aa><.x><zz> a,b 00010bbb000000000BBBDaaZZXAAAAAA.  */
+{ "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> a,b,c 00100bbbaa110ZZXDBBBCCCCCCAAAAAA.  */
+{ "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.aa><.x><zz> 0,b 00010bbb000000000BBBDaaZZX111110.  */
+{ "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> 0,b,c 00100bbbaa110ZZXDBBBCCCCCC111110.  */
+{ "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.aa><.x><zz> a,b,s9 00010bbbssssssssSBBBDaaZZXAAAAAA.  */
+{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> 0,b,s9 00010bbbssssssssSBBBDaaZZX111110.  */
+{ "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+/* ld<.di><.x><zz> a,limm 00010110000000000111DRRZZXAAAAAA.  */
+{ "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA.  */
+{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.aa><.x><zz> a,limm,c 00100110aa110ZZXD111CCCCCCAAAAAA.  */
+{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.x><zz> a,limm,c 00100110RR110ZZXD111CCCCCCAAAAAA.  */
+{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }},
+
+/* ld<.di><.x><zz> 0,limm 00010110000000000111DRRZZX111110.  */
+{ "ld", 0x1600703E, 0xFFFFF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> 0,b,limm 00100bbbaa110ZZXDBBB111110111110.  */
+{ "ld", 0x20300FBE, 0xF8380FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.aa><.x><zz> 0,limm,c 00100110aa110ZZXD111CCCCCC111110.  */
+{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.x><zz> 0,limm,c 00100110RR110ZZXD111CCCCCC111110.  */
+{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }},
+
+/* ld<.di><.aa><.x><zz> a,limm,s9 00010110ssssssssS111DaaZZXAAAAAA.  */
+{ "ld", 0x16007000, 0xFF007000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> 0,limm,s9 00010110ssssssssS111DaaZZX111110.  */
+{ "ld", 0x1600703E, 0xFF00703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+/* ld<.di><.aa><.x><zz> a,limm,limm 00100110aa110ZZXD111111110AAAAAA.  */
+{ "ld", 0x26307F80, 0xFF387FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ld<.di><.aa><.x><zz> 0,limm,limm 00100110aa110ZZXD111111110111110.  */
+{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+/* ldb_s a,b,c 01100bbbccc01aaa.  */
+{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
+
+/* ldb_s c,b,u5 10001bbbcccuuuuu.  */
+{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }},
+
+/* ldb_s b,SP,u7 11000bbb001uuuuu.  */
+{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ldb_s R0,GP,s9 1100101sssssssss.  */
+{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { 0 }},
+
+/* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA.  */
+{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA.  */
+{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }},
+
+/* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110.  */
+{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110.  */
+{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }},
+
+/* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA.  */
+{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110.  */
+{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA.  */
+{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20 }},
+
+/* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA.  */
+{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }},
+
+/* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA.  */
+{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }},
+
+/* ldd<.di> 0,limm 00010110000000000111DRR110111110.  */
+{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20 }},
+
+/* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110.  */
+{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }},
+
+/* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110.  */
+{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }},
+
+/* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA.  */
+{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110.  */
+{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldh_s a,b,c 01100bbbccc10aaa.  */
+{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
+
+/* ldh_s c,b,u6 10010bbbcccuuuuu.  */
+{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
+
+/* ldh_s.X c,b,u6 10011bbbcccuuuuu.  */
+{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }},
+
+/* ldh_s R0,GP,s10 1100110sssssssss.  */
+{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }},
+
+/* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR.  */
+{ "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* ldi 0,c 0010011000100110R111CCCCCCRRRRRR.  */
+{ "ldi", 0x26267000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* ldi b,u6 00100bbb01100110RBBBuuuuuu000000.  */
+{ "ldi", 0x20660000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* ldi 0,u6 0010011001100110R111uuuuuu000000.  */
+{ "ldi", 0x26667000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* ldi<.cc> b,u6 00100bbb11100110RBBBuuuuuu1QQQQQ.  */
+{ "ldi", 0x20E60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, MEMORY, CD2, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* ldi<.cc> 0,u6 0010011011100110R111uuuuuu1QQQQQ.  */
+{ "ldi", 0x26E67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, MEMORY, CD2, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* ldi b,s12 00100bbb10100110RBBBssssssSSSSSS.  */
+{ "ldi", 0x20A60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* ldi 0,s12 0010011010100110R111ssssssSSSSSS.  */
+{ "ldi", 0x26A67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* ldi b,limm 00100bbb00100110RBBB111110RRRRRR.  */
+{ "ldi", 0x20260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* ldi 0,limm 0010011000100110R111111110RRRRRR.  */
+{ "ldi", 0x26267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* ldi_s b,u7 01010bbbUUUU1uuu.  */
+{ "ldi_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB_S, BRAKET, UIMM7_13_S, BRAKETdup }, { 0 }},
+
+/* ldm a,u6,b 00101bbb01001100RBBBRuuuuuAAAAAA.  */
+{ "ldm", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, RB }, { 0 }},
+
+/* ldm 0,u6,b 00101bbb01001100RBBBRuuuuu111110.  */
+{ "ldm", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, RB }, { 0 }},
+
+/* ldm a,u6,limm 0010111001001100R111RuuuuuAAAAAA.  */
+{ "ldm", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, LIMM }, { 0 }},
+
+/* ldm 0,u6,limm 0010111001001100R111Ruuuuu111110.  */
+{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }},
+
+/* ldw_s a,b,c 01100bbbccc10aaa.  */
+{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
+
+/* ldw_s c,b,u6 10010bbbcccuuuuu.  */
+{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
+
+/* ldw_s.X c,b,u6 10011bbbcccuuuuu.  */
+{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }},
+
+/* ldw_s R0,GP,s10 1100110sssssssss.  */
+{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }},
+
+/* ld_s a,b,c 01100bbbccc00aaa.  */
+{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
+
+/* ld_s.AS a,b,c 01001bbbccc00aaa.  */
+{ "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_AS }},
+
+/* ld_s R0,h,u5 01000U00hhhuu1HH.  */
+{ "ld_s", 0x00004004, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R0_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s R1,h,u5 01000U01hhhuu1HH.  */
+{ "ld_s", 0x00004104, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R1_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s R2,h,u5 01000U10hhhuu1HH.  */
+{ "ld_s", 0x00004204, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R2_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s R3,h,u5 01000U11hhhuu1HH.  */
+{ "ld_s", 0x00004304, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R3_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s b,SP,u7 11000bbb000uuuuu.  */
+{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s c,b,u7 10000bbbcccuuuuu.  */
+{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s b,PCL,u10 11010bbbuuuuuuuu.  */
+{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, PCL_S, UIMM10_A32_8_S, BRAKETdup }, { 0 }},
+
+/* ld_s R0,GP,s11 1100100sssssssss.  */
+{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM11_A32_7_S, BRAKETdup }, { 0 }},
+
+/* ld_s R1,GP,s11 01010SSSSSS00sss.  */
+{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
+
+/* leave_s u7 11000UUU110uuuu0.  */
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM7_11_S }, { 0 }},
+
+/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000.  */
+{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,c 0010011000101111D111CCCCCC010000.  */
+{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000.  */
+{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000.  */
+{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> b,limm 00100bbb00101111DBBB111110010000.  */
+{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,limm 0010011000101111D111111110010000.  */
+{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010.  */
+{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> 0,c 0010011000101111D111CCCCCC010010.  */
+{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010.  */
+{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010.  */
+{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> b,limm 00100bbb00101111DBBB111110010010.  */
+{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> 0,limm 0010011000101111D111111110010010.  */
+{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* lp s13 00100RRR101010000RRRssssssSSSSSS.  */
+{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }},
+
+/* lp s13 00100RRR10101000RRRRssssssSSSSSS.  */
+{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }},
+
+/* lp<cc> u7 00100RRR111010000RRRuuuuuu1QQQQQ.  */
+{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }},
+
+/* lp u7 00100RRR011010000RRRuuuuuuRRRRRR.  */
+{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }},
+
+/* lp<cc> u7 00100RRR11101000RRRRuuuuuu1QQQQQ.  */
+{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }},
+
+/* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR.  */
+{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }},
+
+/* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR.  */
+{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr 0,c 00100110001010100111CCCCCCRRRRRR.  */
+{ "lr", 0x262A7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR.  */
+{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr 0,c 0010011000101010R111CCCCCCRRRRRR.  */
+{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr b,u6 00100bbb011010100BBBuuuuuu000000.  */
+{ "lr", 0x206A0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr 0,u6 00100110011010100111uuuuuu000000.  */
+{ "lr", 0x266A7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr b,u6 00100bbb01101010RBBBuuuuuu000000.  */
+{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr 0,u6 0010011001101010R111uuuuuu000000.  */
+{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr b,s12 00100bbb101010100BBBssssssSSSSSS.  */
+{ "lr", 0x20AA0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr 0,s12 00100110101010100111ssssssSSSSSS.  */
+{ "lr", 0x26AA7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS.  */
+{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr 0,s12 0010011010101010R111ssssssSSSSSS.  */
+{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr b,limm 00100bbb001010100BBB111110RRRRRR.  */
+{ "lr", 0x202A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lr 0,limm 00100110001010100111111110RRRRRR.  */
+{ "lr", 0x262A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lr b,limm 00100bbb00101010RBBB111110RRRRRR.  */
+{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lr 0,limm 0010011000101010R111111110RRRRRR.  */
+{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010.  */
+{ "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010.  */
+{ "lsl16", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010.  */
+{ "lsl16", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010.  */
+{ "lsl16", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010.  */
+{ "lsl16", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* lsl16<.f> 0,limm 0010111000101111F111111110001010.  */
+{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111.  */
+{ "lsl8", 0x282F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111.  */
+{ "lsl8", 0x2E2F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111.  */
+{ "lsl8", 0x286F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111.  */
+{ "lsl8", 0x2E6F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111.  */
+{ "lsl8", 0x282F0F8F, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* lsl8<.f> 0,limm 0010111000101111F111111110001111.  */
+{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010.  */
+{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010.  */
+{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA.  */
+{ "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110.  */
+{ "lsr", 0x2801003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ.  */
+{ "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010.  */
+{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010.  */
+{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA.  */
+{ "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110.  */
+{ "lsr", 0x2841003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ.  */
+{ "lsr", 0x28C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS.  */
+{ "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010.  */
+{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* lsr<.f> 0,limm 0010011000101111F111111110000010.  */
+{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA.  */
+{ "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA.  */
+{ "lsr", 0x28010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110.  */
+{ "lsr", 0x2E01703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110.  */
+{ "lsr", 0x28010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ.  */
+{ "lsr", 0x28C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ.  */
+{ "lsr", 0x2EC17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA.  */
+{ "lsr", 0x2E417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110.  */
+{ "lsr", 0x2E41703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ.  */
+{ "lsr", 0x2EC17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS.  */
+{ "lsr", 0x2E817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA.  */
+{ "lsr", 0x2E017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110.  */
+{ "lsr", 0x2E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ.  */
+{ "lsr", 0x2EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011.  */
+{ "lsr16", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011.  */
+{ "lsr16", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011.  */
+{ "lsr16", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011.  */
+{ "lsr16", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011.  */
+{ "lsr16", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* lsr16<.f> 0,limm 0010111000101111F111111110001011.  */
+{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110.  */
+{ "lsr8", 0x282F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110.  */
+{ "lsr8", 0x2E2F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110.  */
+{ "lsr8", 0x286F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110.  */
+{ "lsr8", 0x2E6F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110.  */
+{ "lsr8", 0x282F0F8E, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* lsr8<.f> 0,limm 0010111000101111F111111110001110.  */
+{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* lsrdw<.f> a,b,c 00101bbb00100011FBBBCCCCCCAAAAAA.  */
+{ "lsrdw", 0x28230000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* lsrdw<.f> 0,b,c 00101bbb00100011FBBBCCCCCC111110.  */
+{ "lsrdw", 0x2823003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* lsrdw<.f><.cc> b,b,c 00101bbb11100011FBBBCCCCCC0QQQQQ.  */
+{ "lsrdw", 0x28E30000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* lsrdw<.f> a,b,u6 00101bbb01100011FBBBuuuuuuAAAAAA.  */
+{ "lsrdw", 0x28630000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* lsrdw<.f> 0,b,u6 00101bbb01100011FBBBuuuuuu111110.  */
+{ "lsrdw", 0x2863003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* lsrdw<.f><.cc> b,b,u6 00101bbb11100011FBBBuuuuuu1QQQQQ.  */
+{ "lsrdw", 0x28E30020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrdw<.f> b,b,s12 00101bbb10100011FBBBssssssSSSSSS.  */
+{ "lsrdw", 0x28A30000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* lsrdw<.f> a,limm,c 0010111000100011F111CCCCCCAAAAAA.  */
+{ "lsrdw", 0x2E237000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* lsrdw<.f> a,b,limm 00101bbb00100011FBBB111110AAAAAA.  */
+{ "lsrdw", 0x28230F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* lsrdw<.f> 0,limm,c 0010111000100011F111CCCCCC111110.  */
+{ "lsrdw", 0x2E23703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* lsrdw<.f> 0,b,limm 00101bbb00100011FBBB111110111110.  */
+{ "lsrdw", 0x28230FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* lsrdw<.f><.cc> 0,limm,c 0010111011100011F111CCCCCC0QQQQQ.  */
+{ "lsrdw", 0x2EE37000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* lsrdw<.f><.cc> b,b,limm 00101bbb11100011FBBB1111100QQQQQ.  */
+{ "lsrdw", 0x28E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* lsrdw<.f> a,limm,u6 0010111001100011F111uuuuuuAAAAAA.  */
+{ "lsrdw", 0x2E637000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsrdw<.f> 0,limm,u6 0010111001100011F111uuuuuu111110.  */
+{ "lsrdw", 0x2E63703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsrdw<.f><.cc> 0,limm,u6 0010111011100011F111uuuuuu1QQQQQ.  */
+{ "lsrdw", 0x2EE37020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrdw<.f> 0,limm,s12 0010111010100011F111ssssssSSSSSS.  */
+{ "lsrdw", 0x2EA37000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* lsrdw<.f> a,limm,limm 0010111000100011F111111110AAAAAA.  */
+{ "lsrdw", 0x2E237F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* lsrdw<.f> 0,limm,limm 0010111000100011F111111110111110.  */
+{ "lsrdw", 0x2E237FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* lsrdw<.f><.cc> 0,limm,limm 0010111011100011F1111111100QQQQQ.  */
+{ "lsrdw", 0x2EE37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* lsr_s b,c 01111bbbccc11101.  */
+{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* lsr_s b,b,c 01111bbbccc11001.  */
+{ "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* lsr_s b,b,u5 10111bbb001uuuuu.  */
+{ "lsr_s", 0x0000B820, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA.  */
+{ "mac", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }},
+
+/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110.  */
+{ "mac", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ.  */
+{ "mac", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA.  */
+{ "mac", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110.  */
+{ "mac", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ.  */
+{ "mac", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS.  */
+{ "mac", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA.  */
+{ "mac", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }},
+
+/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA.  */
+{ "mac", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }},
+
+/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110.  */
+{ "mac", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110.  */
+{ "mac", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ.  */
+{ "mac", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ.  */
+{ "mac", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA.  */
+{ "mac", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110.  */
+{ "mac", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ.  */
+{ "mac", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS.  */
+{ "mac", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA.  */
+{ "mac", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mac<.f> 0,limm,limm 0010111000001110F111111110111110.  */
+{ "mac", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ.  */
+{ "mac", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA.  */
+{ "macd", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }},
+
+/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110.  */
+{ "macd", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ.  */
+{ "macd", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA.  */
+{ "macd", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110.  */
+{ "macd", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ.  */
+{ "macd", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS.  */
+{ "macd", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA.  */
+{ "macd", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }},
+
+/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA.  */
+{ "macd", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }},
+
+/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110.  */
+{ "macd", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110.  */
+{ "macd", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ.  */
+{ "macd", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ.  */
+{ "macd", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA.  */
+{ "macd", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110.  */
+{ "macd", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ.  */
+{ "macd", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS.  */
+{ "macd", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA.  */
+{ "macd", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macd<.f> 0,limm,limm 0010111000011010F111111110111110.  */
+{ "macd", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ.  */
+{ "macd", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macdf<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA.  */
+{ "macdf", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* macdf<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110.  */
+{ "macdf", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macdf<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ.  */
+{ "macdf", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macdf<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA.  */
+{ "macdf", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macdf<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110.  */
+{ "macdf", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macdf<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ.  */
+{ "macdf", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdf<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS.  */
+{ "macdf", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macdf<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA.  */
+{ "macdf", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macdf<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA.  */
+{ "macdf", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macdf<.f> 0,limm,c 0011011000010011F111CCCCCC111110.  */
+{ "macdf", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macdf<.f> 0,b,limm 00110bbb00010011FBBB111110111110.  */
+{ "macdf", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macdf<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ.  */
+{ "macdf", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macdf<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ.  */
+{ "macdf", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macdf<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA.  */
+{ "macdf", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdf<.f> 0,limm,u6 0011011001010011F111uuuuuu111110.  */
+{ "macdf", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdf<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ.  */
+{ "macdf", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdf<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS.  */
+{ "macdf", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macdf<.f> a,limm,limm 0011011000010011F111111110AAAAAA.  */
+{ "macdf", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macdf<.f> 0,limm,limm 0011011000010011F111111110111110.  */
+{ "macdf", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macdf<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ.  */
+{ "macdf", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA.  */
+{ "macdu", 0x281B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }},
+
+/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110.  */
+{ "macdu", 0x281B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ.  */
+{ "macdu", 0x28DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA.  */
+{ "macdu", 0x285B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110.  */
+{ "macdu", 0x285B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ.  */
+{ "macdu", 0x28DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS.  */
+{ "macdu", 0x289B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA.  */
+{ "macdu", 0x2E1B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }},
+
+/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA.  */
+{ "macdu", 0x281B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }},
+
+/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110.  */
+{ "macdu", 0x2E1B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110.  */
+{ "macdu", 0x281B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ.  */
+{ "macdu", 0x28DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ.  */
+{ "macdu", 0x2EDB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA.  */
+{ "macdu", 0x2E5B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110.  */
+{ "macdu", 0x2E5B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ.  */
+{ "macdu", 0x2EDB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS.  */
+{ "macdu", 0x2E9B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA.  */
+{ "macdu", 0x2E1B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110.  */
+{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ.  */
+{ "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macdw<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA.  */
+{ "macdw", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macdw<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110.  */
+{ "macdw", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macdw<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ.  */
+{ "macdw", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macdw<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA.  */
+{ "macdw", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macdw<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110.  */
+{ "macdw", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macdw<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ.  */
+{ "macdw", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdw<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS.  */
+{ "macdw", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macdw<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA.  */
+{ "macdw", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macdw<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA.  */
+{ "macdw", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macdw<.f> 0,limm,c 0010111000010000F111CCCCCC111110.  */
+{ "macdw", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macdw<.f> 0,b,limm 00101bbb00010000FBBB111110111110.  */
+{ "macdw", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macdw<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ.  */
+{ "macdw", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macdw<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ.  */
+{ "macdw", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macdw<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA.  */
+{ "macdw", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdw<.f> 0,limm,u6 0010111001010000F111uuuuuu111110.  */
+{ "macdw", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdw<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ.  */
+{ "macdw", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdw<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS.  */
+{ "macdw", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macdw<.f> a,limm,limm 0010111000010000F111111110AAAAAA.  */
+{ "macdw", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macdw<.f> 0,limm,limm 0010111000010000F111111110111110.  */
+{ "macdw", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macdw<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ.  */
+{ "macdw", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macf<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA.  */
+{ "macf", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macf<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110.  */
+{ "macf", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macf<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ.  */
+{ "macf", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macf<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA.  */
+{ "macf", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macf<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110.  */
+{ "macf", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macf<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ.  */
+{ "macf", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macf<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS.  */
+{ "macf", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macf<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA.  */
+{ "macf", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macf<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA.  */
+{ "macf", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macf<.f> 0,limm,c 0011011000001100F111CCCCCC111110.  */
+{ "macf", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macf<.f> 0,b,limm 00110bbb00001100FBBB111110111110.  */
+{ "macf", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macf<.f><.cc> 0,limm,c 00110bbb11001100FBBB1111100QQQQQ.  */
+{ "macf", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macf<.f><.cc> b,b,limm 0011011011001100F111CCCCCC0QQQQQ.  */
+{ "macf", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macf<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA.  */
+{ "macf", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macf<.f> 0,limm,u6 0011011001001100F111uuuuuu111110.  */
+{ "macf", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macf<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ.  */
+{ "macf", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macf<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS.  */
+{ "macf", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macf<.f> a,limm,limm 0011011000001100F111111110AAAAAA.  */
+{ "macf", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macf<.f> 0,limm,limm 0011011000001100F111111110111110.  */
+{ "macf", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macf<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ.  */
+{ "macf", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macflw<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA.  */
+{ "macflw", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macflw<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110.  */
+{ "macflw", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macflw<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ.  */
+{ "macflw", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macflw<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA.  */
+{ "macflw", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macflw<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110.  */
+{ "macflw", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macflw<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ.  */
+{ "macflw", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macflw<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS.  */
+{ "macflw", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macflw<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA.  */
+{ "macflw", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macflw<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA.  */
+{ "macflw", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macflw<.f> 0,limm,c 0010111000110100F111CCCCCC111110.  */
+{ "macflw", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macflw<.f> 0,b,limm 00101bbb00110100FBBB111110111110.  */
+{ "macflw", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macflw<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ.  */
+{ "macflw", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macflw<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ.  */
+{ "macflw", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macflw<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA.  */
+{ "macflw", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macflw<.f> 0,limm,u6 0010111001110100F111uuuuuu111110.  */
+{ "macflw", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macflw<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ.  */
+{ "macflw", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macflw<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS.  */
+{ "macflw", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macflw<.f> a,limm,limm 0010111000110100F111111110AAAAAA.  */
+{ "macflw", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macflw<.f> 0,limm,limm 0010111000110100F111111110111110.  */
+{ "macflw", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macflw<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ.  */
+{ "macflw", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macfr<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA.  */
+{ "macfr", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macfr<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110.  */
+{ "macfr", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macfr<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ.  */
+{ "macfr", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macfr<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA.  */
+{ "macfr", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macfr<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110.  */
+{ "macfr", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macfr<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ.  */
+{ "macfr", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macfr<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS.  */
+{ "macfr", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macfr<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA.  */
+{ "macfr", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macfr<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA.  */
+{ "macfr", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macfr<.f> 0,limm,c 0011011000001101F111CCCCCC111110.  */
+{ "macfr", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macfr<.f> 0,b,limm 00110bbb00001101FBBB111110111110.  */
+{ "macfr", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macfr<.f><.cc> 0,limm,c 00110bbb11001101FBBB1111100QQQQQ.  */
+{ "macfr", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macfr<.f><.cc> b,b,limm 0011011011001101F111CCCCCC0QQQQQ.  */
+{ "macfr", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macfr<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA.  */
+{ "macfr", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macfr<.f> 0,limm,u6 0011011001001101F111uuuuuu111110.  */
+{ "macfr", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macfr<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ.  */
+{ "macfr", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macfr<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS.  */
+{ "macfr", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macfr<.f> a,limm,limm 0011011000001101F111111110AAAAAA.  */
+{ "macfr", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macfr<.f> 0,limm,limm 0011011000001101F111111110111110.  */
+{ "macfr", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macfr<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ.  */
+{ "macfr", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* machflw<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA.  */
+{ "machflw", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* machflw<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110.  */
+{ "machflw", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* machflw<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ.  */
+{ "machflw", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* machflw<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA.  */
+{ "machflw", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* machflw<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110.  */
+{ "machflw", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* machflw<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ.  */
+{ "machflw", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* machflw<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS.  */
+{ "machflw", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* machflw<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA.  */
+{ "machflw", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* machflw<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA.  */
+{ "machflw", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* machflw<.f> 0,limm,c 0010111000110111F111CCCCCC111110.  */
+{ "machflw", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* machflw<.f> 0,b,limm 00101bbb00110111FBBB111110111110.  */
+{ "machflw", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* machflw<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ.  */
+{ "machflw", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* machflw<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ.  */
+{ "machflw", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* machflw<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA.  */
+{ "machflw", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* machflw<.f> 0,limm,u6 0010111001110111F111uuuuuu111110.  */
+{ "machflw", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* machflw<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ.  */
+{ "machflw", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* machflw<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS.  */
+{ "machflw", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* machflw<.f> a,limm,limm 0010111000110111F111111110AAAAAA.  */
+{ "machflw", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* machflw<.f> 0,limm,limm 0010111000110111F111111110111110.  */
+{ "machflw", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* machflw<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ.  */
+{ "machflw", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* machlw<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA.  */
+{ "machlw", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* machlw<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110.  */
+{ "machlw", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* machlw<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ.  */
+{ "machlw", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* machlw<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA.  */
+{ "machlw", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* machlw<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110.  */
+{ "machlw", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* machlw<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ.  */
+{ "machlw", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* machlw<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS.  */
+{ "machlw", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* machlw<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA.  */
+{ "machlw", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* machlw<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA.  */
+{ "machlw", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* machlw<.f> 0,limm,c 0010111000110110F111CCCCCC111110.  */
+{ "machlw", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* machlw<.f> 0,b,limm 00101bbb00110110FBBB111110111110.  */
+{ "machlw", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* machlw<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ.  */
+{ "machlw", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* machlw<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ.  */
+{ "machlw", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* machlw<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA.  */
+{ "machlw", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* machlw<.f> 0,limm,u6 0010111001110110F111uuuuuu111110.  */
+{ "machlw", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* machlw<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ.  */
+{ "machlw", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* machlw<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS.  */
+{ "machlw", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* machlw<.f> a,limm,limm 0010111000110110F111111110AAAAAA.  */
+{ "machlw", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* machlw<.f> 0,limm,limm 0010111000110110F111111110111110.  */
+{ "machlw", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* machlw<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ.  */
+{ "machlw", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* machulw<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA.  */
+{ "machulw", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* machulw<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110.  */
+{ "machulw", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* machulw<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ.  */
+{ "machulw", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* machulw<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA.  */
+{ "machulw", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* machulw<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110.  */
+{ "machulw", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* machulw<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ.  */
+{ "machulw", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* machulw<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS.  */
+{ "machulw", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* machulw<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA.  */
+{ "machulw", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* machulw<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA.  */
+{ "machulw", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* machulw<.f> 0,limm,c 0010111000110101F111CCCCCC111110.  */
+{ "machulw", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* machulw<.f> 0,b,limm 00101bbb00110101FBBB111110111110.  */
+{ "machulw", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* machulw<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ.  */
+{ "machulw", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* machulw<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ.  */
+{ "machulw", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* machulw<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA.  */
+{ "machulw", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* machulw<.f> 0,limm,u6 0010111001110101F111uuuuuu111110.  */
+{ "machulw", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* machulw<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ.  */
+{ "machulw", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* machulw<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS.  */
+{ "machulw", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* machulw<.f> a,limm,limm 0010111000110101F111111110AAAAAA.  */
+{ "machulw", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* machulw<.f> 0,limm,limm 0010111000110101F111111110111110.  */
+{ "machulw", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* machulw<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ.  */
+{ "machulw", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* maclw<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA.  */
+{ "maclw", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* maclw<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110.  */
+{ "maclw", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* maclw<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ.  */
+{ "maclw", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* maclw<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA.  */
+{ "maclw", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* maclw<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110.  */
+{ "maclw", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* maclw<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ.  */
+{ "maclw", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* maclw<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS.  */
+{ "maclw", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* maclw<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA.  */
+{ "maclw", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* maclw<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA.  */
+{ "maclw", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* maclw<.f> 0,limm,c 0010111000110011F111CCCCCC111110.  */
+{ "maclw", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* maclw<.f> 0,b,limm 00101bbb00110011FBBB111110111110.  */
+{ "maclw", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* maclw<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ.  */
+{ "maclw", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* maclw<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ.  */
+{ "maclw", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* maclw<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA.  */
+{ "maclw", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maclw<.f> 0,limm,u6 0010111001110011F111uuuuuu111110.  */
+{ "maclw", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maclw<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ.  */
+{ "maclw", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maclw<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS.  */
+{ "maclw", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* maclw<.f> a,limm,limm 0010111000110011F111111110AAAAAA.  */
+{ "maclw", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* maclw<.f> 0,limm,limm 0010111000110011F111111110111110.  */
+{ "maclw", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* maclw<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ.  */
+{ "maclw", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macrdw<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA.  */
+{ "macrdw", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macrdw<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110.  */
+{ "macrdw", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macrdw<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ.  */
+{ "macrdw", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macrdw<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA.  */
+{ "macrdw", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macrdw<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110.  */
+{ "macrdw", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macrdw<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ.  */
+{ "macrdw", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macrdw<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS.  */
+{ "macrdw", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macrdw<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA.  */
+{ "macrdw", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macrdw<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA.  */
+{ "macrdw", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macrdw<.f> 0,limm,c 0010111000010010F111CCCCCC111110.  */
+{ "macrdw", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macrdw<.f> 0,b,limm 00101bbb00010010FBBB111110111110.  */
+{ "macrdw", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macrdw<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ.  */
+{ "macrdw", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macrdw<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ.  */
+{ "macrdw", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macrdw<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA.  */
+{ "macrdw", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macrdw<.f> 0,limm,u6 0010111001010010F111uuuuuu111110.  */
+{ "macrdw", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macrdw<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ.  */
+{ "macrdw", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macrdw<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS.  */
+{ "macrdw", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macrdw<.f> a,limm,limm 0010111000010010F111111110AAAAAA.  */
+{ "macrdw", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macrdw<.f> 0,limm,limm 0010111000010010F111111110111110.  */
+{ "macrdw", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macrdw<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ.  */
+{ "macrdw", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macrt<.f> a,b,c 00101bbb00011110FBBBCCCCCCAAAAAA.  */
+{ "macrt", 0x281E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macrt<.f> 0,b,c 00101bbb00011110FBBBCCCCCC111110.  */
+{ "macrt", 0x281E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macrt<.f><.cc> b,b,c 00101bbb11011110FBBBCCCCCC0QQQQQ.  */
+{ "macrt", 0x28DE0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macrt<.f> a,b,u6 00101bbb01011110FBBBuuuuuuAAAAAA.  */
+{ "macrt", 0x285E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macrt<.f> 0,b,u6 00101bbb01011110FBBBuuuuuu111110.  */
+{ "macrt", 0x285E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macrt<.f><.cc> b,b,u6 00101bbb11011110FBBBuuuuuu1QQQQQ.  */
+{ "macrt", 0x28DE0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macrt<.f> b,b,s12 00101bbb10011110FBBBssssssSSSSSS.  */
+{ "macrt", 0x289E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macrt<.f> a,limm,c 0010111000011110F111CCCCCCAAAAAA.  */
+{ "macrt", 0x2E1E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macrt<.f> a,b,limm 00101bbb00011110FBBB111110AAAAAA.  */
+{ "macrt", 0x281E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macrt<.f> 0,limm,c 0010111000011110F111CCCCCC111110.  */
+{ "macrt", 0x2E1E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macrt<.f> 0,b,limm 00101bbb00011110FBBB111110111110.  */
+{ "macrt", 0x281E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macrt<.f><.cc> 0,limm,c 0010111011011110F111CCCCCC0QQQQQ.  */
+{ "macrt", 0x2EDE7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macrt<.f><.cc> b,b,limm 00101bbb11011110FBBB1111100QQQQQ.  */
+{ "macrt", 0x28DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macrt<.f> a,limm,u6 0010111001011110F111uuuuuuAAAAAA.  */
+{ "macrt", 0x2E5E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macrt<.f> 0,limm,u6 0010111001011110F111uuuuuu111110.  */
+{ "macrt", 0x2E5E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macrt<.f><.cc> 0,limm,u6 0010111011011110F111uuuuuu1QQQQQ.  */
+{ "macrt", 0x2EDE7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macrt<.f> 0,limm,s12 0010111010011110F111ssssssSSSSSS.  */
+{ "macrt", 0x2E9E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macrt<.f> a,limm,limm 0010111000011110F111111110AAAAAA.  */
+{ "macrt", 0x2E1E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macrt<.f> 0,limm,limm 0010111000011110F111111110111110.  */
+{ "macrt", 0x2E1E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macrt<.f><.cc> 0,limm,limm 0010111011011110F1111111100QQQQQ.  */
+{ "macrt", 0x2EDE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mact<.f> a,b,c 00101bbb00011100FBBBCCCCCCAAAAAA.  */
+{ "mact", 0x281C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mact<.f> 0,b,c 00101bbb00011100FBBBCCCCCC111110.  */
+{ "mact", 0x281C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mact<.f><.cc> b,b,c 00101bbb11011100FBBBCCCCCC0QQQQQ.  */
+{ "mact", 0x28DC0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mact<.f> a,b,u6 00101bbb01011100FBBBuuuuuuAAAAAA.  */
+{ "mact", 0x285C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mact<.f> 0,b,u6 00101bbb01011100FBBBuuuuuu111110.  */
+{ "mact", 0x285C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mact<.f><.cc> b,b,u6 00101bbb11011100FBBBuuuuuu1QQQQQ.  */
+{ "mact", 0x28DC0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mact<.f> b,b,s12 00101bbb10011100FBBBssssssSSSSSS.  */
+{ "mact", 0x289C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mact<.f> a,limm,c 0010111000011100F111CCCCCCAAAAAA.  */
+{ "mact", 0x2E1C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mact<.f> a,b,limm 00101bbb00011100FBBB111110AAAAAA.  */
+{ "mact", 0x281C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mact<.f> 0,limm,c 0010111000011100F111CCCCCC111110.  */
+{ "mact", 0x2E1C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mact<.f> 0,b,limm 00101bbb00011100FBBB111110111110.  */
+{ "mact", 0x281C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mact<.f><.cc> 0,limm,c 0010111011011100F111CCCCCC0QQQQQ.  */
+{ "mact", 0x2EDC7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mact<.f><.cc> b,b,limm 00101bbb11011100FBBB1111100QQQQQ.  */
+{ "mact", 0x28DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mact<.f> a,limm,u6 0010111001011100F111uuuuuuAAAAAA.  */
+{ "mact", 0x2E5C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mact<.f> 0,limm,u6 0010111001011100F111uuuuuu111110.  */
+{ "mact", 0x2E5C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mact<.f><.cc> 0,limm,u6 0010111011011100F111uuuuuu1QQQQQ.  */
+{ "mact", 0x2EDC7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mact<.f> 0,limm,s12 0010111010011100F111ssssssSSSSSS.  */
+{ "mact", 0x2E9C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mact<.f> a,limm,limm 0010111000011100F111111110AAAAAA.  */
+{ "mact", 0x2E1C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mact<.f> 0,limm,limm 0010111000011100F111111110111110.  */
+{ "mact", 0x2E1C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mact<.f><.cc> 0,limm,limm 0010111011011100F1111111100QQQQQ.  */
+{ "mact", 0x2EDC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA.  */
+{ "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }},
+
+/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110.  */
+{ "macu", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ.  */
+{ "macu", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA.  */
+{ "macu", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110.  */
+{ "macu", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ.  */
+{ "macu", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS.  */
+{ "macu", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA.  */
+{ "macu", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }},
+
+/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA.  */
+{ "macu", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }},
+
+/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110.  */
+{ "macu", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110.  */
+{ "macu", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ.  */
+{ "macu", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ.  */
+{ "macu", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA.  */
+{ "macu", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110.  */
+{ "macu", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ.  */
+{ "macu", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS.  */
+{ "macu", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA.  */
+{ "macu", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macu<.f> 0,limm,limm 0010111000001111F111111110111110.  */
+{ "macu", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ.  */
+{ "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macudw<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA.  */
+{ "macudw", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macudw<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110.  */
+{ "macudw", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macudw<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ.  */
+{ "macudw", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macudw<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA.  */
+{ "macudw", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macudw<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110.  */
+{ "macudw", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macudw<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ.  */
+{ "macudw", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macudw<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS.  */
+{ "macudw", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macudw<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA.  */
+{ "macudw", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macudw<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA.  */
+{ "macudw", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macudw<.f> 0,limm,c 0010111000010001F111CCCCCC111110.  */
+{ "macudw", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macudw<.f> 0,b,limm 00101bbb00010001FBBB111110111110.  */
+{ "macudw", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macudw<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ.  */
+{ "macudw", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macudw<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ.  */
+{ "macudw", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macudw<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA.  */
+{ "macudw", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macudw<.f> 0,limm,u6 0010111001010001F111uuuuuu111110.  */
+{ "macudw", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macudw<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ.  */
+{ "macudw", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macudw<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS.  */
+{ "macudw", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macudw<.f> a,limm,limm 0010111000010001F111111110AAAAAA.  */
+{ "macudw", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macudw<.f> 0,limm,limm 0010111000010001F111111110111110.  */
+{ "macudw", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macudw<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ.  */
+{ "macudw", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhfm<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA.  */
+{ "macwhfm", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macwhfm<.f> 0,b,c 00110bbb00100010FBBBCCCCCC111110.  */
+{ "macwhfm", 0x3022003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhfm<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ.  */
+{ "macwhfm", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhfm<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA.  */
+{ "macwhfm", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f> 0,b,u6 00110bbb01100010FBBBuuuuuu111110.  */
+{ "macwhfm", 0x3062003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ.  */
+{ "macwhfm", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfm<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS.  */
+{ "macwhfm", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhfm<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA.  */
+{ "macwhfm", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macwhfm<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA.  */
+{ "macwhfm", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macwhfm<.f> 0,limm,c 0011011001100010F111CCCCCC111110.  */
+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhfm<.f> 0,b,limm 00110bbb00100010FBBB111110111110.  */
+{ "macwhfm", 0x30220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhfm<.f><.cc> 0,limm,c 00110bbb11100010FBBB1111100QQQQQ.  */
+{ "macwhfm", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhfm<.f><.cc> b,b,limm 0011011011100010F111CCCCCC0QQQQQ.  */
+{ "macwhfm", 0x36E27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhfm<.f> a,limm,u6 0011011001100010F111uuuuuuAAAAAA.  */
+{ "macwhfm", 0x36627000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f> 0,limm,u6 0011011001100010F111uuuuuu111110.  */
+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f><.cc> 0,limm,u6 0011011011100010F111uuuuuu1QQQQQ.  */
+{ "macwhfm", 0x36E27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfm<.f> 0,limm,s12 0011011010100010F111ssssssSSSSSS.  */
+{ "macwhfm", 0x36A27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhfm<.f> a,limm,limm 0011011000100010F111111110AAAAAA.  */
+{ "macwhfm", 0x36227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfm<.f> 0,limm,limm 0011011000100010F111111110111110.  */
+{ "macwhfm", 0x36227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfm<.f><.cc> 0,limm,limm 0011011011100010F1111111100QQQQQ.  */
+{ "macwhfm", 0x36E27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhfmr<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA.  */
+{ "macwhfmr", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macwhfmr<.f> 0,b,c 00110bbb00100011FBBBCCCCCC111110.  */
+{ "macwhfmr", 0x3023003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhfmr<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ.  */
+{ "macwhfmr", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhfmr<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA.  */
+{ "macwhfmr", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f> 0,b,u6 00110bbb01100011FBBBuuuuuu111110.  */
+{ "macwhfmr", 0x3063003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ.  */
+{ "macwhfmr", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfmr<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS.  */
+{ "macwhfmr", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhfmr<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA.  */
+{ "macwhfmr", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macwhfmr<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA.  */
+{ "macwhfmr", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macwhfmr<.f> 0,limm,c 0011011001100011F111CCCCCC111110.  */
+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhfmr<.f> 0,b,limm 00110bbb00100011FBBB111110111110.  */
+{ "macwhfmr", 0x30230FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhfmr<.f><.cc> 0,limm,c 00110bbb11100011FBBB1111100QQQQQ.  */
+{ "macwhfmr", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhfmr<.f><.cc> b,b,limm 0011011011100011F111CCCCCC0QQQQQ.  */
+{ "macwhfmr", 0x36E37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhfmr<.f> a,limm,u6 0011011001100011F111uuuuuuAAAAAA.  */
+{ "macwhfmr", 0x36637000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f> 0,limm,u6 0011011001100011F111uuuuuu111110.  */
+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f><.cc> 0,limm,u6 0011011011100011F111uuuuuu1QQQQQ.  */
+{ "macwhfmr", 0x36E37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfmr<.f> 0,limm,s12 0011011010100011F111ssssssSSSSSS.  */
+{ "macwhfmr", 0x36A37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhfmr<.f> a,limm,limm 0011011000100011F111111110AAAAAA.  */
+{ "macwhfmr", 0x36237F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfmr<.f> 0,limm,limm 0011011000100011F111111110111110.  */
+{ "macwhfmr", 0x36237FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfmr<.f><.cc> 0,limm,limm 0011011011100011F1111111100QQQQQ.  */
+{ "macwhfmr", 0x36E37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhl<.f> a,b,c 00110bbb00011101FBBBCCCCCCAAAAAA.  */
+{ "macwhl", 0x301D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macwhl<.f> 0,b,c 00110bbb00011101FBBBCCCCCC111110.  */
+{ "macwhl", 0x301D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhl<.f><.cc> b,b,c 00110bbb11011101FBBBCCCCCC0QQQQQ.  */
+{ "macwhl", 0x30DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhl<.f> a,b,u6 00110bbb01011101FBBBuuuuuuAAAAAA.  */
+{ "macwhl", 0x305D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f> 0,b,u6 00110bbb01011101FBBBuuuuuu111110.  */
+{ "macwhl", 0x305D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f><.cc> b,b,u6 00110bbb11011101FBBBuuuuuu1QQQQQ.  */
+{ "macwhl", 0x30DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhl<.f> b,b,s12 00110bbb10011101FBBBssssssSSSSSS.  */
+{ "macwhl", 0x309D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhl<.f> a,limm,c 0011011000011101F111CCCCCCAAAAAA.  */
+{ "macwhl", 0x361D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macwhl<.f> a,b,limm 00110bbb00011101FBBB111110AAAAAA.  */
+{ "macwhl", 0x301D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macwhl<.f> 0,limm,c 0011011000011101F111CCCCCC111110.  */
+{ "macwhl", 0x361D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhl<.f> 0,b,limm 00110bbb00011101FBBB111110111110.  */
+{ "macwhl", 0x301D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhl<.f><.cc> 0,limm,c 00110bbb11011101FBBB1111100QQQQQ.  */
+{ "macwhl", 0x30DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhl<.f><.cc> b,b,limm 0011011011011101F111CCCCCC0QQQQQ.  */
+{ "macwhl", 0x36DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhl<.f> a,limm,u6 0011011001011101F111uuuuuuAAAAAA.  */
+{ "macwhl", 0x365D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f> 0,limm,u6 0011011001011101F111uuuuuu111110.  */
+{ "macwhl", 0x365D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f><.cc> 0,limm,u6 0011011011011101F111uuuuuu1QQQQQ.  */
+{ "macwhl", 0x36DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhl<.f> 0,limm,s12 0011011010011101F111ssssssSSSSSS.  */
+{ "macwhl", 0x369D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhl<.f> a,limm,limm 0011011000011101F111111110AAAAAA.  */
+{ "macwhl", 0x361D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhl<.f> 0,limm,limm 0011011000011101F111111110111110.  */
+{ "macwhl", 0x361D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhl<.f><.cc> 0,limm,limm 0011011011011101F1111111100QQQQQ.  */
+{ "macwhl", 0x36DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhul<.f> a,b,c 00110bbb00011111FBBBCCCCCCAAAAAA.  */
+{ "macwhul", 0x301F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* macwhul<.f> 0,b,c 00110bbb00011111FBBBCCCCCC111110.  */
+{ "macwhul", 0x301F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhul<.f><.cc> b,b,c 00110bbb11011111FBBBCCCCCC0QQQQQ.  */
+{ "macwhul", 0x30DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhul<.f> a,b,u6 00110bbb01011111FBBBuuuuuuAAAAAA.  */
+{ "macwhul", 0x305F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f> 0,b,u6 00110bbb01011111FBBBuuuuuu111110.  */
+{ "macwhul", 0x305F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f><.cc> b,b,u6 00110bbb11011111FBBBuuuuuu1QQQQQ.  */
+{ "macwhul", 0x30DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhul<.f> b,b,s12 00110bbb10011111FBBBssssssSSSSSS.  */
+{ "macwhul", 0x309F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhul<.f> a,limm,c 0011011000011111F111CCCCCCAAAAAA.  */
+{ "macwhul", 0x361F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* macwhul<.f> a,b,limm 00110bbb00011111FBBB111110AAAAAA.  */
+{ "macwhul", 0x301F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* macwhul<.f> 0,limm,c 0011011000011111F111CCCCCC111110.  */
+{ "macwhul", 0x361F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhul<.f> 0,b,limm 00110bbb00011111FBBB111110111110.  */
+{ "macwhul", 0x301F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhul<.f><.cc> 0,limm,c 00110bbb11011111FBBB1111100QQQQQ.  */
+{ "macwhul", 0x30DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhul<.f><.cc> b,b,limm 0011011011011111F111CCCCCC0QQQQQ.  */
+{ "macwhul", 0x36DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhul<.f> a,limm,u6 0011011001011111F111uuuuuuAAAAAA.  */
+{ "macwhul", 0x365F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f> 0,limm,u6 0011011001011111F111uuuuuu111110.  */
+{ "macwhul", 0x365F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f><.cc> 0,limm,u6 0011011011011111F111uuuuuu1QQQQQ.  */
+{ "macwhul", 0x36DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhul<.f> 0,limm,s12 0011011010011111F111ssssssSSSSSS.  */
+{ "macwhul", 0x369F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhul<.f> a,limm,limm 0011011000011111F111111110AAAAAA.  */
+{ "macwhul", 0x361F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhul<.f> 0,limm,limm 0011011000011111F111111110111110.  */
+{ "macwhul", 0x361F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhul<.f><.cc> 0,limm,limm 0011011011011111F1111111100QQQQQ.  */
+{ "macwhul", 0x36DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA.  */
+{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110.  */
+{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ.  */
+{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA.  */
+{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110.  */
+{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ.  */
+{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS.  */
+{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA.  */
+{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA.  */
+{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110.  */
+{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110.  */
+{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ.  */
+{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ.  */
+{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA.  */
+{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110.  */
+{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ.  */
+{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS.  */
+{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA.  */
+{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* max<.f> 0,limm,limm 0010011000001000F111111110111110.  */
+{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ.  */
+{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* maxabssdw<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA.  */
+{ "maxabssdw", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* maxabssdw<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110.  */
+{ "maxabssdw", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* maxabssdw<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ.  */
+{ "maxabssdw", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* maxabssdw<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA.  */
+{ "maxabssdw", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* maxabssdw<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110.  */
+{ "maxabssdw", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* maxabssdw<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ.  */
+{ "maxabssdw", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxabssdw<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS.  */
+{ "maxabssdw", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* maxabssdw<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA.  */
+{ "maxabssdw", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* maxabssdw<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA.  */
+{ "maxabssdw", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* maxabssdw<.f> 0,limm,c 0010111000101011F111CCCCCC111110.  */
+{ "maxabssdw", 0x2E2B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* maxabssdw<.f> 0,b,limm 00101bbb00101011FBBB111110111110.  */
+{ "maxabssdw", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* maxabssdw<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ.  */
+{ "maxabssdw", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* maxabssdw<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ.  */
+{ "maxabssdw", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* maxabssdw<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA.  */
+{ "maxabssdw", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxabssdw<.f> 0,limm,u6 0010111001101011F111uuuuuu111110.  */
+{ "maxabssdw", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxabssdw<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ.  */
+{ "maxabssdw", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxabssdw<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS.  */
+{ "maxabssdw", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* maxabssdw<.f> a,limm,limm 0010111000101011F111111110AAAAAA.  */
+{ "maxabssdw", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* maxabssdw<.f> 0,limm,limm 0010111000101011F111111110111110.  */
+{ "maxabssdw", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* maxabssdw<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ.  */
+{ "maxabssdw", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* maxidl<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA.  */
+{ "maxidl", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* maxidl<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110.  */
+{ "maxidl", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* maxidl<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ.  */
+{ "maxidl", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* maxidl<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA.  */
+{ "maxidl", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* maxidl<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110.  */
+{ "maxidl", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* maxidl<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ.  */
+{ "maxidl", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxidl<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS.  */
+{ "maxidl", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* maxidl<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA.  */
+{ "maxidl", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* maxidl<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA.  */
+{ "maxidl", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* maxidl<.f> 0,limm,c 0010111000001111F111CCCCCC111110.  */
+{ "maxidl", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* maxidl<.f> 0,b,limm 00101bbb00001111FBBB111110111110.  */
+{ "maxidl", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* maxidl<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ.  */
+{ "maxidl", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* maxidl<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ.  */
+{ "maxidl", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* maxidl<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA.  */
+{ "maxidl", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxidl<.f> 0,limm,u6 0010111001001111F111uuuuuu111110.  */
+{ "maxidl", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxidl<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ.  */
+{ "maxidl", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxidl<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS.  */
+{ "maxidl", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* maxidl<.f> a,limm,limm 0010111000001111F111111110AAAAAA.  */
+{ "maxidl", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* maxidl<.f> 0,limm,limm 0010111000001111F111111110111110.  */
+{ "maxidl", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* maxidl<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ.  */
+{ "maxidl", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA.  */
+{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110.  */
+{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ.  */
+{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA.  */
+{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110.  */
+{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ.  */
+{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS.  */
+{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA.  */
+{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA.  */
+{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110.  */
+{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110.  */
+{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ.  */
+{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ.  */
+{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA.  */
+{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110.  */
+{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ.  */
+{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS.  */
+{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA.  */
+{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* min<.f> 0,limm,limm 0010011000001001F111111110111110.  */
+{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ.  */
+{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* minidl<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA.  */
+{ "minidl", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* minidl<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110.  */
+{ "minidl", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* minidl<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ.  */
+{ "minidl", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* minidl<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA.  */
+{ "minidl", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* minidl<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110.  */
+{ "minidl", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* minidl<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ.  */
+{ "minidl", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* minidl<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS.  */
+{ "minidl", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* minidl<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA.  */
+{ "minidl", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* minidl<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA.  */
+{ "minidl", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* minidl<.f> 0,limm,c 0010111000001001F111CCCCCC111110.  */
+{ "minidl", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* minidl<.f> 0,b,limm 00101bbb00001001FBBB111110111110.  */
+{ "minidl", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* minidl<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ.  */
+{ "minidl", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* minidl<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ.  */
+{ "minidl", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* minidl<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA.  */
+{ "minidl", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* minidl<.f> 0,limm,u6 0010111001001001F111uuuuuu111110.  */
+{ "minidl", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* minidl<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ.  */
+{ "minidl", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* minidl<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS.  */
+{ "minidl", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* minidl<.f> a,limm,limm 0010111000001001F111111110AAAAAA.  */
+{ "minidl", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* minidl<.f> 0,limm,limm 0010111000001001F111111110111110.  */
+{ "minidl", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ.  */
+{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR.  */
+{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_F }},
+
+/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR.  */
+{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, RC }, { C_F }},
+
+/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ.  */
+{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ.  */
+{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, RC }, { C_F, C_CC }},
+
+/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR.  */
+{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR.  */
+{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.  */
+{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ.  */
+{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_20 }, { C_F, C_CC }},
+
+/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS.  */
+{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, SIMM12_20 }, { C_F }},
+
+/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS.  */
+{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, SIMM12_20 }, { C_F }},
+
+/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR.  */
+{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_F }},
+
+/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR.  */
+{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, LIMM }, { C_F }},
+
+/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ.  */
+{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ.  */
+{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, LIMM }, { C_F, C_CC }},
+
+/* mov_s b,h 01110bbbhhh01HHH.  */
+{ "mov_s", 0x00007008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RB_S, R6H }, { 0 }},
+
+/* mov_s b,h 01110bbbhhh010HH.  */
+{ "mov_s", 0x00007008, 0x0000F81C, 0, MEMORY, NONE, { RB_S, RH_S }, { 0 }},
+
+/* mov_s h,b 01110bbbhhh11HHH.  */
+{ "mov_s", 0x00007018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { R6H, RB_S }, { 0 }},
+
+/* mov_s h,b 01110bbbhhh110HH.  */
+{ "mov_s", 0x00007018, 0x0000F81C, 0, MEMORY, NONE, { RH_S, RB_S }, { 0 }},
+
+/* mov_s 0,b 01110bbb1101111H.  */
+{ "mov_s", 0x000070DE, 0x0000F8FE, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { ZA_S, RB_S }, { 0 }},
+
+/* mov_s 0,b 01110bbb11011011.  */
+{ "mov_s", 0x000070DB, 0x0000F8FF, 0, MEMORY, NONE, { ZA_S, RB_S }, { 0 }},
+
+/* mov_s g,h 01000ggghhhGG0HH.  */
+{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { G_S, RH_S }, { 0 }},
+
+/* mov_s 0,h 01000110hhh110HH.  */
+{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA_S, RH_S }, { 0 }},
+
+/* mov_s h,s3 01110ssshhh011HH.  */
+{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RH_S, SIMM3_5_S }, { 0 }},
+
+/* mov_s 0,s3 01110sss11001111.  */
+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA_S, SIMM3_5_S }, { 0 }},
+
+/* mov_s b,u8 11011bbbuuuuuuuu.  */
+{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, UIMM8_8_S }, { 0 }},
+
+/* mov_s b,limm 01110bbb11001111.  */
+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RB_S, LIMM_S }, { 0 }},
+
+/* mov_s b,limm 01110bbb11001011.  */
+{ "mov_s", 0x000070CB, 0x0000F8FF, 0, MEMORY, NONE, { RB_S, LIMM_S }, { 0 }},
+
+/* mov_s g,limm 01000ggg110GG011.  */
+{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { G_S, LIMM_S }, { 0 }},
+
+/* mov_s 0,limm 0100011011011011.  */
+{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA_S, LIMM_S }, { 0 }},
+
+/* mov_s.ne b,h 01110bbbhhh111HH.  */
+{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, RH_S }, { C_NE }},
+
+/* mov_s.ne b,limm 01110bbb11011111.  */
+{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, LIMM_S }, { C_NE }},
+
+/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA.  */
+{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }},
+
+/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110.  */
+{ "mpy", 0x201A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ.  */
+{ "mpy", 0x20DA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.  */
+{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110.  */
+{ "mpy", 0x205A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ.  */
+{ "mpy", 0x20DA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS.  */
+{ "mpy", 0x209A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA.  */
+{ "mpy", 0x261A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }},
+
+/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA.  */
+{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110.  */
+{ "mpy", 0x261A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110.  */
+{ "mpy", 0x201A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ.  */
+{ "mpy", 0x20DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ.  */
+{ "mpy", 0x26DA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA.  */
+{ "mpy", 0x265A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110.  */
+{ "mpy", 0x265A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ.  */
+{ "mpy", 0x26DA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS.  */
+{ "mpy", 0x269A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA.  */
+{ "mpy", 0x261A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110.  */
+{ "mpy", 0x261A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ.  */
+{ "mpy", 0x26DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA.  */
+{ "mpyd", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }},
+
+/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110.  */
+{ "mpyd", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ.  */
+{ "mpyd", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA.  */
+{ "mpyd", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110.  */
+{ "mpyd", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ.  */
+{ "mpyd", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS.  */
+{ "mpyd", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA.  */
+{ "mpyd", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }},
+
+/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA.  */
+{ "mpyd", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }},
+
+/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110.  */
+{ "mpyd", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110.  */
+{ "mpyd", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ.  */
+{ "mpyd", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ.  */
+{ "mpyd", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA.  */
+{ "mpyd", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110.  */
+{ "mpyd", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ.  */
+{ "mpyd", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS.  */
+{ "mpyd", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA.  */
+{ "mpyd", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110.  */
+{ "mpyd", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ.  */
+{ "mpyd", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA.  */
+{ "mpydf", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110.  */
+{ "mpydf", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ.  */
+{ "mpydf", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA.  */
+{ "mpydf", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110.  */
+{ "mpydf", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ.  */
+{ "mpydf", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS.  */
+{ "mpydf", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA.  */
+{ "mpydf", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA.  */
+{ "mpydf", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110.  */
+{ "mpydf", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110.  */
+{ "mpydf", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ.  */
+{ "mpydf", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ.  */
+{ "mpydf", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA.  */
+{ "mpydf", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110.  */
+{ "mpydf", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ.  */
+{ "mpydf", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS.  */
+{ "mpydf", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA.  */
+{ "mpydf", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110.  */
+{ "mpydf", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ.  */
+{ "mpydf", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA.  */
+{ "mpydu", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }},
+
+/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110.  */
+{ "mpydu", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ.  */
+{ "mpydu", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA.  */
+{ "mpydu", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110.  */
+{ "mpydu", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ.  */
+{ "mpydu", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS.  */
+{ "mpydu", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA.  */
+{ "mpydu", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }},
+
+/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA.  */
+{ "mpydu", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }},
+
+/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110.  */
+{ "mpydu", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110.  */
+{ "mpydu", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ.  */
+{ "mpydu", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ.  */
+{ "mpydu", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA.  */
+{ "mpydu", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110.  */
+{ "mpydu", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ.  */
+{ "mpydu", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS.  */
+{ "mpydu", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA.  */
+{ "mpydu", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110.  */
+{ "mpydu", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ.  */
+{ "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyf<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA.  */
+{ "mpyf", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyf<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110.  */
+{ "mpyf", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyf<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ.  */
+{ "mpyf", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyf<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA.  */
+{ "mpyf", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110.  */
+{ "mpyf", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ.  */
+{ "mpyf", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyf<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS.  */
+{ "mpyf", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyf<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA.  */
+{ "mpyf", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyf<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA.  */
+{ "mpyf", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyf<.f> 0,limm,c 0011011000001010F111CCCCCC111110.  */
+{ "mpyf", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyf<.f> 0,b,limm 00110bbb00001010FBBB111110111110.  */
+{ "mpyf", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyf<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ.  */
+{ "mpyf", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyf<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ.  */
+{ "mpyf", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyf<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA.  */
+{ "mpyf", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f> 0,limm,u6 0011011001001010F111uuuuuu111110.  */
+{ "mpyf", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ.  */
+{ "mpyf", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyf<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS.  */
+{ "mpyf", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyf<.f> a,limm,limm 0011011000001010F111111110AAAAAA.  */
+{ "mpyf", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyf<.f> 0,limm,limm 0011011000001010F111111110111110.  */
+{ "mpyf", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyf<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ.  */
+{ "mpyf", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyfr<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA.  */
+{ "mpyfr", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyfr<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110.  */
+{ "mpyfr", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyfr<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ.  */
+{ "mpyfr", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyfr<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA.  */
+{ "mpyfr", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110.  */
+{ "mpyfr", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ.  */
+{ "mpyfr", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyfr<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS.  */
+{ "mpyfr", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyfr<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA.  */
+{ "mpyfr", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyfr<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA.  */
+{ "mpyfr", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyfr<.f> 0,limm,c 0011011000001011F111CCCCCC111110.  */
+{ "mpyfr", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyfr<.f> 0,b,limm 00110bbb00001011FBBB111110111110.  */
+{ "mpyfr", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyfr<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ.  */
+{ "mpyfr", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyfr<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ.  */
+{ "mpyfr", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyfr<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA.  */
+{ "mpyfr", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f> 0,limm,u6 0011011001001011F111uuuuuu111110.  */
+{ "mpyfr", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ.  */
+{ "mpyfr", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyfr<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS.  */
+{ "mpyfr", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyfr<.f> a,limm,limm 0011011000001011F111111110AAAAAA.  */
+{ "mpyfr", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyfr<.f> 0,limm,limm 0011011000001011F111111110111110.  */
+{ "mpyfr", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyfr<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ.  */
+{ "mpyfr", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyh<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA.  */
+{ "mpyh", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyh<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110.  */
+{ "mpyh", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyh<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ.  */
+{ "mpyh", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyh<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA.  */
+{ "mpyh", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyh<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110.  */
+{ "mpyh", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyh<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ.  */
+{ "mpyh", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyh<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS.  */
+{ "mpyh", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyh<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA.  */
+{ "mpyh", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyh<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA.  */
+{ "mpyh", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyh<.f> 0,limm,c 0010011000011011F111CCCCCC111110.  */
+{ "mpyh", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyh<.f> 0,b,limm 00100bbb00011011FBBB111110111110.  */
+{ "mpyh", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyh<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ.  */
+{ "mpyh", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyh<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ.  */
+{ "mpyh", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyh<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA.  */
+{ "mpyh", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyh<.f> 0,limm,u6 0010011001011011F111uuuuuu111110.  */
+{ "mpyh", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyh<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ.  */
+{ "mpyh", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyh<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS.  */
+{ "mpyh", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyh<.f> a,limm,limm 0010011000011011F111111110AAAAAA.  */
+{ "mpyh", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyh<.f> 0,limm,limm 0010011000011011F111111110111110.  */
+{ "mpyh", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyh<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ.  */
+{ "mpyh", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyhu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA.  */
+{ "mpyhu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyhu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110.  */
+{ "mpyhu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyhu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ.  */
+{ "mpyhu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyhu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA.  */
+{ "mpyhu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyhu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110.  */
+{ "mpyhu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyhu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ.  */
+{ "mpyhu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyhu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS.  */
+{ "mpyhu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyhu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA.  */
+{ "mpyhu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyhu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA.  */
+{ "mpyhu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyhu<.f> 0,limm,c 0010011000011100F111CCCCCC111110.  */
+{ "mpyhu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyhu<.f> 0,b,limm 00100bbb00011100FBBB111110111110.  */
+{ "mpyhu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyhu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ.  */
+{ "mpyhu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyhu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ.  */
+{ "mpyhu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyhu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA.  */
+{ "mpyhu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyhu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110.  */
+{ "mpyhu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyhu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ.  */
+{ "mpyhu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyhu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS.  */
+{ "mpyhu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyhu<.f> a,limm,limm 0010011000011100F111111110AAAAAA.  */
+{ "mpyhu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyhu<.f> 0,limm,limm 0010011000011100F111111110111110.  */
+{ "mpyhu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyhu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ.  */
+{ "mpyhu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA.  */
+{ "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }},
+
+/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110.  */
+{ "mpym", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ.  */
+{ "mpym", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA.  */
+{ "mpym", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110.  */
+{ "mpym", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ.  */
+{ "mpym", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS.  */
+{ "mpym", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA.  */
+{ "mpym", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }},
+
+/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA.  */
+{ "mpym", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110.  */
+{ "mpym", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110.  */
+{ "mpym", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ.  */
+{ "mpym", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ.  */
+{ "mpym", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA.  */
+{ "mpym", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110.  */
+{ "mpym", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ.  */
+{ "mpym", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS.  */
+{ "mpym", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA.  */
+{ "mpym", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110.  */
+{ "mpym", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ.  */
+{ "mpym", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA.  */
+{ "mpymu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }},
+
+/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110.  */
+{ "mpymu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ.  */
+{ "mpymu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA.  */
+{ "mpymu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110.  */
+{ "mpymu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ.  */
+{ "mpymu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS.  */
+{ "mpymu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA.  */
+{ "mpymu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }},
+
+/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA.  */
+{ "mpymu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110.  */
+{ "mpymu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110.  */
+{ "mpymu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ.  */
+{ "mpymu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ.  */
+{ "mpymu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA.  */
+{ "mpymu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110.  */
+{ "mpymu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ.  */
+{ "mpymu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS.  */
+{ "mpymu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA.  */
+{ "mpymu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110.  */
+{ "mpymu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ.  */
+{ "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyqb<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ.  */
+{ "mpyqb", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyqb<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA.  */
+{ "mpyqb", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyqb<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ.  */
+{ "mpyqb", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyqb<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS.  */
+{ "mpyqb", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyqb<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA.  */
+{ "mpyqb", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyqb<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA.  */
+{ "mpyqb", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyqb<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ.  */
+{ "mpyqb", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA.  */
+{ "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }},
+
+/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110.  */
+{ "mpyu", 0x201D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ.  */
+{ "mpyu", 0x20DD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA.  */
+{ "mpyu", 0x205D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110.  */
+{ "mpyu", 0x205D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ.  */
+{ "mpyu", 0x20DD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS.  */
+{ "mpyu", 0x209D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA.  */
+{ "mpyu", 0x261D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }},
+
+/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA.  */
+{ "mpyu", 0x201D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110.  */
+{ "mpyu", 0x261D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110.  */
+{ "mpyu", 0x201D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ.  */
+{ "mpyu", 0x20DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ.  */
+{ "mpyu", 0x26DD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA.  */
+{ "mpyu", 0x265D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110.  */
+{ "mpyu", 0x265D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ.  */
+{ "mpyu", 0x26DD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS.  */
+{ "mpyu", 0x269D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA.  */
+{ "mpyu", 0x261D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110.  */
+{ "mpyu", 0x261D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ.  */
+{ "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA.  */
+{ "mpyuw", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110.  */
+{ "mpyuw", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ.  */
+{ "mpyuw", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA.  */
+{ "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110.  */
+{ "mpyuw", 0x201F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, RC }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ.  */
+{ "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA.  */
+{ "mpyuw", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110.  */
+{ "mpyuw", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ.  */
+{ "mpyuw", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA.  */
+{ "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110.  */
+{ "mpyuw", 0x205F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ.  */
+{ "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS.  */
+{ "mpyuw", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS.  */
+{ "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA.  */
+{ "mpyuw", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA.  */
+{ "mpyuw", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f> 0,limm,c 0010011000111111F111CCCCCC111110.  */
+{ "mpyuw", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,limm 00100bbb00111111FBBB111110111110.  */
+{ "mpyuw", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ.  */
+{ "mpyuw", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyuw<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ.  */
+{ "mpyuw", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA.  */
+{ "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA.  */
+{ "mpyuw", 0x201F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110.  */
+{ "mpyuw", 0x261F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110.  */
+{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ.  */
+{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ.  */
+{ "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA.  */
+{ "mpyuw", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,limm,u6 0010011001111111F111uuuuuu111110.  */
+{ "mpyuw", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ.  */
+{ "mpyuw", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA.  */
+{ "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110.  */
+{ "mpyuw", 0x265F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ.  */
+{ "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS.  */
+{ "mpyuw", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS.  */
+{ "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> a,limm,limm 0010011000111111F111111110AAAAAA.  */
+{ "mpyuw", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f> 0,limm,limm 0010011000111111F111111110111110.  */
+{ "mpyuw", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ.  */
+{ "mpyuw", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA.  */
+{ "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110.  */
+{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ.  */
+{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw_s b,b,c 01111bbbccc01010.  */
+{ "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* mpyw<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA.  */
+{ "mpyw", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110.  */
+{ "mpyw", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ.  */
+{ "mpyw", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA.  */
+{ "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110.  */
+{ "mpyw", 0x201E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, RC }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ.  */
+{ "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA.  */
+{ "mpyw", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110.  */
+{ "mpyw", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ.  */
+{ "mpyw", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA.  */
+{ "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110.  */
+{ "mpyw", 0x205E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ.  */
+{ "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS.  */
+{ "mpyw", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS.  */
+{ "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA.  */
+{ "mpyw", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA.  */
+{ "mpyw", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyw<.f> 0,limm,c 0010011000111110F111CCCCCC111110.  */
+{ "mpyw", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,limm 00100bbb00111110FBBB111110111110.  */
+{ "mpyw", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ.  */
+{ "mpyw", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyw<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ.  */
+{ "mpyw", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA.  */
+{ "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA.  */
+{ "mpyw", 0x201E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, LIMM }, { C_F }},
+
+/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110.  */
+{ "mpyw", 0x261E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110.  */
+{ "mpyw", 0x201E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ.  */
+{ "mpyw", 0x20DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ.  */
+{ "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA.  */
+{ "mpyw", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,limm,u6 0010011001111110F111uuuuuu111110.  */
+{ "mpyw", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ.  */
+{ "mpyw", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA.  */
+{ "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110.  */
+{ "mpyw", 0x265E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ.  */
+{ "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS.  */
+{ "mpyw", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS.  */
+{ "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> a,limm,limm 0010011000111110F111111110AAAAAA.  */
+{ "mpyw", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f> 0,limm,limm 0010011000111110F111111110111110.  */
+{ "mpyw", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ.  */
+{ "mpyw", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA.  */
+{ "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110.  */
+{ "mpyw", 0x261E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ.  */
+{ "mpyw", 0x26DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhfl<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA.  */
+{ "mpywhfl", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpywhfl<.f> 0,b,c 00110bbb00100100FBBBCCCCCC111110.  */
+{ "mpywhfl", 0x3024003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhfl<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ.  */
+{ "mpywhfl", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhfl<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA.  */
+{ "mpywhfl", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f> 0,b,u6 00110bbb01100100FBBBuuuuuu111110.  */
+{ "mpywhfl", 0x3064003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ.  */
+{ "mpywhfl", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfl<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS.  */
+{ "mpywhfl", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhfl<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA.  */
+{ "mpywhfl", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpywhfl<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA.  */
+{ "mpywhfl", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpywhfl<.f> 0,limm,c 0011011001100100F111CCCCCC111110.  */
+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhfl<.f> 0,b,limm 00110bbb00100100FBBB111110111110.  */
+{ "mpywhfl", 0x30240FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhfl<.f><.cc> 0,limm,c 00110bbb11100100FBBB1111100QQQQQ.  */
+{ "mpywhfl", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhfl<.f><.cc> b,b,limm 0011011011100100F111CCCCCC0QQQQQ.  */
+{ "mpywhfl", 0x36E47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhfl<.f> a,limm,u6 0011011001100100F111uuuuuuAAAAAA.  */
+{ "mpywhfl", 0x36647000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f> 0,limm,u6 0011011001100100F111uuuuuu111110.  */
+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f><.cc> 0,limm,u6 0011011011100100F111uuuuuu1QQQQQ.  */
+{ "mpywhfl", 0x36E47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfl<.f> 0,limm,s12 0011011010100100F111ssssssSSSSSS.  */
+{ "mpywhfl", 0x36A47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhfl<.f> a,limm,limm 0011011000100100F111111110AAAAAA.  */
+{ "mpywhfl", 0x36247F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfl<.f> 0,limm,limm 0011011000100100F111111110111110.  */
+{ "mpywhfl", 0x36247FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfl<.f><.cc> 0,limm,limm 0011011011100100F1111111100QQQQQ.  */
+{ "mpywhfl", 0x36E47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhflr<.f> a,b,c 00110bbb00100101FBBBCCCCCCAAAAAA.  */
+{ "mpywhflr", 0x30250000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpywhflr<.f> 0,b,c 00110bbb00100101FBBBCCCCCC111110.  */
+{ "mpywhflr", 0x3025003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhflr<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ.  */
+{ "mpywhflr", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhflr<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA.  */
+{ "mpywhflr", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f> 0,b,u6 00110bbb01100101FBBBuuuuuu111110.  */
+{ "mpywhflr", 0x3065003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ.  */
+{ "mpywhflr", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhflr<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS.  */
+{ "mpywhflr", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhflr<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA.  */
+{ "mpywhflr", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpywhflr<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA.  */
+{ "mpywhflr", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpywhflr<.f> 0,limm,c 0011011001100101F111CCCCCC111110.  */
+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhflr<.f> 0,b,limm 00110bbb00100101FBBB111110111110.  */
+{ "mpywhflr", 0x30250FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhflr<.f><.cc> 0,limm,c 00110bbb11100101FBBB1111100QQQQQ.  */
+{ "mpywhflr", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhflr<.f><.cc> b,b,limm 0011011011100101F111CCCCCC0QQQQQ.  */
+{ "mpywhflr", 0x36E57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhflr<.f> a,limm,u6 0011011001100101F111uuuuuuAAAAAA.  */
+{ "mpywhflr", 0x36657000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f> 0,limm,u6 0011011001100101F111uuuuuu111110.  */
+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f><.cc> 0,limm,u6 0011011011100101F111uuuuuu1QQQQQ.  */
+{ "mpywhflr", 0x36E57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhflr<.f> 0,limm,s12 0011011010100101F111ssssssSSSSSS.  */
+{ "mpywhflr", 0x36A57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhflr<.f> a,limm,limm 0011011000100101F111111110AAAAAA.  */
+{ "mpywhflr", 0x36257F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhflr<.f> 0,limm,limm 0011011000100101F111111110111110.  */
+{ "mpywhflr", 0x36257FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhflr<.f><.cc> 0,limm,limm 0011011011100101F1111111100QQQQQ.  */
+{ "mpywhflr", 0x36E57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhfm<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA.  */
+{ "mpywhfm", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpywhfm<.f> 0,b,c 00110bbb00100000FBBBCCCCCC111110.  */
+{ "mpywhfm", 0x3020003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhfm<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ.  */
+{ "mpywhfm", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhfm<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA.  */
+{ "mpywhfm", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f> 0,b,u6 00110bbb01100000FBBBuuuuuu111110.  */
+{ "mpywhfm", 0x3060003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ.  */
+{ "mpywhfm", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfm<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS.  */
+{ "mpywhfm", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhfm<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA.  */
+{ "mpywhfm", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpywhfm<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA.  */
+{ "mpywhfm", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpywhfm<.f> 0,limm,c 0011011001100000F111CCCCCC111110.  */
+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhfm<.f> 0,b,limm 00110bbb00100000FBBB111110111110.  */
+{ "mpywhfm", 0x30200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhfm<.f><.cc> 0,limm,c 00110bbb11100000FBBB1111100QQQQQ.  */
+{ "mpywhfm", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhfm<.f><.cc> b,b,limm 0011011011100000F111CCCCCC0QQQQQ.  */
+{ "mpywhfm", 0x36E07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhfm<.f> a,limm,u6 0011011001100000F111uuuuuuAAAAAA.  */
+{ "mpywhfm", 0x36607000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f> 0,limm,u6 0011011001100000F111uuuuuu111110.  */
+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f><.cc> 0,limm,u6 0011011011100000F111uuuuuu1QQQQQ.  */
+{ "mpywhfm", 0x36E07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfm<.f> 0,limm,s12 0011011010100000F111ssssssSSSSSS.  */
+{ "mpywhfm", 0x36A07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhfm<.f> a,limm,limm 0011011000100000F111111110AAAAAA.  */
+{ "mpywhfm", 0x36207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfm<.f> 0,limm,limm 0011011000100000F111111110111110.  */
+{ "mpywhfm", 0x36207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfm<.f><.cc> 0,limm,limm 0011011011100000F1111111100QQQQQ.  */
+{ "mpywhfm", 0x36E07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA.  */
+{ "mpywhfmr", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpywhfmr<.f> 0,b,c 00110bbb00100001FBBBCCCCCC111110.  */
+{ "mpywhfmr", 0x3021003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhfmr<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ.  */
+{ "mpywhfmr", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA.  */
+{ "mpywhfmr", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f> 0,b,u6 00110bbb01100001FBBBuuuuuu111110.  */
+{ "mpywhfmr", 0x3061003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f><.cc> b,b,u6 00110bbb11100001FBBBuuuuuu1QQQQQ.  */
+{ "mpywhfmr", 0x30E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS.  */
+{ "mpywhfmr", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhfmr<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA.  */
+{ "mpywhfmr", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpywhfmr<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA.  */
+{ "mpywhfmr", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpywhfmr<.f> 0,limm,c 0011011001100001F111CCCCCC111110.  */
+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhfmr<.f> 0,b,limm 00110bbb00100001FBBB111110111110.  */
+{ "mpywhfmr", 0x30210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhfmr<.f><.cc> 0,limm,c 00110bbb11100001FBBB1111100QQQQQ.  */
+{ "mpywhfmr", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhfmr<.f><.cc> b,b,limm 0011011011100001F111CCCCCC0QQQQQ.  */
+{ "mpywhfmr", 0x36E17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> a,limm,u6 0011011001100001F111uuuuuuAAAAAA.  */
+{ "mpywhfmr", 0x36617000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f> 0,limm,u6 0011011001100001F111uuuuuu111110.  */
+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f><.cc> 0,limm,u6 0011011011100001F111uuuuuu1QQQQQ.  */
+{ "mpywhfmr", 0x36E17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> 0,limm,s12 0011011010100001F111ssssssSSSSSS.  */
+{ "mpywhfmr", 0x36A17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhfmr<.f> a,limm,limm 0011011000100001F111111110AAAAAA.  */
+{ "mpywhfmr", 0x36217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfmr<.f> 0,limm,limm 0011011000100001F111111110111110.  */
+{ "mpywhfmr", 0x36217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfmr<.f><.cc> 0,limm,limm 0011011011100001F1111111100QQQQQ.  */
+{ "mpywhfmr", 0x36E17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhl<.f> a,b,c 00110bbb00011100FBBBCCCCCCAAAAAA.  */
+{ "mpywhl", 0x301C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpywhl<.f> 0,b,c 00110bbb00011100FBBBCCCCCC111110.  */
+{ "mpywhl", 0x301C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhl<.f><.cc> b,b,c 00110bbb11011100FBBBCCCCCC0QQQQQ.  */
+{ "mpywhl", 0x30DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhl<.f> a,b,u6 00110bbb01011100FBBBuuuuuuAAAAAA.  */
+{ "mpywhl", 0x305C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f> 0,b,u6 00110bbb01011100FBBBuuuuuu111110.  */
+{ "mpywhl", 0x305C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f><.cc> b,b,u6 00110bbb11011100FBBBuuuuuu1QQQQQ.  */
+{ "mpywhl", 0x30DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhl<.f> b,b,s12 00110bbb10011100FBBBssssssSSSSSS.  */
+{ "mpywhl", 0x309C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhl<.f> a,limm,c 0011011000011100F111CCCCCCAAAAAA.  */
+{ "mpywhl", 0x361C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpywhl<.f> a,b,limm 00110bbb00011100FBBB111110AAAAAA.  */
+{ "mpywhl", 0x301C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpywhl<.f> 0,limm,c 0011011000011100F111CCCCCC111110.  */
+{ "mpywhl", 0x361C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhl<.f> 0,b,limm 00110bbb00011100FBBB111110111110.  */
+{ "mpywhl", 0x301C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhl<.f><.cc> 0,limm,c 00110bbb11011100FBBB1111100QQQQQ.  */
+{ "mpywhl", 0x30DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhl<.f><.cc> b,b,limm 0011011011011100F111CCCCCC0QQQQQ.  */
+{ "mpywhl", 0x36DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhl<.f> a,limm,u6 0011011001011100F111uuuuuuAAAAAA.  */
+{ "mpywhl", 0x365C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f> 0,limm,u6 0011011001011100F111uuuuuu111110.  */
+{ "mpywhl", 0x365C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f><.cc> 0,limm,u6 0011011011011100F111uuuuuu1QQQQQ.  */
+{ "mpywhl", 0x36DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhl<.f> 0,limm,s12 0011011010011100F111ssssssSSSSSS.  */
+{ "mpywhl", 0x369C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhl<.f> a,limm,limm 0011011000011100F111111110AAAAAA.  */
+{ "mpywhl", 0x361C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhl<.f> 0,limm,limm 0011011000011100F111111110111110.  */
+{ "mpywhl", 0x361C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhl<.f><.cc> 0,limm,limm 0011011011011100F1111111100QQQQQ.  */
+{ "mpywhl", 0x36DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhul<.f> a,b,c 00110bbb00011110FBBBCCCCCCAAAAAA.  */
+{ "mpywhul", 0x301E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpywhul<.f> 0,b,c 00110bbb00011110FBBBCCCCCC111110.  */
+{ "mpywhul", 0x301E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhul<.f><.cc> b,b,c 00110bbb11011110FBBBCCCCCC0QQQQQ.  */
+{ "mpywhul", 0x30DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhul<.f> a,b,u6 00110bbb01011110FBBBuuuuuuAAAAAA.  */
+{ "mpywhul", 0x305E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f> 0,b,u6 00110bbb01011110FBBBuuuuuu111110.  */
+{ "mpywhul", 0x305E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f><.cc> b,b,u6 00110bbb11011110FBBBuuuuuu1QQQQQ.  */
+{ "mpywhul", 0x30DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhul<.f> b,b,s12 00110bbb10011110FBBBssssssSSSSSS.  */
+{ "mpywhul", 0x309E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhul<.f> a,limm,c 0011011000011110F111CCCCCCAAAAAA.  */
+{ "mpywhul", 0x361E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpywhul<.f> a,b,limm 00110bbb00011110FBBB111110AAAAAA.  */
+{ "mpywhul", 0x301E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpywhul<.f> 0,limm,c 0011011000011110F111CCCCCC111110.  */
+{ "mpywhul", 0x361E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhul<.f> 0,b,limm 00110bbb00011110FBBB111110111110.  */
+{ "mpywhul", 0x301E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhul<.f><.cc> 0,limm,c 00110bbb11011110FBBB1111100QQQQQ.  */
+{ "mpywhul", 0x30DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhul<.f><.cc> b,b,limm 0011011011011110F111CCCCCC0QQQQQ.  */
+{ "mpywhul", 0x36DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhul<.f> a,limm,u6 0011011001011110F111uuuuuuAAAAAA.  */
+{ "mpywhul", 0x365E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f> 0,limm,u6 0011011001011110F111uuuuuu111110.  */
+{ "mpywhul", 0x365E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f><.cc> 0,limm,u6 0011011011011110F111uuuuuu1QQQQQ.  */
+{ "mpywhul", 0x36DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhul<.f> 0,limm,s12 0011011010011110F111ssssssSSSSSS.  */
+{ "mpywhul", 0x369E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhul<.f> a,limm,limm 0011011000011110F111111110AAAAAA.  */
+{ "mpywhul", 0x361E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhul<.f> 0,limm,limm 0011011000011110F111111110111110.  */
+{ "mpywhul", 0x361E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhul<.f><.cc> 0,limm,limm 0011011011011110F1111111100QQQQQ.  */
+{ "mpywhul", 0x36DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyw_s b,b,c 01111bbbccc01001.  */
+{ "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* mpy_s b,b,c 01111bbbccc01100.  */
+{ "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* msubdf<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA.  */
+{ "msubdf", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* msubdf<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110.  */
+{ "msubdf", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubdf<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ.  */
+{ "msubdf", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* msubdf<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA.  */
+{ "msubdf", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110.  */
+{ "msubdf", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ.  */
+{ "msubdf", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubdf<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS.  */
+{ "msubdf", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubdf<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA.  */
+{ "msubdf", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* msubdf<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA.  */
+{ "msubdf", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* msubdf<.f> 0,limm,c 0011011000010101F111CCCCCC111110.  */
+{ "msubdf", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubdf<.f> 0,b,limm 00110bbb00010101FBBB111110111110.  */
+{ "msubdf", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubdf<.f><.cc> 0,limm,c 00110bbb11010101FBBB1111100QQQQQ.  */
+{ "msubdf", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubdf<.f><.cc> b,b,limm 0011011011010101F111CCCCCC0QQQQQ.  */
+{ "msubdf", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubdf<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA.  */
+{ "msubdf", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f> 0,limm,u6 0011011001010101F111uuuuuu111110.  */
+{ "msubdf", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ.  */
+{ "msubdf", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubdf<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS.  */
+{ "msubdf", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubdf<.f> a,limm,limm 0011011000010101F111111110AAAAAA.  */
+{ "msubdf", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* msubdf<.f> 0,limm,limm 0011011000010101F111111110111110.  */
+{ "msubdf", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubdf<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ.  */
+{ "msubdf", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubdw<.f> a,b,c 00101bbb00010100FBBBCCCCCCAAAAAA.  */
+{ "msubdw", 0x28140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* msubdw<.f> 0,b,c 00101bbb00010100FBBBCCCCCC111110.  */
+{ "msubdw", 0x2814003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubdw<.f><.cc> b,b,c 00101bbb11010100FBBBCCCCCC0QQQQQ.  */
+{ "msubdw", 0x28D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* msubdw<.f> a,b,u6 00101bbb01010100FBBBuuuuuuAAAAAA.  */
+{ "msubdw", 0x28540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* msubdw<.f> 0,b,u6 00101bbb01010100FBBBuuuuuu111110.  */
+{ "msubdw", 0x2854003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubdw<.f><.cc> b,b,u6 00101bbb11010100FBBBuuuuuu1QQQQQ.  */
+{ "msubdw", 0x28D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubdw<.f> b,b,s12 00101bbb10010100FBBBssssssSSSSSS.  */
+{ "msubdw", 0x28940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubdw<.f> a,limm,c 0010111000010100F111CCCCCCAAAAAA.  */
+{ "msubdw", 0x2E147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* msubdw<.f> a,b,limm 00101bbb00010100FBBB111110AAAAAA.  */
+{ "msubdw", 0x28140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* msubdw<.f> 0,limm,c 0010111000010100F111CCCCCC111110.  */
+{ "msubdw", 0x2E14703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubdw<.f> 0,b,limm 00101bbb00010100FBBB111110111110.  */
+{ "msubdw", 0x28140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubdw<.f><.cc> 0,limm,c 0010111011010100F111CCCCCC0QQQQQ.  */
+{ "msubdw", 0x2ED47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubdw<.f><.cc> b,b,limm 00101bbb11010100FBBB1111100QQQQQ.  */
+{ "msubdw", 0x28D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubdw<.f> a,limm,u6 0010111001010100F111uuuuuuAAAAAA.  */
+{ "msubdw", 0x2E547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubdw<.f> 0,limm,u6 0010111001010100F111uuuuuu111110.  */
+{ "msubdw", 0x2E54703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubdw<.f><.cc> 0,limm,u6 0010111011010100F111uuuuuu1QQQQQ.  */
+{ "msubdw", 0x2ED47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubdw<.f> 0,limm,s12 0010111010010100F111ssssssSSSSSS.  */
+{ "msubdw", 0x2E947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubdw<.f> a,limm,limm 0010111000010100F111111110AAAAAA.  */
+{ "msubdw", 0x2E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* msubdw<.f> 0,limm,limm 0010111000010100F111111110111110.  */
+{ "msubdw", 0x2E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubdw<.f><.cc> 0,limm,limm 0010111011010100F1111111100QQQQQ.  */
+{ "msubdw", 0x2ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubf<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA.  */
+{ "msubf", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* msubf<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110.  */
+{ "msubf", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubf<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ.  */
+{ "msubf", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* msubf<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA.  */
+{ "msubf", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* msubf<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110.  */
+{ "msubf", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubf<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ.  */
+{ "msubf", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubf<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS.  */
+{ "msubf", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubf<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA.  */
+{ "msubf", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* msubf<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA.  */
+{ "msubf", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* msubf<.f> 0,limm,c 0011011000001110F111CCCCCC111110.  */
+{ "msubf", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubf<.f> 0,b,limm 00110bbb00001110FBBB111110111110.  */
+{ "msubf", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubf<.f><.cc> 0,limm,c 00110bbb11001110FBBB1111100QQQQQ.  */
+{ "msubf", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubf<.f><.cc> b,b,limm 0011011011001110F111CCCCCC0QQQQQ.  */
+{ "msubf", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubf<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA.  */
+{ "msubf", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubf<.f> 0,limm,u6 0011011001001110F111uuuuuu111110.  */
+{ "msubf", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubf<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ.  */
+{ "msubf", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubf<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS.  */
+{ "msubf", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubf<.f> a,limm,limm 0011011000001110F111111110AAAAAA.  */
+{ "msubf", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* msubf<.f> 0,limm,limm 0011011000001110F111111110111110.  */
+{ "msubf", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubf<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ.  */
+{ "msubf", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubfr<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA.  */
+{ "msubfr", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* msubfr<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110.  */
+{ "msubfr", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubfr<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ.  */
+{ "msubfr", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* msubfr<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA.  */
+{ "msubfr", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110.  */
+{ "msubfr", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ.  */
+{ "msubfr", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubfr<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS.  */
+{ "msubfr", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubfr<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA.  */
+{ "msubfr", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* msubfr<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA.  */
+{ "msubfr", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* msubfr<.f> 0,limm,c 0011011000001111F111CCCCCC111110.  */
+{ "msubfr", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubfr<.f> 0,b,limm 00110bbb00001111FBBB111110111110.  */
+{ "msubfr", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubfr<.f><.cc> 0,limm,c 00110bbb11001111FBBB1111100QQQQQ.  */
+{ "msubfr", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubfr<.f><.cc> b,b,limm 0011011011001111F111CCCCCC0QQQQQ.  */
+{ "msubfr", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubfr<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA.  */
+{ "msubfr", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f> 0,limm,u6 0011011001001111F111uuuuuu111110.  */
+{ "msubfr", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ.  */
+{ "msubfr", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubfr<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS.  */
+{ "msubfr", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubfr<.f> a,limm,limm 0011011000001111F111111110AAAAAA.  */
+{ "msubfr", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* msubfr<.f> 0,limm,limm 0011011000001111F111111110111110.  */
+{ "msubfr", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubfr<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ.  */
+{ "msubfr", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubt<.f> a,b,c 00101bbb00100000FBBBCCCCCCAAAAAA.  */
+{ "msubt", 0x28200000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* msubt<.f> 0,b,c 00101bbb00100000FBBBCCCCCC111110.  */
+{ "msubt", 0x2820003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubt<.f><.cc> b,b,c 00101bbb11100000FBBBCCCCCC0QQQQQ.  */
+{ "msubt", 0x28E00000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* msubt<.f> a,b,u6 00101bbb01100000FBBBuuuuuuAAAAAA.  */
+{ "msubt", 0x28600000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* msubt<.f> 0,b,u6 00101bbb01100000FBBBuuuuuu111110.  */
+{ "msubt", 0x2860003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubt<.f><.cc> b,b,u6 00101bbb11100000FBBBuuuuuu1QQQQQ.  */
+{ "msubt", 0x28E00020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubt<.f> b,b,s12 00101bbb10100000FBBBssssssSSSSSS.  */
+{ "msubt", 0x28A00000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubt<.f> a,limm,c 0010111000100000F111CCCCCCAAAAAA.  */
+{ "msubt", 0x2E207000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* msubt<.f> a,b,limm 00101bbb00100000FBBB111110AAAAAA.  */
+{ "msubt", 0x28200F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* msubt<.f> 0,limm,c 0010111000100000F111CCCCCC111110.  */
+{ "msubt", 0x2E20703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubt<.f> 0,b,limm 00101bbb00100000FBBB111110111110.  */
+{ "msubt", 0x28200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubt<.f><.cc> 0,limm,c 0010111011100000F111CCCCCC0QQQQQ.  */
+{ "msubt", 0x2EE07000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubt<.f><.cc> b,b,limm 00101bbb11100000FBBB1111100QQQQQ.  */
+{ "msubt", 0x28E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubt<.f> a,limm,u6 0010111001100000F111uuuuuuAAAAAA.  */
+{ "msubt", 0x2E607000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubt<.f> 0,limm,u6 0010111001100000F111uuuuuu111110.  */
+{ "msubt", 0x2E60703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubt<.f><.cc> 0,limm,u6 0010111011100000F111uuuuuu1QQQQQ.  */
+{ "msubt", 0x2EE07020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubt<.f> 0,limm,s12 0010111010100000F111ssssssSSSSSS.  */
+{ "msubt", 0x2EA07000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubt<.f> a,limm,limm 0010111000100000F111111110AAAAAA.  */
+{ "msubt", 0x2E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* msubt<.f> 0,limm,limm 0010111000100000F111111110111110.  */
+{ "msubt", 0x2E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubt<.f><.cc> 0,limm,limm 0010111011100000F1111111100QQQQQ.  */
+{ "msubt", 0x2EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110.  */
+{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ.  */
+{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_CC }},
+
+/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110.  */
+{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ.  */
+{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_CC }},
+
+/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS.  */
+{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, SIMM12_20 }, { 0 }},
+
+/* mul64 0,limm,c 00101110000001000111CCCCCC111110.  */
+{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* mul64 0,b,limm 00101bbb000001000BBB111110111110.  */
+{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ.  */
+{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ.  */
+{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_CC }},
+
+/* mul64 0,limm,u6 00101110010001000111uuuuuu111110.  */
+{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ.  */
+{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS.  */
+{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* mul64 0,limm,limm 00101110000001000111111110111110.  */
+{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ.  */
+{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110.  */
+{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ.  */
+{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110.  */
+{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ.  */
+{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS.  */
+{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* mul64 0,limm,c 00101110000001000111CCCCCC111110.  */
+{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* mul64 0,b,limm 00101bbb000001000BBB111110111110.  */
+{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ.  */
+{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ.  */
+{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* mul64 0,limm,u6 00101110010001000111uuuuuu111110.  */
+{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ.  */
+{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS.  */
+{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* mul64 0,limm,limm 00101110000001000111111110111110.  */
+{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ.  */
+{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* mul64_s 0,b,c 01111bbbccc01100.  */
+{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA_S, RB_S, RC_S }, { 0 }},
+
+/* mul64_s 0,b,c 01111bbbccc01100.  */
+{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* muldw<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA.  */
+{ "muldw", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* muldw<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110.  */
+{ "muldw", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* muldw<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ.  */
+{ "muldw", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* muldw<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA.  */
+{ "muldw", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* muldw<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110.  */
+{ "muldw", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* muldw<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ.  */
+{ "muldw", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* muldw<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS.  */
+{ "muldw", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* muldw<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA.  */
+{ "muldw", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* muldw<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA.  */
+{ "muldw", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* muldw<.f> 0,limm,c 0010111000001100F111CCCCCC111110.  */
+{ "muldw", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* muldw<.f> 0,b,limm 00101bbb00001100FBBB111110111110.  */
+{ "muldw", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* muldw<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ.  */
+{ "muldw", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* muldw<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ.  */
+{ "muldw", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* muldw<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA.  */
+{ "muldw", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* muldw<.f> 0,limm,u6 0010111001001100F111uuuuuu111110.  */
+{ "muldw", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* muldw<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ.  */
+{ "muldw", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* muldw<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS.  */
+{ "muldw", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* muldw<.f> a,limm,limm 0010111000001100F111111110AAAAAA.  */
+{ "muldw", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* muldw<.f> 0,limm,limm 0010111000001100F111111110111110.  */
+{ "muldw", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* muldw<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ.  */
+{ "muldw", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulflw<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA.  */
+{ "mulflw", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mulflw<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110.  */
+{ "mulflw", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mulflw<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ.  */
+{ "mulflw", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mulflw<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA.  */
+{ "mulflw", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mulflw<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110.  */
+{ "mulflw", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mulflw<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ.  */
+{ "mulflw", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulflw<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS.  */
+{ "mulflw", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mulflw<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA.  */
+{ "mulflw", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mulflw<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA.  */
+{ "mulflw", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mulflw<.f> 0,limm,c 0010111000110010F111CCCCCC111110.  */
+{ "mulflw", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mulflw<.f> 0,b,limm 00101bbb00110010FBBB111110111110.  */
+{ "mulflw", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mulflw<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ.  */
+{ "mulflw", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mulflw<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ.  */
+{ "mulflw", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mulflw<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA.  */
+{ "mulflw", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulflw<.f> 0,limm,u6 0010111001110010F111uuuuuu111110.  */
+{ "mulflw", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulflw<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ.  */
+{ "mulflw", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulflw<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS.  */
+{ "mulflw", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mulflw<.f> a,limm,limm 0010111000110010F111111110AAAAAA.  */
+{ "mulflw", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mulflw<.f> 0,limm,limm 0010111000110010F111111110111110.  */
+{ "mulflw", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mulflw<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ.  */
+{ "mulflw", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulhflw<.f> a,b,c 00101bbb00111001FBBBCCCCCCAAAAAA.  */
+{ "mulhflw", 0x28390000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mulhflw<.f> 0,b,c 00101bbb00111001FBBBCCCCCC111110.  */
+{ "mulhflw", 0x2839003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mulhflw<.f><.cc> b,b,c 00101bbb11111001FBBBCCCCCC0QQQQQ.  */
+{ "mulhflw", 0x28F90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mulhflw<.f> a,b,u6 00101bbb01111001FBBBuuuuuuAAAAAA.  */
+{ "mulhflw", 0x28790000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mulhflw<.f> 0,b,u6 00101bbb01111001FBBBuuuuuu111110.  */
+{ "mulhflw", 0x2879003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mulhflw<.f><.cc> b,b,u6 00101bbb11111001FBBBuuuuuu1QQQQQ.  */
+{ "mulhflw", 0x28F90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulhflw<.f> b,b,s12 00101bbb10111001FBBBssssssSSSSSS.  */
+{ "mulhflw", 0x28B90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mulhflw<.f> a,limm,c 0010111000111001F111CCCCCCAAAAAA.  */
+{ "mulhflw", 0x2E397000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mulhflw<.f> a,b,limm 00101bbb00111001FBBB111110AAAAAA.  */
+{ "mulhflw", 0x28390F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mulhflw<.f> 0,limm,c 0010111000111001F111CCCCCC111110.  */
+{ "mulhflw", 0x2E39703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mulhflw<.f> 0,b,limm 00101bbb00111001FBBB111110111110.  */
+{ "mulhflw", 0x28390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mulhflw<.f><.cc> 0,limm,c 0010111011111001F111CCCCCC0QQQQQ.  */
+{ "mulhflw", 0x2EF97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mulhflw<.f><.cc> b,b,limm 00101bbb11111001FBBB1111100QQQQQ.  */
+{ "mulhflw", 0x28F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mulhflw<.f> a,limm,u6 0010111001111001F111uuuuuuAAAAAA.  */
+{ "mulhflw", 0x2E797000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulhflw<.f> 0,limm,u6 0010111001111001F111uuuuuu111110.  */
+{ "mulhflw", 0x2E79703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulhflw<.f><.cc> 0,limm,u6 0010111011111001F111uuuuuu1QQQQQ.  */
+{ "mulhflw", 0x2EF97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulhflw<.f> 0,limm,s12 0010111010111001F111ssssssSSSSSS.  */
+{ "mulhflw", 0x2EB97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mulhflw<.f> a,limm,limm 0010111000111001F111111110AAAAAA.  */
+{ "mulhflw", 0x2E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mulhflw<.f> 0,limm,limm 0010111000111001F111111110111110.  */
+{ "mulhflw", 0x2E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mulhflw<.f><.cc> 0,limm,limm 0010111011111001F1111111100QQQQQ.  */
+{ "mulhflw", 0x2EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulhlw<.f> a,b,c 00101bbb00111000FBBBCCCCCCAAAAAA.  */
+{ "mulhlw", 0x28380000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mulhlw<.f> 0,b,c 00101bbb00111000FBBBCCCCCC111110.  */
+{ "mulhlw", 0x2838003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mulhlw<.f><.cc> b,b,c 00101bbb11111000FBBBCCCCCC0QQQQQ.  */
+{ "mulhlw", 0x28F80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mulhlw<.f> a,b,u6 00101bbb01111000FBBBuuuuuuAAAAAA.  */
+{ "mulhlw", 0x28780000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mulhlw<.f> 0,b,u6 00101bbb01111000FBBBuuuuuu111110.  */
+{ "mulhlw", 0x2878003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mulhlw<.f><.cc> b,b,u6 00101bbb11111000FBBBuuuuuu1QQQQQ.  */
+{ "mulhlw", 0x28F80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulhlw<.f> b,b,s12 00101bbb10111000FBBBssssssSSSSSS.  */
+{ "mulhlw", 0x28B80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mulhlw<.f> a,limm,c 0010111000111000F111CCCCCCAAAAAA.  */
+{ "mulhlw", 0x2E387000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mulhlw<.f> a,b,limm 00101bbb00111000FBBB111110AAAAAA.  */
+{ "mulhlw", 0x28380F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mulhlw<.f> 0,limm,c 0010111000111000F111CCCCCC111110.  */
+{ "mulhlw", 0x2E38703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mulhlw<.f> 0,b,limm 00101bbb00111000FBBB111110111110.  */
+{ "mulhlw", 0x28380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mulhlw<.f><.cc> 0,limm,c 0010111011111000F111CCCCCC0QQQQQ.  */
+{ "mulhlw", 0x2EF87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mulhlw<.f><.cc> b,b,limm 00101bbb11111000FBBB1111100QQQQQ.  */
+{ "mulhlw", 0x28F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mulhlw<.f> a,limm,u6 0010111001111000F111uuuuuuAAAAAA.  */
+{ "mulhlw", 0x2E787000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulhlw<.f> 0,limm,u6 0010111001111000F111uuuuuu111110.  */
+{ "mulhlw", 0x2E78703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulhlw<.f><.cc> 0,limm,u6 0010111011111000F111uuuuuu1QQQQQ.  */
+{ "mulhlw", 0x2EF87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulhlw<.f> 0,limm,s12 0010111010111000F111ssssssSSSSSS.  */
+{ "mulhlw", 0x2EB87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mulhlw<.f> a,limm,limm 0010111000111000F111111110AAAAAA.  */
+{ "mulhlw", 0x2E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mulhlw<.f> 0,limm,limm 0010111000111000F111111110111110.  */
+{ "mulhlw", 0x2E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mulhlw<.f><.cc> 0,limm,limm 0010111011111000F1111111100QQQQQ.  */
+{ "mulhlw", 0x2EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mullw<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA.  */
+{ "mullw", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mullw<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110.  */
+{ "mullw", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mullw<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ.  */
+{ "mullw", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mullw<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA.  */
+{ "mullw", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mullw<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110.  */
+{ "mullw", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mullw<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ.  */
+{ "mullw", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mullw<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS.  */
+{ "mullw", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mullw<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA.  */
+{ "mullw", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mullw<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA.  */
+{ "mullw", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mullw<.f> 0,limm,c 0010111000110001F111CCCCCC111110.  */
+{ "mullw", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mullw<.f> 0,b,limm 00101bbb00110001FBBB111110111110.  */
+{ "mullw", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mullw<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ.  */
+{ "mullw", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mullw<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ.  */
+{ "mullw", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mullw<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA.  */
+{ "mullw", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mullw<.f> 0,limm,u6 0010111001110001F111uuuuuu111110.  */
+{ "mullw", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mullw<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ.  */
+{ "mullw", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mullw<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS.  */
+{ "mullw", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mullw<.f> a,limm,limm 0010111000110001F111111110AAAAAA.  */
+{ "mullw", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mullw<.f> 0,limm,limm 0010111000110001F111111110111110.  */
+{ "mullw", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mullw<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ.  */
+{ "mullw", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulrdw<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA.  */
+{ "mulrdw", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mulrdw<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110.  */
+{ "mulrdw", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mulrdw<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ.  */
+{ "mulrdw", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mulrdw<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA.  */
+{ "mulrdw", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mulrdw<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110.  */
+{ "mulrdw", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mulrdw<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ.  */
+{ "mulrdw", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulrdw<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS.  */
+{ "mulrdw", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mulrdw<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA.  */
+{ "mulrdw", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mulrdw<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA.  */
+{ "mulrdw", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mulrdw<.f> 0,limm,c 0010111000001110F111CCCCCC111110.  */
+{ "mulrdw", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mulrdw<.f> 0,b,limm 00101bbb00001110FBBB111110111110.  */
+{ "mulrdw", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mulrdw<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ.  */
+{ "mulrdw", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mulrdw<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ.  */
+{ "mulrdw", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mulrdw<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA.  */
+{ "mulrdw", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulrdw<.f> 0,limm,u6 0010111001001110F111uuuuuu111110.  */
+{ "mulrdw", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulrdw<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ.  */
+{ "mulrdw", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulrdw<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS.  */
+{ "mulrdw", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mulrdw<.f> a,limm,limm 0010111000001110F111111110AAAAAA.  */
+{ "mulrdw", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mulrdw<.f> 0,limm,limm 0010111000001110F111111110111110.  */
+{ "mulrdw", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mulrdw<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ.  */
+{ "mulrdw", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulrt<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA.  */
+{ "mulrt", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mulrt<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110.  */
+{ "mulrt", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mulrt<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ.  */
+{ "mulrt", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mulrt<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA.  */
+{ "mulrt", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mulrt<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110.  */
+{ "mulrt", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mulrt<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ.  */
+{ "mulrt", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulrt<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS.  */
+{ "mulrt", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mulrt<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA.  */
+{ "mulrt", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mulrt<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA.  */
+{ "mulrt", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mulrt<.f> 0,limm,c 0010111000011010F111CCCCCC111110.  */
+{ "mulrt", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mulrt<.f> 0,b,limm 00101bbb00011010FBBB111110111110.  */
+{ "mulrt", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mulrt<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ.  */
+{ "mulrt", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mulrt<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ.  */
+{ "mulrt", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mulrt<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA.  */
+{ "mulrt", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulrt<.f> 0,limm,u6 0010111001011010F111uuuuuu111110.  */
+{ "mulrt", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulrt<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ.  */
+{ "mulrt", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulrt<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS.  */
+{ "mulrt", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mulrt<.f> a,limm,limm 0010111000011010F111111110AAAAAA.  */
+{ "mulrt", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mulrt<.f> 0,limm,limm 0010111000011010F111111110111110.  */
+{ "mulrt", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mulrt<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ.  */
+{ "mulrt", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mult<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA.  */
+{ "mult", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mult<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110.  */
+{ "mult", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mult<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ.  */
+{ "mult", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mult<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA.  */
+{ "mult", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mult<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110.  */
+{ "mult", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mult<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ.  */
+{ "mult", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mult<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS.  */
+{ "mult", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mult<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA.  */
+{ "mult", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mult<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA.  */
+{ "mult", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mult<.f> 0,limm,c 0010111000011000F111CCCCCC111110.  */
+{ "mult", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mult<.f> 0,b,limm 00101bbb00011000FBBB111110111110.  */
+{ "mult", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mult<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ.  */
+{ "mult", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mult<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ.  */
+{ "mult", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mult<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA.  */
+{ "mult", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mult<.f> 0,limm,u6 0010111001011000F111uuuuuu111110.  */
+{ "mult", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mult<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ.  */
+{ "mult", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mult<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS.  */
+{ "mult", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mult<.f> a,limm,limm 0010111000011000F111111110AAAAAA.  */
+{ "mult", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mult<.f> 0,limm,limm 0010111000011000F111111110111110.  */
+{ "mult", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mult<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ.  */
+{ "mult", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110.  */
+{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ.  */
+{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_CC }},
+
+/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110.  */
+{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ.  */
+{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_CC }},
+
+/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS.  */
+{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, SIMM12_20 }, { 0 }},
+
+/* mulu64 0,limm,c 00101110000001010111CCCCCC111110.  */
+{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* mulu64 0,b,limm 00101bbb000001010BBB111110111110.  */
+{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ.  */
+{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ.  */
+{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_CC }},
+
+/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110.  */
+{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ.  */
+{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS.  */
+{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* mulu64 0,limm,limm 00101110000001010111111110111110.  */
+{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ.  */
+{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110.  */
+{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ.  */
+{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110.  */
+{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ.  */
+{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS.  */
+{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* mulu64 0,limm,c 00101110000001010111CCCCCC111110.  */
+{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* mulu64 0,b,limm 00101bbb000001010BBB111110111110.  */
+{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ.  */
+{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ.  */
+{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110.  */
+{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ.  */
+{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS.  */
+{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* mulu64 0,limm,limm 00101110000001010111111110111110.  */
+{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ.  */
+{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* muludw<.f> a,b,c 00101bbb00001101FBBBCCCCCCAAAAAA.  */
+{ "muludw", 0x280D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* muludw<.f> 0,b,c 00101bbb00001101FBBBCCCCCC111110.  */
+{ "muludw", 0x280D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* muludw<.f><.cc> b,b,c 00101bbb11001101FBBBCCCCCC0QQQQQ.  */
+{ "muludw", 0x28CD0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* muludw<.f> a,b,u6 00101bbb01001101FBBBuuuuuuAAAAAA.  */
+{ "muludw", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* muludw<.f> 0,b,u6 00101bbb01001101FBBBuuuuuu111110.  */
+{ "muludw", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* muludw<.f><.cc> b,b,u6 00101bbb11001101FBBBuuuuuu1QQQQQ.  */
+{ "muludw", 0x28CD0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* muludw<.f> b,b,s12 00101bbb10001101FBBBssssssSSSSSS.  */
+{ "muludw", 0x288D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* muludw<.f> a,limm,c 0010111000001101F111CCCCCCAAAAAA.  */
+{ "muludw", 0x2E0D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* muludw<.f> a,b,limm 00101bbb00001101FBBB111110AAAAAA.  */
+{ "muludw", 0x280D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* muludw<.f> 0,limm,c 0010111000001101F111CCCCCC111110.  */
+{ "muludw", 0x2E0D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* muludw<.f> 0,b,limm 00101bbb00001101FBBB111110111110.  */
+{ "muludw", 0x280D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* muludw<.f><.cc> 0,limm,c 0010111011001101F111CCCCCC0QQQQQ.  */
+{ "muludw", 0x2ECD7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* muludw<.f><.cc> b,b,limm 00101bbb11001101FBBB1111100QQQQQ.  */
+{ "muludw", 0x28CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* muludw<.f> a,limm,u6 0010111001001101F111uuuuuuAAAAAA.  */
+{ "muludw", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* muludw<.f> 0,limm,u6 0010111001001101F111uuuuuu111110.  */
+{ "muludw", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* muludw<.f><.cc> 0,limm,u6 0010111011001101F111uuuuuu1QQQQQ.  */
+{ "muludw", 0x2ECD7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* muludw<.f> 0,limm,s12 0010111010001101F111ssssssSSSSSS.  */
+{ "muludw", 0x2E8D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* muludw<.f> a,limm,limm 0010111000001101F111111110AAAAAA.  */
+{ "muludw", 0x2E0D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* muludw<.f> 0,limm,limm 0010111000001101F111111110111110.  */
+{ "muludw", 0x2E0D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* muludw<.f><.cc> 0,limm,limm 0010111011001101F1111111100QQQQQ.  */
+{ "muludw", 0x2ECD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mululw<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA.  */
+{ "mululw", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mululw<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110.  */
+{ "mululw", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mululw<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ.  */
+{ "mululw", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mululw<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA.  */
+{ "mululw", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mululw<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110.  */
+{ "mululw", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mululw<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ.  */
+{ "mululw", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mululw<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS.  */
+{ "mululw", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mululw<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA.  */
+{ "mululw", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mululw<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA.  */
+{ "mululw", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mululw<.f> 0,limm,c 0010111000110000F111CCCCCC111110.  */
+{ "mululw", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mululw<.f> 0,b,limm 00101bbb00110000FBBB111110111110.  */
+{ "mululw", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mululw<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ.  */
+{ "mululw", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mululw<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ.  */
+{ "mululw", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mululw<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA.  */
+{ "mululw", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mululw<.f> 0,limm,u6 0010111001110000F111uuuuuu111110.  */
+{ "mululw", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mululw<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ.  */
+{ "mululw", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mululw<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS.  */
+{ "mululw", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mululw<.f> a,limm,limm 0010111000110000F111111110AAAAAA.  */
+{ "mululw", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mululw<.f> 0,limm,limm 0010111000110000F111111110111110.  */
+{ "mululw", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mululw<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ.  */
+{ "mululw", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mulut<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA.  */
+{ "mulut", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+
+/* mulut<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110.  */
+{ "mulut", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mulut<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ.  */
+{ "mulut", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mulut<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA.  */
+{ "mulut", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mulut<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110.  */
+{ "mulut", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mulut<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ.  */
+{ "mulut", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulut<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS.  */
+{ "mulut", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mulut<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA.  */
+{ "mulut", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mulut<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA.  */
+{ "mulut", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mulut<.f> 0,limm,c 0010111000011001F111CCCCCC111110.  */
+{ "mulut", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mulut<.f> 0,b,limm 00101bbb00011001FBBB111110111110.  */
+{ "mulut", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mulut<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ.  */
+{ "mulut", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mulut<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ.  */
+{ "mulut", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mulut<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA.  */
+{ "mulut", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulut<.f> 0,limm,u6 0010111001011001F111uuuuuu111110.  */
+{ "mulut", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mulut<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ.  */
+{ "mulut", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mulut<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS.  */
+{ "mulut", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mulut<.f> a,limm,limm 0010111000011001F111111110AAAAAA.  */
+{ "mulut", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mulut<.f> 0,limm,limm 0010111000011001F111111110111110.  */
+{ "mulut", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mulut<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ.  */
+{ "mulut", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA.  */
+{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB }, { C_F }},
+
+/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ.  */
+{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup }, { C_F, C_CC }},
+
+/* neg<.f> a,limm 0010011001001110F111000000AAAAAA.  */
+{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM }, { C_F }},
+
+/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ.  */
+{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F, C_CC }},
+
+/* negs<.f> b,c 00101bbb00101111FBBBCCCCCC000111.  */
+{ "negs", 0x282F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* negs<.f> 0,c 0010111000101111F111CCCCCC000111.  */
+{ "negs", 0x2E2F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* negs<.f> b,u6 00101bbb01101111FBBBuuuuuu000111.  */
+{ "negs", 0x286F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* negs<.f> 0,u6 0010111001101111F111uuuuuu000111.  */
+{ "negs", 0x2E6F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* negs<.f> b,limm 00101bbb00101111FBBB111110000111.  */
+{ "negs", 0x282F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* negs<.f> 0,limm 0010111000101111F111111110000111.  */
+{ "negs", 0x2E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* negsh<.f> b,c 00101bbb00101111FBBBCCCCCC000110.  */
+{ "negsh", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }},
+
+/* negsh<.f> 0,c 0010111000101111F111CCCCCC000110.  */
+{ "negsh", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* negsh<.f> b,u6 00101bbb01101111FBBBuuuuuu000110.  */
+{ "negsh", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* negsh<.f> 0,u6 0010111001101111F111uuuuuu000110.  */
+{ "negsh", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* negsh<.f> b,limm 00101bbb00101111FBBB111110000110.  */
+{ "negsh", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }},
+
+/* negsh<.f> 0,limm 0010111000101111F111111110000110.  */
+{ "negsh", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* negsw<.f> b,c 00101bbb00101111FBBBCCCCCC000110.  */
+{ "negsw", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* negsw<.f> 0,c 0010111000101111F111CCCCCC000110.  */
+{ "negsw", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* negsw<.f> b,u6 00101bbb01101111FBBBuuuuuu000110.  */
+{ "negsw", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* negsw<.f> 0,u6 0010111001101111F111uuuuuu000110.  */
+{ "negsw", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* negsw<.f> b,limm 00101bbb00101111FBBB111110000110.  */
+{ "negsw", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* negsw<.f> 0,limm 0010111000101111F111111110000110.  */
+{ "negsw", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* neg_s b,c 01111bbbccc10011.  */
+{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* nop  00100110010010100111000000000000.  */
+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+
+/* nop_s  0111100011100000.  */
+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+
+/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001.  */
+{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* norm<.f> 0,c 0010111000101111F111CCCCCC000001.  */
+{ "norm", 0x2E2F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001.  */
+{ "norm", 0x286F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001.  */
+{ "norm", 0x2E6F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* norm<.f> b,limm 00101bbb00101111FBBB111110000001.  */
+{ "norm", 0x282F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* norm<.f> 0,limm 0010111000101111F111111110000001.  */
+{ "norm", 0x2E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* normacc b,c 00101bbb001011110BBBCCCCCC011001.  */
+{ "normacc", 0x282F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* normacc 0,c 00101110001011110111CCCCCC011001.  */
+{ "normacc", 0x2E2F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* normacc b,u6 00101bbb011011110BBBuuuuuu011001.  */
+{ "normacc", 0x286F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* normacc 0,u6 00101110011011110111uuuuuu011001.  */
+{ "normacc", 0x2E6F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* normacc b,limm 00101bbb001011110BBB111110011001.  */
+{ "normacc", 0x282F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* normacc 0,limm 00101110001011110111111110011001.  */
+{ "normacc", 0x2E2F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000.  */
+{ "normh", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* normh<.f> 0,c 0010111000101111F111CCCCCC001000.  */
+{ "normh", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000.  */
+{ "normh", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000.  */
+{ "normh", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* normh<.f> b,limm 00101bbb00101111FBBB111110001000.  */
+{ "normh", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* normh<.f> 0,limm 0010111000101111F111111110001000.  */
+{ "normh", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* normw<.f> b,c 00101bbb00101111FBBBCCCCCC001000.  */
+{ "normw", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* normw<.f> 0,c 0010111000101111F111CCCCCC001000.  */
+{ "normw", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* normw<.f> b,u6 00101bbb01101111FBBBuuuuuu001000.  */
+{ "normw", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* normw<.f> 0,u6 0010111001101111F111uuuuuu001000.  */
+{ "normw", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* normw<.f> b,limm 00101bbb00101111FBBB111110001000.  */
+{ "normw", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* normw<.f> 0,limm 0010111000101111F111111110001000.  */
+{ "normw", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010.  */
+{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* not<.f> 0,c 0010011000101111F111CCCCCC001010.  */
+{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010.  */
+{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* not<.f> 0,u6 0010011001101111F111uuuuuu001010.  */
+{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* not<.f> b,limm 00100bbb00101111FBBB111110001010.  */
+{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* not<.f> 0,limm 0010011000101111F111111110001010.  */
+{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* not_s b,c 01111bbbccc10010.  */
+{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA.  */
+{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110.  */
+{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ.  */
+{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA.  */
+{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110.  */
+{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ.  */
+{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS.  */
+{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA.  */
+{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA.  */
+{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110.  */
+{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110.  */
+{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ.  */
+{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ.  */
+{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA.  */
+{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110.  */
+{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ.  */
+{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS.  */
+{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA.  */
+{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* or<.f> 0,limm,limm 0010011000000101F111111110111110.  */
+{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ.  */
+{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* or_s b,b,c 01111bbbccc00101.  */
+{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* pkqb<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA.  */
+{ "pkqb", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* pkqb<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ.  */
+{ "pkqb", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* pkqb<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA.  */
+{ "pkqb", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* pkqb<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ.  */
+{ "pkqb", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* pkqb<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS.  */
+{ "pkqb", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* pkqb<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA.  */
+{ "pkqb", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* pkqb<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA.  */
+{ "pkqb", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* pkqb<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ.  */
+{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* pop_s b 11000bbb11000001.  */
+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }},
+
+/* pop_s BLINK 11000RRR11010001.  */
+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }},
+
+/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110.  */
+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110.  */
+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110.  */
+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prealloc limm,c 00100110RR1100010111CCCCCC111110.  */
+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prealloc limm 000101100000000001110RR001111110.  */
+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prealloc limm,s9 00010110ssssssssS1110RR001111110.  */
+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110.  */
+{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetch b 00010bbb000000000BBB0RR000111110.  */
+{ "prefetch", 0x1000003E, 0xF8FF89FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { BRAKET, RB, BRAKETdup }, { 0 }},
+
+/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110.  */
+{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110.  */
+{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prefetch<.aa> limm,c 00100110aa1100000111CCCCCC111110.  */
+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetch limm,c 00100110RR1100000111CCCCCC111110.  */
+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prefetch limm 000101100000000001110RR000111110.  */
+{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prefetch<.aa> limm,s9 00010110ssssssssS1110aa000111110.  */
+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetch limm,s9 00010110ssssssssS1110RR000111110.  */
+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* prefetch<.aa> limm,limm 00100110aa1100000111111110111110.  */
+{ "prefetch", 0x26307FBE, 0xFF3FFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_AA8 }},
+
+/* prefetchl2<.aa> b,c 00100bbbaa1100100BBBCCCCCC111110.  */
+{ "prefetchl2", 0x2032003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_AA8 }},
+
+/* prefetchl2 b 00010bbb000000000BBB0RR000111110.  */
+{ "prefetchl2", 0x1000003E, 0xF8FF89FF, 0, MEMORY, NONE, { RB }, { 0 }},
+
+/* prefetchl2<.aa> b,s9 00010bbbssssssssSBBB0aa010111110.  */
+{ "prefetchl2", 0x100000BE, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, SIMM9_8 }, { C_AA21 }},
+
+/* prefetchl2<.aa> b,limm 00100bbbaa1100100BBB111110111110.  */
+{ "prefetchl2", 0x20320FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_AA8 }},
+
+/* prefetchl2<.aa> limm,c 00100110aa1100000111CCCCCC111110.  */
+{ "prefetchl2", 0x2630703E, 0xFF3FF03F, 0, MEMORY, NONE, { LIMM, RC }, { C_AA8 }},
+
+/* prefetchl2 limm,c 00100110RR1100100111CCCCCC111110.  */
+{ "prefetchl2", 0x2632703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, RC }, { 0 }},
+
+/* prefetchl2 limm 000101100000000001110RR010111110.  */
+{ "prefetchl2", 0x160070BE, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM }, { 0 }},
+
+/* prefetchl2<.aa> limm,s9 00010110ssssssssS1110aa000111110.  */
+{ "prefetchl2", 0x1600703E, 0xFF0079FF, 0, MEMORY, NONE, { LIMM, SIMM9_8 }, { C_AA21 }},
+
+/* prefetchl2 limm,s9 00010110ssssssssS1110RR010111110.  */
+{ "prefetchl2", 0x160070BE, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, SIMM9_8 }, { 0 }},
+
+/* prefetchl2<.aa> limm,limm 00100110aa1100000111111110111110.  */
+{ "prefetchl2", 0x26307FBE, 0xFF3FFFFF, 0, MEMORY, NONE, { LIMM, LIMMdup }, { C_AA8 }},
+
+/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110.  */
+{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110.  */
+{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110.  */
+{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prefetchw limm,c 00100110RR1100001111CCCCCC111110.  */
+{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prefetchw limm 000101100000000001111RR000111110.  */
+{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prefetchw limm,s9 00010110ssssssssS1111RR000111110.  */
+{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* push_s b 11000bbb11100001.  */
+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }},
+
+/* push_s blink 11000RRR11110001.  */
+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }},
+
+/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA.  */
+{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110.  */
+{ "qmach", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ.  */
+{ "qmach", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA.  */
+{ "qmach", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110.  */
+{ "qmach", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ.  */
+{ "qmach", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS.  */
+{ "qmach", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA.  */
+{ "qmach", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA.  */
+{ "qmach", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110.  */
+{ "qmach", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110.  */
+{ "qmach", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ.  */
+{ "qmach", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ.  */
+{ "qmach", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA.  */
+{ "qmach", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110.  */
+{ "qmach", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ.  */
+{ "qmach", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS.  */
+{ "qmach", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA.  */
+{ "qmach", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110.  */
+{ "qmach", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ.  */
+{ "qmach", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA.  */
+{ "qmachu", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110.  */
+{ "qmachu", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ.  */
+{ "qmachu", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA.  */
+{ "qmachu", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110.  */
+{ "qmachu", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ.  */
+{ "qmachu", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS.  */
+{ "qmachu", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA.  */
+{ "qmachu", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA.  */
+{ "qmachu", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110.  */
+{ "qmachu", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110.  */
+{ "qmachu", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ.  */
+{ "qmachu", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ.  */
+{ "qmachu", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA.  */
+{ "qmachu", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110.  */
+{ "qmachu", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ.  */
+{ "qmachu", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS.  */
+{ "qmachu", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA.  */
+{ "qmachu", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110.  */
+{ "qmachu", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ.  */
+{ "qmachu", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA.  */
+{ "qmpyh", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110.  */
+{ "qmpyh", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ.  */
+{ "qmpyh", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA.  */
+{ "qmpyh", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110.  */
+{ "qmpyh", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ.  */
+{ "qmpyh", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS.  */
+{ "qmpyh", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA.  */
+{ "qmpyh", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA.  */
+{ "qmpyh", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110.  */
+{ "qmpyh", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110.  */
+{ "qmpyh", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ.  */
+{ "qmpyh", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ.  */
+{ "qmpyh", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA.  */
+{ "qmpyh", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110.  */
+{ "qmpyh", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ.  */
+{ "qmpyh", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS.  */
+{ "qmpyh", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA.  */
+{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110.  */
+{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ.  */
+{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA.  */
+{ "qmpyhu", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }},
+
+/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110.  */
+{ "qmpyhu", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ.  */
+{ "qmpyhu", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA.  */
+{ "qmpyhu", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110.  */
+{ "qmpyhu", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ.  */
+{ "qmpyhu", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS.  */
+{ "qmpyhu", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA.  */
+{ "qmpyhu", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }},
+
+/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA.  */
+{ "qmpyhu", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110.  */
+{ "qmpyhu", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110.  */
+{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ.  */
+{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ.  */
+{ "qmpyhu", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA.  */
+{ "qmpyhu", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110.  */
+{ "qmpyhu", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ.  */
+{ "qmpyhu", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS.  */
+{ "qmpyhu", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA.  */
+{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110.  */
+{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ.  */
+{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR.  */
+{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* rcmp b,c 00100bbb000011011BBBCCCCCC000000.  */
+{ "rcmp", 0x200D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ.  */
+{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR.  */
+{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rcmp b,u6 00100bbb010011011BBBuuuuuu000000.  */
+{ "rcmp", 0x204D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ.  */
+{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS.  */
+{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR.  */
+{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR.  */
+{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* rcmp limm,c 00100110000011011111CCCCCC000000.  */
+{ "rcmp", 0x260DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* rcmp b,limm 00100bbb000011011BBB111110000000.  */
+{ "rcmp", 0x200D8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ.  */
+{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ.  */
+{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR.  */
+{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* rcmp limm,u6 00100110010011011111uuuuuu000000.  */
+{ "rcmp", 0x264DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ.  */
+{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* rcmp limm,s12 00100110100011011111ssssssSSSSSS.  */
+{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* rcmp limm,limm 00100110000011011111111110RRRRRR.  */
+{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* rcmp limm,limm 00100110000011011111111110000000.  */
+{ "rcmp", 0x260DFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ.  */
+{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA.  */
+{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }},
+
+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110.  */
+{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }},
+
+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ.  */
+{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA.  */
+{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110.  */
+{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ.  */
+{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS.  */
+{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA.  */
+{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }},
+
+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA.  */
+{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }},
+
+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110.  */
+{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110.  */
+{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ.  */
+{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ.  */
+{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA.  */
+{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110.  */
+{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ.  */
+{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS.  */
+{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA.  */
+{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110.  */
+{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ.  */
+{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA.  */
+{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }},
+
+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110.  */
+{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }},
+
+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ.  */
+{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA.  */
+{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110.  */
+{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ.  */
+{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS.  */
+{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA.  */
+{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }},
+
+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA.  */
+{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }},
+
+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110.  */
+{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110.  */
+{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ.  */
+{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ.  */
+{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA.  */
+{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110.  */
+{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ.  */
+{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS.  */
+{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA.  */
+{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110.  */
+{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ.  */
+{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011.  */
+{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011.  */
+{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011.  */
+{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011.  */
+{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011.  */
+{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rlc<.f> 0,limm 0010011000101111F111111110001011.  */
+{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rnd16<.f> b,c 00101bbb00101111FBBBCCCCCC000011.  */
+{ "rnd16", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* rnd16<.f> 0,c 0010111000101111F111CCCCCC000011.  */
+{ "rnd16", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* rnd16<.f> b,u6 00101bbb01101111FBBBuuuuuu000011.  */
+{ "rnd16", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rnd16<.f> 0,u6 0010111001101111F111uuuuuu000011.  */
+{ "rnd16", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rnd16<.f> b,limm 00101bbb00101111FBBB111110000011.  */
+{ "rnd16", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* rnd16<.f> 0,limm 0010111000101111F111111110000011.  */
+{ "rnd16", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* rndh<.f> b,c 00101bbb00101111FBBBCCCCCC000011.  */
+{ "rndh", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }},
+
+/* rndh<.f> 0,c 0010111000101111F111CCCCCC000011.  */
+{ "rndh", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* rndh<.f> b,u6 00101bbb01101111FBBBuuuuuu000011.  */
+{ "rndh", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rndh<.f> 0,u6 0010111001101111F111uuuuuu000011.  */
+{ "rndh", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rndh<.f> b,limm 00101bbb00101111FBBB111110000011.  */
+{ "rndh", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }},
+
+/* rndh<.f> 0,limm 0010111000101111F111111110000011.  */
+{ "rndh", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101.  */
+{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rol<.f> 0,c 0010011000101111F111CCCCCC001101.  */
+{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101.  */
+{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101.  */
+{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rol<.f> b,limm 00100bbb00101111FBBB111110001101.  */
+{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rol<.f> 0,limm 0010011000101111F111111110001101.  */
+{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000.  */
+{ "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, RC }, { C_F }},
+
+/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000.  */
+{ "rol8", 0x2E2F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, RC }, { C_F }},
+
+/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000.  */
+{ "rol8", 0x286F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000.  */
+{ "rol8", 0x2E6F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000.  */
+{ "rol8", 0x282F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, LIMM }, { C_F }},
+
+/* rol8<.f> 0,limm 0010111000101111F111111110010000.  */
+{ "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011.  */
+{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* ror<.f> 0,c 0010011000101111F111CCCCCC000011.  */
+{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA.  */
+{ "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110.  */
+{ "ror", 0x2803003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ.  */
+{ "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011.  */
+{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011.  */
+{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA.  */
+{ "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110.  */
+{ "ror", 0x2843003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ.  */
+{ "ror", 0x28C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS.  */
+{ "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* ror<.f> b,limm 00100bbb00101111FBBB111110000011.  */
+{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* ror<.f> 0,limm 0010011000101111F111111110000011.  */
+{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA.  */
+{ "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA.  */
+{ "ror", 0x28030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110.  */
+{ "ror", 0x2E03703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110.  */
+{ "ror", 0x28030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ.  */
+{ "ror", 0x28C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ.  */
+{ "ror", 0x2EC37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA.  */
+{ "ror", 0x2E437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110.  */
+{ "ror", 0x2E43703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ.  */
+{ "ror", 0x2EC37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS.  */
+{ "ror", 0x2E837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA.  */
+{ "ror", 0x2E037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* ror<.f> 0,limm,limm 0010111000000011F111111110111110.  */
+{ "ror", 0x2E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ.  */
+{ "ror", 0x2EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001.  */
+{ "ror8", 0x282F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, RC }, { C_F }},
+
+/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001.  */
+{ "ror8", 0x2E2F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, RC }, { C_F }},
+
+/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001.  */
+{ "ror8", 0x286F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001.  */
+{ "ror8", 0x2E6F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001.  */
+{ "ror8", 0x282F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, LIMM }, { C_F }},
+
+/* ror8<.f> 0,limm 0010111000101111F111111110010001.  */
+{ "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100.  */
+{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100.  */
+{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100.  */
+{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100.  */
+{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100.  */
+{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rrc<.f> 0,limm 0010011000101111F111111110000100.  */
+{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA.  */
+{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110.  */
+{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ.  */
+{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA.  */
+{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110.  */
+{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ.  */
+{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS.  */
+{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA.  */
+{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA.  */
+{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110.  */
+{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110.  */
+{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ.  */
+{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ.  */
+{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA.  */
+{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110.  */
+{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ.  */
+{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS.  */
+{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA.  */
+{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110.  */
+{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ.  */
+{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rtie  00100100011011110000000000111111.  */
+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+
+/* rtsc b,0 00110bbb01101111RBBB000000011010.  */
+{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, ZB }, { 0 }},
+
+/* rtsc 0,0 0011011001101111R111000000011010.  */
+{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, ZB }, { 0 }},
+
+/* rtsc b,c 00110bbb00101111RBBBCCCCCC011010.  */
+{ "rtsc", 0x302F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, RC }, { 0 }},
+
+/* rtsc 0,c 0011011000101111R111CCCCCC011010.  */
+{ "rtsc", 0x362F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, RC }, { 0 }},
+
+/* rtsc b,u6 00110bbb01101111RBBBuuuuuu011010.  */
+{ "rtsc", 0x306F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rtsc 0,u6 0011011001101111R111uuuuuu011010.  */
+{ "rtsc", 0x366F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* rtsc b,limm 00110bbb00101111RBBB111110011010.  */
+{ "rtsc", 0x302F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, LIMM }, { 0 }},
+
+/* rtsc 0,limm 0011011000101111R111111110011010.  */
+{ "rtsc", 0x362F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, LIMM }, { 0 }},
+
+/* sat16<.f> b,c 00101bbb00101111FBBBCCCCCC000010.  */
+{ "sat16", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sat16<.f> 0,c 0010111000101111F111CCCCCC000010.  */
+{ "sat16", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sat16<.f> b,u6 00101bbb01101111FBBBuuuuuu000010.  */
+{ "sat16", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sat16<.f> 0,u6 0010111001101111F111uuuuuu000010.  */
+{ "sat16", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sat16<.f> b,limm 00101bbb00101111FBBB111110000010.  */
+{ "sat16", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sat16<.f> 0,limm 0010111000101111F111111110000010.  */
+{ "sat16", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sath<.f> b,c 00101bbb00101111FBBBCCCCCC000010.  */
+{ "sath", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }},
+
+/* sath<.f> 0,c 0010111000101111F111CCCCCC000010.  */
+{ "sath", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* sath<.f> b,u6 00101bbb01101111FBBBuuuuuu000010.  */
+{ "sath", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sath<.f> 0,u6 0010111001101111F111uuuuuu000010.  */
+{ "sath", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sath<.f> b,limm 00101bbb00101111FBBB111110000010.  */
+{ "sath", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }},
+
+/* sath<.f> 0,limm 0010111000101111F111111110000010.  */
+{ "sath", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA.  */
+{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110.  */
+{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ.  */
+{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA.  */
+{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110.  */
+{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ.  */
+{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS.  */
+{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA.  */
+{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA.  */
+{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110.  */
+{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110.  */
+{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ.  */
+{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ.  */
+{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA.  */
+{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110.  */
+{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ.  */
+{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS.  */
+{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA.  */
+{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110.  */
+{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ.  */
+{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001.  */
+{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001.  */
+{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> b,limm 00100bbb00101111DBBB111110010001.  */
+{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> limm,c 0010011000101111D111CCCCCC010001.  */
+{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> limm,u6 0010011001101111D111uuuuuu010001.  */
+{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> limm,limm 0010011000101111D111111110010001.  */
+{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
+
+/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011.  */
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_DI16 }},
+
+/* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011.  */
+{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_DI16 }},
+
+/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011.  */
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_DI16 }},
+
+/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA.  */
+{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* setacc 0,b,c 00101bbb000011011BBBCCCCCC111110.  */
+{ "setacc", 0x280D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* setacc<.cc> b,b,c 00101bbb110011011BBBCCCCCC0QQQQQ.  */
+{ "setacc", 0x28CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* setacc a,b,u6 00101bbb010011011BBBuuuuuuAAAAAA.  */
+{ "setacc", 0x284D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* setacc 0,b,u6 00101bbb010011011BBBuuuuuu111110.  */
+{ "setacc", 0x284D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* setacc<.cc> b,b,u6 00101bbb110011011BBBuuuuuu1QQQQQ.  */
+{ "setacc", 0x28CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* setacc b,b,s12 00101bbb100011011BBBssssssSSSSSS.  */
+{ "setacc", 0x288D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* setacc a,limm,c 00101110000011011111CCCCCCAAAAAA.  */
+{ "setacc", 0x2E0DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* setacc a,b,limm 00101bbb000011011BBB111110AAAAAA.  */
+{ "setacc", 0x280D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* setacc 0,limm,c 00101110000011011111CCCCCC111110.  */
+{ "setacc", 0x2E0DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* setacc 0,b,limm 00101bbb000011011BBB111110111110.  */
+{ "setacc", 0x280D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* setacc<.cc> b,b,limm 00101bbb110011011BBB1111100QQQQQ.  */
+{ "setacc", 0x28CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* setacc<.cc> 0,limm,c 00101110110011011111CCCCCC0QQQQQ.  */
+{ "setacc", 0x2ECDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* setacc a,limm,u6 00101110010011011111uuuuuuAAAAAA.  */
+{ "setacc", 0x2E4DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* setacc 0,limm,u6 00101110010011011111uuuuuu111110.  */
+{ "setacc", 0x2E4DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* setacc<.cc> 0,limm,u6 00101110110011011111uuuuuu1QQQQQ.  */
+{ "setacc", 0x2ECDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* setacc 0,limm,s12 00101110100011011111ssssssSSSSSS.  */
+{ "setacc", 0x2E8DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* setacc a,limm,limm 00101110000011011111111110AAAAAA.  */
+{ "setacc", 0x2E0DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* setacc 0,limm,limm 00101110000011011111111110111110.  */
+{ "setacc", 0x2E0DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* setacc<.cc> 0,limm,limm 001011101100110111111111100QQQQQ.  */
+{ "setacc", 0x2ECDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA.  */
+{ "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110.  */
+{ "seteq", 0x2038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ.  */
+{ "seteq", 0x20F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA.  */
+{ "seteq", 0x20780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110.  */
+{ "seteq", 0x2078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ.  */
+{ "seteq", 0x20F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS.  */
+{ "seteq", 0x20B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA.  */
+{ "seteq", 0x26387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA.  */
+{ "seteq", 0x20380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110.  */
+{ "seteq", 0x2638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110.  */
+{ "seteq", 0x20380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ.  */
+{ "seteq", 0x20F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ.  */
+{ "seteq", 0x26F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA.  */
+{ "seteq", 0x26787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110.  */
+{ "seteq", 0x2678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ.  */
+{ "seteq", 0x26F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS.  */
+{ "seteq", 0x26B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA.  */
+{ "seteq", 0x26387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110.  */
+{ "seteq", 0x26387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ.  */
+{ "seteq", 0x26F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA.  */
+{ "setge", 0x203B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110.  */
+{ "setge", 0x203B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ.  */
+{ "setge", 0x20FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA.  */
+{ "setge", 0x207B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110.  */
+{ "setge", 0x207B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ.  */
+{ "setge", 0x20FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS.  */
+{ "setge", 0x20BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA.  */
+{ "setge", 0x263B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA.  */
+{ "setge", 0x203B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110.  */
+{ "setge", 0x263B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110.  */
+{ "setge", 0x203B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ.  */
+{ "setge", 0x20FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ.  */
+{ "setge", 0x26FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA.  */
+{ "setge", 0x267B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110.  */
+{ "setge", 0x267B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ.  */
+{ "setge", 0x26FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS.  */
+{ "setge", 0x26BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA.  */
+{ "setge", 0x263B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setge<.f> 0,limm,limm 0010011000111011F111111110111110.  */
+{ "setge", 0x263B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ.  */
+{ "setge", 0x26FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA.  */
+{ "setgt", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110.  */
+{ "setgt", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ.  */
+{ "setgt", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA.  */
+{ "setgt", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110.  */
+{ "setgt", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ.  */
+{ "setgt", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS.  */
+{ "setgt", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA.  */
+{ "setgt", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA.  */
+{ "setgt", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110.  */
+{ "setgt", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110.  */
+{ "setgt", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ.  */
+{ "setgt", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ.  */
+{ "setgt", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA.  */
+{ "setgt", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110.  */
+{ "setgt", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ.  */
+{ "setgt", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS.  */
+{ "setgt", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA.  */
+{ "setgt", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110.  */
+{ "setgt", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ.  */
+{ "setgt", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA.  */
+{ "seths", 0x203D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110.  */
+{ "seths", 0x203D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ.  */
+{ "seths", 0x20FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA.  */
+{ "seths", 0x207D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110.  */
+{ "seths", 0x207D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ.  */
+{ "seths", 0x20FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS.  */
+{ "seths", 0x20BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA.  */
+{ "seths", 0x263D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA.  */
+{ "seths", 0x203D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110.  */
+{ "seths", 0x263D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110.  */
+{ "seths", 0x203D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ.  */
+{ "seths", 0x20FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ.  */
+{ "seths", 0x26FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA.  */
+{ "seths", 0x267D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110.  */
+{ "seths", 0x267D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ.  */
+{ "seths", 0x26FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS.  */
+{ "seths", 0x26BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA.  */
+{ "seths", 0x263D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seths<.f> 0,limm,limm 0010011000111101F111111110111110.  */
+{ "seths", 0x263D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ.  */
+{ "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seti c 00100110001011110000CCCCCC111111.  */
+{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
+
+/* seti u6 00100110011011110000uuuuuu111111.  */
+{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* seti limm 00100110001011110000111110111111.  */
+{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA.  */
+{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110.  */
+{ "setle", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ.  */
+{ "setle", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA.  */
+{ "setle", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110.  */
+{ "setle", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ.  */
+{ "setle", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS.  */
+{ "setle", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA.  */
+{ "setle", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA.  */
+{ "setle", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110.  */
+{ "setle", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110.  */
+{ "setle", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ.  */
+{ "setle", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ.  */
+{ "setle", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA.  */
+{ "setle", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110.  */
+{ "setle", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ.  */
+{ "setle", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS.  */
+{ "setle", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA.  */
+{ "setle", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setle<.f> 0,limm,limm 0010011000111110F111111110111110.  */
+{ "setle", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ.  */
+{ "setle", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA.  */
+{ "setlo", 0x203C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110.  */
+{ "setlo", 0x203C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ.  */
+{ "setlo", 0x20FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA.  */
+{ "setlo", 0x207C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110.  */
+{ "setlo", 0x207C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ.  */
+{ "setlo", 0x20FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS.  */
+{ "setlo", 0x20BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA.  */
+{ "setlo", 0x263C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA.  */
+{ "setlo", 0x203C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110.  */
+{ "setlo", 0x263C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110.  */
+{ "setlo", 0x203C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ.  */
+{ "setlo", 0x20FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ.  */
+{ "setlo", 0x26FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA.  */
+{ "setlo", 0x267C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110.  */
+{ "setlo", 0x267C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ.  */
+{ "setlo", 0x26FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS.  */
+{ "setlo", 0x26BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA.  */
+{ "setlo", 0x263C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110.  */
+{ "setlo", 0x263C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ.  */
+{ "setlo", 0x26FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA.  */
+{ "setlt", 0x203A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110.  */
+{ "setlt", 0x203A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ.  */
+{ "setlt", 0x20FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA.  */
+{ "setlt", 0x207A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110.  */
+{ "setlt", 0x207A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ.  */
+{ "setlt", 0x20FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS.  */
+{ "setlt", 0x20BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA.  */
+{ "setlt", 0x263A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA.  */
+{ "setlt", 0x203A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110.  */
+{ "setlt", 0x263A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110.  */
+{ "setlt", 0x203A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ.  */
+{ "setlt", 0x20FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ.  */
+{ "setlt", 0x26FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA.  */
+{ "setlt", 0x267A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110.  */
+{ "setlt", 0x267A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ.  */
+{ "setlt", 0x26FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS.  */
+{ "setlt", 0x26BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA.  */
+{ "setlt", 0x263A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110.  */
+{ "setlt", 0x263A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ.  */
+{ "setlt", 0x26FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA.  */
+{ "setne", 0x20390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110.  */
+{ "setne", 0x2039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ.  */
+{ "setne", 0x20F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA.  */
+{ "setne", 0x20790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110.  */
+{ "setne", 0x2079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ.  */
+{ "setne", 0x20F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS.  */
+{ "setne", 0x20B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA.  */
+{ "setne", 0x26397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA.  */
+{ "setne", 0x20390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110.  */
+{ "setne", 0x2639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110.  */
+{ "setne", 0x20390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ.  */
+{ "setne", 0x20F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ.  */
+{ "setne", 0x26F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA.  */
+{ "setne", 0x26797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110.  */
+{ "setne", 0x2679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ.  */
+{ "setne", 0x26F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS.  */
+{ "setne", 0x26B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA.  */
+{ "setne", 0x26397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setne<.f> 0,limm,limm 0010011000111001F111111110111110.  */
+{ "setne", 0x26397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ.  */
+{ "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setcc<.f> a,b,c 00100bbb00iiiiiiFBBBCCCCCCAAAAAA.  */
+{ "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setcc<.f> 0,b,c 00100bbb00iiiiiiFBBBCCCCCC111110.  */
+{ "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setcc<.f><.cc> b,b,c 00100bbb11iiiiiiFBBBCCCCCC0QQQQQ.  */
+{ "setcc", 0x20C00000, 0xF8C00020, 0, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setcc<.f> a,b,u6 00100bbb01iiiiiiFBBBuuuuuuAAAAAA.  */
+{ "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setcc<.f> 0,b,u6 00100bbb01iiiiiiFBBBuuuuuu111110.  */
+{ "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setcc<.f><.cc> b,b,u6 00100bbb11iiiiiiFBBBuuuuuu1QQQQQ.  */
+{ "setcc", 0x20C00020, 0xF8C00020, 0, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setcc<.f> b,b,s12 00100bbb10iiiiiiFBBBssssssSSSSSS.  */
+{ "setcc", 0x20800000, 0xF8C00000, 0, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setcc<.f> a,limm,c 0010011000iiiiiiF111CCCCCCAAAAAA.  */
+{ "setcc", 0x26007000, 0xFFC07000, 0, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setcc<.f> a,b,limm 00100bbb00iiiiiiFBBB111110AAAAAA.  */
+{ "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setcc<.f> 0,limm,c 0010011000iiiiiiF111CCCCCC111110.  */
+{ "setcc", 0x2600703E, 0xFFC0703F, 0, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setcc<.f> 0,b,limm 00100bbb00iiiiiiFBBB111110111110.  */
+{ "setcc", 0x20000FBE, 0xF8C00FFF, 0, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setcc<.f><.cc> b,b,limm 00100bbb11iiiiiiFBBB1111100QQQQQ.  */
+{ "setcc", 0x20C00F80, 0xF8C00FE0, 0, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setcc<.f><.cc> 0,limm,c 0010011011iiiiiiF111CCCCCC0QQQQQ.  */
+{ "setcc", 0x26C07000, 0xFFC07020, 0, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setcc<.f> a,limm,u6 0010011001iiiiiiF111uuuuuuAAAAAA.  */
+{ "setcc", 0x26407000, 0xFFC07000, 0, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setcc<.f> 0,limm,u6 0010011001iiiiiiF111uuuuuu111110.  */
+{ "setcc", 0x2640703E, 0xFFC0703F, 0, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setcc<.f><.cc> 0,limm,u6 0010011011iiiiiiF111uuuuuu1QQQQQ.  */
+{ "setcc", 0x26C07020, 0xFFC07020, 0, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setcc<.f> 0,limm,s12 0010011010iiiiiiF111ssssssSSSSSS.  */
+{ "setcc", 0x26807000, 0xFFC07000, 0, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setcc<.f> a,limm,limm 0010011000iiiiiiF111111110AAAAAA.  */
+{ "setcc", 0x26007F80, 0xFFC07FC0, 0, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setcc<.f> 0,limm,limm 0010011000iiiiiiF111111110111110.  */
+{ "setcc", 0x26007FBE, 0xFFC07FFF, 0, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setcc<.f><.cc> 0,limm,limm 0010011011iiiiiiF1111111100QQQQQ.  */
+{ "setcc", 0x26C07F80, 0xFFC07FE0, 0, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101.  */
+{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101.  */
+{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101.  */
+{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101.  */
+{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101.  */
+{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexb<.f> 0,limm 0010011000101111F111111110000101.  */
+{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexb_s b,c 01111bbbccc01101.  */
+{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110.  */
+{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110.  */
+{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110.  */
+{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110.  */
+{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110.  */
+{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexh<.f> 0,limm 0010011000101111F111111110000110.  */
+{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexh_s b,c 01111bbbccc01110.  */
+{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sexw<.f> b,c 00100bbb00101111FBBBCCCCCC000110.  */
+{ "sexw", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexw<.f> 0,c 0010011000101111F111CCCCCC000110.  */
+{ "sexw", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexw<.f> b,u6 00100bbb01101111FBBBuuuuuu000110.  */
+{ "sexw", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexw<.f> 0,u6 0010011001101111F111uuuuuu000110.  */
+{ "sexw", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexw<.f> b,limm 00100bbb00101111FBBB111110000110.  */
+{ "sexw", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexw<.f> 0,limm 0010011000101111F111111110000110.  */
+{ "sexw", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexw_s b,c 01111bbbccc01110.  */
+{ "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sfxtr<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA.  */
+{ "sfxtr", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sfxtr<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ.  */
+{ "sfxtr", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sfxtr<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA.  */
+{ "sfxtr", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sfxtr<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ.  */
+{ "sfxtr", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sfxtr<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS.  */
+{ "sfxtr", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sfxtr<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA.  */
+{ "sfxtr", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sfxtr<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA.  */
+{ "sfxtr", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sfxtr<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ.  */
+{ "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sleep c 00100001001011110000CCCCCC111111.  */
+{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }},
+
+/* sleep u6 00100001011011110000uuuuuu111111.  */
+{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* sleep limm 00100001001011110000111110111111.  */
+{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { LIMM }, { 0 }},
+
+/* sqrtacc c 00101010001011110000CCCCCC111111.  */
+{ "sqrtacc", 0x2A2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }},
+
+/* sqrtacc u6 00101010011011110000uuuuuu111111.  */
+{ "sqrtacc", 0x2A6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* sr b,c 00100bbb001010110BBBCCCCCCRRRRRR.  */
+{ "sr", 0x202B0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR.  */
+{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,u6 00100bbb011010110BBBuuuuuu000000.  */
+{ "sr", 0x206B0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr b,u6 00100bbb01101011RBBBuuuuuu000000.  */
+{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr b,s12 00100bbb101010110BBBssssssSSSSSS.  */
+{ "sr", 0x20AB0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS.  */
+{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,c 00100110001010110111CCCCCCRRRRRR.  */
+{ "sr", 0x262B7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,limm 00100bbb001010110BBB111110RRRRRR.  */
+{ "sr", 0x202B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* sr limm,c 0010011000101011R111CCCCCCRRRRRR.  */
+{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,limm 00100bbb00101011RBBB111110RRRRRR.  */
+{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* sr limm,u6 00100110011010110111uuuuuu000000.  */
+{ "sr", 0x266B7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr limm,u6 0010011001101011R111uuuuuu000000.  */
+{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr limm,s12 00100110101010110111ssssssSSSSSS.  */
+{ "sr", 0x26AB7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,s12 0010011010101011R111ssssssSSSSSS.  */
+{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,limm 00100110001010110111111110RRRRRR.  */
+{ "sr", 0x262B7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* sr limm,limm 0010011000101011R111111110RRRRRR.  */
+{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* st<.di><.aa><zz> c,b 00011bbb000000000BBBCCCCCCDaaZZR.  */
+{ "st", 0x18000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> c,b 00011bbb000000000BBBCCCCCCDaaZZ0.  */
+{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1.  */
+{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZR.  */
+{ "st", 0x18000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0.  */
+{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1.  */
+{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><zz> c,limm 00011110000000000111CCCCCCDRRZZR.  */
+{ "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }},
+
+/* st<.di><zz> c,limm 00011110000000000111CCCCCCDRRZZ0.  */
+{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }},
+
+/* st<.di><zz> w6,limm 00011110000000000111wwwwwwDRRZZ1.  */
+{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }},
+
+/* st<.di><.aa><zz> limm,b,s9 00011bbbssssssssSBBB111110DaaZZR.  */
+{ "st", 0x18000F80, 0xF8000FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0.  */
+{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1.  */
+{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> limm,limm,s9 00011110ssssssssS111111110DaaZZR.  */
+{ "st", 0x1E007F80, 0xFF007FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<.di><.aa><zz> limm,limm,s9 00011110ssssssssS111111110DaaZZ0.  */
+{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* stb_s c,b,u5 10101bbbcccuuuuu.  */
+{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }},
+
+/* stb_s b,SP,u7 11000bbb011uuuuu.  */
+{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110.  */
+{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111.  */
+{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110.  */
+{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111.  */
+{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.di> c,limm 00011110000000000111CCCCCCDRR110.  */
+{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26 }},
+
+/* std<.di> w6,limm 00011110000000000111wwwwwwDRR111.  */
+{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26 }},
+
+/* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110.  */
+{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111.  */
+{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110.  */
+{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* sth_s c,b,u6 10110bbbcccuuuuu.  */
+{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
+
+/* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA.  */
+{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, RB }, { 0 }},
+
+/* stm 0,u6,b 00101bbb01001101RBBBRuuuuu111110.  */
+{ "stm", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, RB }, { 0 }},
+
+/* stm a,u6,limm 0010111001001101R111RuuuuuAAAAAA.  */
+{ "stm", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, LIMM }, { 0 }},
+
+/* stm 0,u6,limm 0010111001001101R111Ruuuuu111110.  */
+{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }},
+
+/* stw_s c,b,u6 10110bbbcccuuuuu.  */
+{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
+
+/* st_s b,SP,u7 11000bbb010uuuuu.  */
+{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* st_s c,b,u7 10100bbbcccuuuuu.  */
+{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* st_s R0,GP,s11 01010SSSSSS10sss.  */
+{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
+
+/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA.  */
+{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110.  */
+{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ.  */
+{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.  */
+{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110.  */
+{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ.  */
+{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS.  */
+{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA.  */
+{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA.  */
+{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110.  */
+{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110.  */
+{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ.  */
+{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ.  */
+{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA.  */
+{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110.  */
+{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ.  */
+{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS.  */
+{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA.  */
+{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub<.f> 0,limm,limm 0010011000000010F111111110111110.  */
+{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ.  */
+{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA.  */
+{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110.  */
+{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ.  */
+{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA.  */
+{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110.  */
+{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ.  */
+{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS.  */
+{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA.  */
+{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA.  */
+{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110.  */
+{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110.  */
+{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ.  */
+{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ.  */
+{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA.  */
+{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110.  */
+{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ.  */
+{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS.  */
+{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA.  */
+{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110.  */
+{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ.  */
+{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA.  */
+{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110.  */
+{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ.  */
+{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA.  */
+{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110.  */
+{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ.  */
+{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS.  */
+{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA.  */
+{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA.  */
+{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110.  */
+{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110.  */
+{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ.  */
+{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ.  */
+{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA.  */
+{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110.  */
+{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ.  */
+{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS.  */
+{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA.  */
+{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110.  */
+{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ.  */
+{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA.  */
+{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110.  */
+{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ.  */
+{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA.  */
+{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110.  */
+{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ.  */
+{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS.  */
+{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA.  */
+{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA.  */
+{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110.  */
+{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110.  */
+{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ.  */
+{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ.  */
+{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA.  */
+{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110.  */
+{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ.  */
+{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS.  */
+{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA.  */
+{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110.  */
+{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ.  */
+{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA.  */
+{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* subs<.f> 0,b,c 00101bbb00000111FBBBCCCCCC111110.  */
+{ "subs", 0x2807003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* subs<.f><.cc> b,b,c 00101bbb11000111FBBBCCCCCC0QQQQQ.  */
+{ "subs", 0x28C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* subs<.f> a,b,u6 00101bbb01000111FBBBuuuuuuAAAAAA.  */
+{ "subs", 0x28470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* subs<.f> 0,b,u6 00101bbb01000111FBBBuuuuuu111110.  */
+{ "subs", 0x2847003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* subs<.f><.cc> b,b,u6 00101bbb11000111FBBBuuuuuu1QQQQQ.  */
+{ "subs", 0x28C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* subs<.f> b,b,s12 00101bbb10000111FBBBssssssSSSSSS.  */
+{ "subs", 0x28870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA.  */
+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subs<.f> a,b,limm 00101bbb00000111FBBB111110AAAAAA.  */
+{ "subs", 0x28070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* subs<.f> 0,limm,c 0010111000000111F111CCCCCC111110.  */
+{ "subs", 0x2E07703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* subs<.f> 0,b,limm 00101bbb00000111FBBB111110111110.  */
+{ "subs", 0x28070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA.  */
+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subs<.f><.cc> b,b,limm 00101bbb11000111FBBB1111100QQQQQ.  */
+{ "subs", 0x28C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* subs<.f><.cc> 0,limm,c 0010111011000111F111CCCCCC0QQQQQ.  */
+{ "subs", 0x2EC77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* subs<.f> a,limm,u6 0010111001000111F111uuuuuuAAAAAA.  */
+{ "subs", 0x2E477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subs<.f> 0,limm,u6 0010111001000111F111uuuuuu111110.  */
+{ "subs", 0x2E47703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subs<.f><.cc> 0,limm,u6 0010111011000111F111uuuuuu1QQQQQ.  */
+{ "subs", 0x2EC77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subs<.f> 0,limm,s12 0010111010000111F111ssssssSSSSSS.  */
+{ "subs", 0x2E877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* subs<.f> a,limm,limm 0010111000000111F111111110AAAAAA.  */
+{ "subs", 0x2E077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* subs<.f> 0,limm,limm 0010111000000111F111111110111110.  */
+{ "subs", 0x2E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* subs<.f><.cc> 0,limm,limm 0010111011000111F1111111100QQQQQ.  */
+{ "subs", 0x2EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* subsdw<.f> a,b,c 00101bbb00101001FBBBCCCCCCAAAAAA.  */
+{ "subsdw", 0x28290000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* subsdw<.f> 0,b,c 00101bbb00101001FBBBCCCCCC111110.  */
+{ "subsdw", 0x2829003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* subsdw<.f><.cc> b,b,c 00101bbb11101001FBBBCCCCCC0QQQQQ.  */
+{ "subsdw", 0x28E90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* subsdw<.f> a,b,u6 00101bbb01101001FBBBuuuuuuAAAAAA.  */
+{ "subsdw", 0x28690000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* subsdw<.f> 0,b,u6 00101bbb01101001FBBBuuuuuu111110.  */
+{ "subsdw", 0x2869003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* subsdw<.f><.cc> b,b,u6 00101bbb11101001FBBBuuuuuu1QQQQQ.  */
+{ "subsdw", 0x28E90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* subsdw<.f> b,b,s12 00101bbb10101001FBBBssssssSSSSSS.  */
+{ "subsdw", 0x28A90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* subsdw<.f> a,limm,c 0010111000101001F111CCCCCCAAAAAA.  */
+{ "subsdw", 0x2E297000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subsdw<.f> a,b,limm 00101bbb00101001FBBB111110AAAAAA.  */
+{ "subsdw", 0x28290F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* subsdw<.f> 0,limm,c 0010111000101001F111CCCCCC111110.  */
+{ "subsdw", 0x2E29703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* subsdw<.f> 0,b,limm 00101bbb00101001FBBB111110111110.  */
+{ "subsdw", 0x28290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* subsdw<.f><.cc> b,b,limm 00101bbb11101001FBBB1111100QQQQQ.  */
+{ "subsdw", 0x28E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* subsdw<.f><.cc> 0,limm,c 0010111011101001F111CCCCCC0QQQQQ.  */
+{ "subsdw", 0x2EE97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* subsdw<.f> a,limm,u6 0010111001101001F111uuuuuuAAAAAA.  */
+{ "subsdw", 0x2E697000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subsdw<.f> 0,limm,u6 0010111001101001F111uuuuuu111110.  */
+{ "subsdw", 0x2E69703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subsdw<.f><.cc> 0,limm,u6 0010111011101001F111uuuuuu1QQQQQ.  */
+{ "subsdw", 0x2EE97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subsdw<.f> 0,limm,s12 0010111010101001F111ssssssSSSSSS.  */
+{ "subsdw", 0x2EA97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* subsdw<.f> a,limm,limm 0010111000101001F111111110AAAAAA.  */
+{ "subsdw", 0x2E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* subsdw<.f> 0,limm,limm 0010111000101001F111111110111110.  */
+{ "subsdw", 0x2E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* subsdw<.f><.cc> 0,limm,limm 0010111011101001F1111111100QQQQQ.  */
+{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub_s b,b,c 01111bbbccc00010.  */
+{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* sub_s a,b,c 01001bbbccc10aaa.  */
+{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { RA_S, RB_S, RC_S }, { 0 }},
+
+/* sub_s c,b,u3 01101bbbccc01uuu.  */
+{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* sub_s b,b,u5 10111bbb011uuuuu.  */
+{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* sub_s SP,SP,u7 11000001101uuuuu.  */
+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+
+/* sub_s.ne b,b,b 01111bbb11000000.  */
+{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE }},
+
+/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000.  */
+{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* swap<.f> 0,c 0010111000101111F111CCCCCC000000.  */
+{ "swap", 0x2E2F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000.  */
+{ "swap", 0x286F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000.  */
+{ "swap", 0x2E6F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* swap<.f> b,limm 00101bbb00101111FBBB111110000000.  */
+{ "swap", 0x282F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* swap<.f> 0,limm 0010111000101111F111111110000000.  */
+{ "swap", 0x2E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001.  */
+{ "swape", 0x282F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* swape<.f> 0,c 0010111000101111F111CCCCCC001001.  */
+{ "swape", 0x2E2F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001.  */
+{ "swape", 0x286F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001.  */
+{ "swape", 0x2E6F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* swape<.f> b,limm 00101bbb00101111FBBB111110001001.  */
+{ "swape", 0x282F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* swape<.f> 0,limm 0010111000101111F111111110001001.  */
+{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* swi  00100010011011110000000000111111.  */
+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+
+/* swi_s  0111101011100000.  */
+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+
+/* swi_s u6 01111uuuuuu11111.  */
+{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
+
+/* sync  00100011011011110000000000111111.  */
+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+
+/* trap0  00100010011011110000000000111111.  */
+{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, {  }, { 0 }},
+
+/* trap_s u6 01111uuuuuu11110.  */
+{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
+
+/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR.  */
+{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* tst b,c 00100bbb000010111BBBCCCCCC000000.  */
+{ "tst", 0x200B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ.  */
+{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_CC }},
+
+/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR.  */
+{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* tst b,u6 00100bbb010010111BBBuuuuuu000000.  */
+{ "tst", 0x204B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ.  */
+{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* tst b,s12 00100bbb100010111BBBssssssSSSSSS.  */
+{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* tst limm,c 00100110000010111111CCCCCCRRRRRR.  */
+{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* tst b,limm 00100bbb000010111BBB111110RRRRRR.  */
+{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* tst limm,c 00100110000010111111CCCCCC000000.  */
+{ "tst", 0x260BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* tst b,limm 00100bbb000010111BBB111110000000.  */
+{ "tst", 0x200B8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ.  */
+{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_CC }},
+
+/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ.  */
+{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { C_CC }},
+
+/* tst limm,u6 00100110010010111111uuuuuuRRRRRR.  */
+{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* tst limm,u6 00100110010010111111uuuuuu000000.  */
+{ "tst", 0x264BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ.  */
+{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* tst limm,s12 00100110100010111111ssssssSSSSSS.  */
+{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* tst limm,limm 00100110000010111111111110RRRRRR.  */
+{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* tst limm,limm 00100110000010111111111110000000.  */
+{ "tst", 0x260BFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ.  */
+{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* tst_s b,c 01111bbbccc01011.  */
+{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* unimp_s  0111100111100000.  */
+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+
+/* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA.  */
+{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* upkqb<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ.  */
+{ "upkqb", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* upkqb<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA.  */
+{ "upkqb", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* upkqb<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS.  */
+{ "upkqb", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* upkqb<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA.  */
+{ "upkqb", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* upkqb<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA.  */
+{ "upkqb", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* upkqb<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ.  */
+{ "upkqb", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* vabs2h b,c 00101bbb001011110BBBCCCCCC101000.  */
+{ "vabs2h", 0x282F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vabs2h 0,c 00101110001011110111CCCCCC101000.  */
+{ "vabs2h", 0x2E2F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vabs2h b,u6 00101bbb011011110BBBuuuuuu101000.  */
+{ "vabs2h", 0x286F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vabs2h 0,u6 00101110011011110111uuuuuu101000.  */
+{ "vabs2h", 0x2E6F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vabs2h b,limm 00101bbb001011110BBB111110101000.  */
+{ "vabs2h", 0x282F0FA8, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vabs2h 0,limm 00101110001011110111111110101000.  */
+{ "vabs2h", 0x2E2F7FA8, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vabss2h b,c 00101bbb001011110BBBCCCCCC101001.  */
+{ "vabss2h", 0x282F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vabss2h 0,c 00101110001011110111CCCCCC101001.  */
+{ "vabss2h", 0x2E2F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vabss2h b,u6 00101bbb011011110BBBuuuuuu101001.  */
+{ "vabss2h", 0x286F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vabss2h 0,u6 00101110011011110111uuuuuu101001.  */
+{ "vabss2h", 0x2E6F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vabss2h b,limm 00101bbb001011110BBB111110101001.  */
+{ "vabss2h", 0x282F0FA9, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vabss2h 0,limm 00101110001011110111111110101001.  */
+{ "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA.  */
+{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110.  */
+{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ.  */
+{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA.  */
+{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110.  */
+{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ.  */
+{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS.  */
+{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA.  */
+{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA.  */
+{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vadd2 0,limm,c 00101110001111000111CCCCCC111110.  */
+{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd2 0,b,limm 00101bbb001111000BBB111110111110.  */
+{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ.  */
+{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ.  */
+{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA.  */
+{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110.  */
+{ "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ.  */
+{ "vadd2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS.  */
+{ "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA.  */
+{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2 0,limm,limm 00101110001111000111111110111110.  */
+{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ.  */
+{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA.  */
+{ "vadd2h", 0x28140000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }},
+
+/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110.  */
+{ "vadd2h", 0x2814003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ.  */
+{ "vadd2h", 0x28D40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }},
+
+/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA.  */
+{ "vadd2h", 0x28540000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110.  */
+{ "vadd2h", 0x2854003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ.  */
+{ "vadd2h", 0x28D40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS.  */
+{ "vadd2h", 0x28940000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA.  */
+{ "vadd2h", 0x2E147000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }},
+
+/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA.  */
+{ "vadd2h", 0x28140F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }},
+
+/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110.  */
+{ "vadd2h", 0x2E14703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110.  */
+{ "vadd2h", 0x28140FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ.  */
+{ "vadd2h", 0x28D40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ.  */
+{ "vadd2h", 0x2ED47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA.  */
+{ "vadd2h", 0x2E547000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110.  */
+{ "vadd2h", 0x2E54703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ.  */
+{ "vadd2h", 0x2ED47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS.  */
+{ "vadd2h", 0x2E947000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA.  */
+{ "vadd2h", 0x2E147F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2h 0,limm,limm 00101110000101000111111110111110.  */
+{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ.  */
+{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd4b a,b,c 00101bbb001001000BBBCCCCCCAAAAAA.  */
+{ "vadd4b", 0x28240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vadd4b 0,b,c 00101bbb001001000BBBCCCCCC111110.  */
+{ "vadd4b", 0x2824003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vadd4b<.cc> b,b,c 00101bbb111001000BBBCCCCCC0QQQQQ.  */
+{ "vadd4b", 0x28E40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vadd4b a,b,u6 00101bbb011001000BBBuuuuuuAAAAAA.  */
+{ "vadd4b", 0x28640000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4b 0,b,u6 00101bbb011001000BBBuuuuuu111110.  */
+{ "vadd4b", 0x2864003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4b<.cc> b,b,u6 00101bbb111001000BBBuuuuuu1QQQQQ.  */
+{ "vadd4b", 0x28E40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd4b b,b,s12 00101bbb101001000BBBssssssSSSSSS.  */
+{ "vadd4b", 0x28A40000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd4b a,limm,c 00101110001001000111CCCCCCAAAAAA.  */
+{ "vadd4b", 0x2E247000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vadd4b a,b,limm 00101bbb001001000BBB111110AAAAAA.  */
+{ "vadd4b", 0x28240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vadd4b 0,limm,c 00101110011001000111CCCCCC111110.  */
+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd4b 0,b,limm 00101bbb001001000BBB111110111110.  */
+{ "vadd4b", 0x28240FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd4b<.cc> b,b,limm 00101bbb111001000BBB1111100QQQQQ.  */
+{ "vadd4b", 0x28E40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vadd4b<.cc> 0,limm,c 00101110111001000111CCCCCC0QQQQQ.  */
+{ "vadd4b", 0x2EE47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd4b a,limm,u6 00101110011001000111uuuuuuAAAAAA.  */
+{ "vadd4b", 0x2E647000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4b 0,limm,u6 00101110011001000111uuuuuu111110.  */
+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4b<.cc> 0,limm,u6 00101110111001000111uuuuuu1QQQQQ.  */
+{ "vadd4b", 0x2EE47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd4b 0,limm,s12 00101110101001000111ssssssSSSSSS.  */
+{ "vadd4b", 0x2EA47000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd4b a,limm,limm 00101110001001000111111110AAAAAA.  */
+{ "vadd4b", 0x2E247F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4b 0,limm,limm 00101110001001000111111110111110.  */
+{ "vadd4b", 0x2E247FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4b<.cc> 0,limm,limm 001011101110010001111111100QQQQQ.  */
+{ "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA.  */
+{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110.  */
+{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ.  */
+{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA.  */
+{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110.  */
+{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ.  */
+{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS.  */
+{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA.  */
+{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA.  */
+{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110.  */
+{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110.  */
+{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ.  */
+{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ.  */
+{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA.  */
+{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110.  */
+{ "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ.  */
+{ "vadd4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS.  */
+{ "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA.  */
+{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4h 0,limm,limm 00101110001110000111111110111110.  */
+{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ.  */
+{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadds2h a,b,c 00101bbb000101001BBBCCCCCCAAAAAA.  */
+{ "vadds2h", 0x28148000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vadds2h 0,b,c 00101bbb000101001BBBCCCCCC111110.  */
+{ "vadds2h", 0x2814803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vadds2h<.cc> b,b,c 00101bbb110101001BBBCCCCCC0QQQQQ.  */
+{ "vadds2h", 0x28D48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vadds2h a,b,u6 00101bbb010101001BBBuuuuuuAAAAAA.  */
+{ "vadds2h", 0x28548000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vadds2h 0,b,u6 00101bbb010101001BBBuuuuuu111110.  */
+{ "vadds2h", 0x2854803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadds2h<.cc> b,b,u6 00101bbb110101001BBBuuuuuu1QQQQQ.  */
+{ "vadds2h", 0x28D48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadds2h b,b,s12 00101bbb100101001BBBssssssSSSSSS.  */
+{ "vadds2h", 0x28948000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadds2h a,limm,c 00101110000101001111CCCCCCAAAAAA.  */
+{ "vadds2h", 0x2E14F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vadds2h a,b,limm 00101bbb000101001BBB111110AAAAAA.  */
+{ "vadds2h", 0x28148F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vadds2h 0,limm,c 00101110000101001111CCCCCC111110.  */
+{ "vadds2h", 0x2E14F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vadds2h 0,b,limm 00101bbb000101001BBB111110111110.  */
+{ "vadds2h", 0x28148FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vadds2h<.cc> b,b,limm 00101bbb110101001BBB1111100QQQQQ.  */
+{ "vadds2h", 0x28D48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vadds2h<.cc> 0,limm,c 00101110110101001111CCCCCC0QQQQQ.  */
+{ "vadds2h", 0x2ED4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadds2h a,limm,u6 00101110010101001111uuuuuuAAAAAA.  */
+{ "vadds2h", 0x2E54F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds2h 0,limm,u6 00101110010101001111uuuuuu111110.  */
+{ "vadds2h", 0x2E54F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds2h<.cc> 0,limm,u6 00101110110101001111uuuuuu1QQQQQ.  */
+{ "vadds2h", 0x2ED4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadds2h 0,limm,s12 00101110100101001111ssssssSSSSSS.  */
+{ "vadds2h", 0x2E94F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadds2h a,limm,limm 00101110000101001111111110AAAAAA.  */
+{ "vadds2h", 0x2E14FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vadds2h 0,limm,limm 00101110000101001111111110111110.  */
+{ "vadds2h", 0x2E14FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadds2h<.cc> 0,limm,limm 001011101101010011111111100QQQQQ.  */
+{ "vadds2h", 0x2ED4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA.  */
+{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110.  */
+{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ.  */
+{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA.  */
+{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110.  */
+{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ.  */
+{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS.  */
+{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA.  */
+{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA.  */
+{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110.  */
+{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110.  */
+{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ.  */
+{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ.  */
+{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA.  */
+{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110.  */
+{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ.  */
+{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS.  */
+{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA.  */
+{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub 0,limm,limm 00101110001111100111111110111110.  */
+{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ.  */
+{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA.  */
+{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }},
+
+/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110.  */
+{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ.  */
+{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }},
+
+/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA.  */
+{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110.  */
+{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ.  */
+{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS.  */
+{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA.  */
+{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }},
+
+/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA.  */
+{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }},
+
+/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110.  */
+{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110.  */
+{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ.  */
+{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ.  */
+{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA.  */
+{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110.  */
+{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ.  */
+{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS.  */
+{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA.  */
+{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub2h 0,limm,limm 00101110000101100111111110111110.  */
+{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ.  */
+{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA.  */
+{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110.  */
+{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ.  */
+{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA.  */
+{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110.  */
+{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ.  */
+{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS.  */
+{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA.  */
+{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA.  */
+{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110.  */
+{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110.  */
+{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ.  */
+{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ.  */
+{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA.  */
+{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110.  */
+{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ.  */
+{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS.  */
+{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA.  */
+{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub4h 0,limm,limm 00101110001110100111111110111110.  */
+{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ.  */
+{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsubs2h a,b,c 00101bbb000101101BBBCCCCCCAAAAAA.  */
+{ "vaddsubs2h", 0x28168000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vaddsubs2h 0,b,c 00101bbb000101101BBBCCCCCC111110.  */
+{ "vaddsubs2h", 0x2816803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vaddsubs2h<.cc> b,b,c 00101bbb110101101BBBCCCCCC0QQQQQ.  */
+{ "vaddsubs2h", 0x28D68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vaddsubs2h a,b,u6 00101bbb010101101BBBuuuuuuAAAAAA.  */
+{ "vaddsubs2h", 0x28568000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h 0,b,u6 00101bbb010101101BBBuuuuuu111110.  */
+{ "vaddsubs2h", 0x2856803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h<.cc> b,b,u6 00101bbb110101101BBBuuuuuu1QQQQQ.  */
+{ "vaddsubs2h", 0x28D68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs2h b,b,s12 00101bbb100101101BBBssssssSSSSSS.  */
+{ "vaddsubs2h", 0x28968000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsubs2h a,limm,c 00101110000101101111CCCCCCAAAAAA.  */
+{ "vaddsubs2h", 0x2E16F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vaddsubs2h a,b,limm 00101bbb000101101BBB111110AAAAAA.  */
+{ "vaddsubs2h", 0x28168F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vaddsubs2h 0,limm,c 00101110000101101111CCCCCC111110.  */
+{ "vaddsubs2h", 0x2E16F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsubs2h 0,b,limm 00101bbb000101101BBB111110111110.  */
+{ "vaddsubs2h", 0x28168FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsubs2h<.cc> b,b,limm 00101bbb110101101BBB1111100QQQQQ.  */
+{ "vaddsubs2h", 0x28D68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vaddsubs2h<.cc> 0,limm,c 00101110110101101111CCCCCC0QQQQQ.  */
+{ "vaddsubs2h", 0x2ED6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsubs2h a,limm,u6 00101110010101101111uuuuuuAAAAAA.  */
+{ "vaddsubs2h", 0x2E56F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h 0,limm,u6 00101110010101101111uuuuuu111110.  */
+{ "vaddsubs2h", 0x2E56F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h<.cc> 0,limm,u6 00101110110101101111uuuuuu1QQQQQ.  */
+{ "vaddsubs2h", 0x2ED6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs2h 0,limm,s12 00101110100101101111ssssssSSSSSS.  */
+{ "vaddsubs2h", 0x2E96F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsubs2h a,limm,limm 00101110000101101111111110AAAAAA.  */
+{ "vaddsubs2h", 0x2E16FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs2h 0,limm,limm 00101110000101101111111110111110.  */
+{ "vaddsubs2h", 0x2E16FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs2h<.cc> 0,limm,limm 001011101101011011111111100QQQQQ.  */
+{ "vaddsubs2h", 0x2ED6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* valgn2h a,b,c 00101bbb000011010BBBCCCCCCAAAAAA.  */
+{ "valgn2h", 0x280D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* valgn2h 0,b,c 00101bbb000011010BBBCCCCCC111110.  */
+{ "valgn2h", 0x280D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* valgn2h<.cc> b,b,c 00101bbb110011010BBBCCCCCC0QQQQQ.  */
+{ "valgn2h", 0x28CD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* valgn2h a,b,u6 00101bbb010011010BBBuuuuuuAAAAAA.  */
+{ "valgn2h", 0x284D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* valgn2h 0,b,u6 00101bbb010011010BBBuuuuuu111110.  */
+{ "valgn2h", 0x284D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* valgn2h<.cc> b,b,u6 00101bbb110011010BBBuuuuuu1QQQQQ.  */
+{ "valgn2h", 0x28CD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* valgn2h b,b,s12 00101bbb100011010BBBssssssSSSSSS.  */
+{ "valgn2h", 0x288D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* valgn2h a,limm,c 00101110000011010111CCCCCCAAAAAA.  */
+{ "valgn2h", 0x2E0D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* valgn2h a,b,limm 00101bbb000011010BBB111110AAAAAA.  */
+{ "valgn2h", 0x280D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* valgn2h 0,limm,c 00101110000011010111CCCCCC111110.  */
+{ "valgn2h", 0x2E0D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* valgn2h 0,b,limm 00101bbb000011010BBB111110111110.  */
+{ "valgn2h", 0x280D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* valgn2h<.cc> b,b,limm 00101bbb110011010BBB1111100QQQQQ.  */
+{ "valgn2h", 0x28CD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* valgn2h<.cc> 0,limm,c 00101110110011010111CCCCCC0QQQQQ.  */
+{ "valgn2h", 0x2ECD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* valgn2h a,limm,u6 00101110010011010111uuuuuuAAAAAA.  */
+{ "valgn2h", 0x2E4D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* valgn2h 0,limm,u6 00101110010011010111uuuuuu111110.  */
+{ "valgn2h", 0x2E4D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* valgn2h<.cc> 0,limm,u6 00101110110011010111uuuuuu1QQQQQ.  */
+{ "valgn2h", 0x2ECD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* valgn2h 0,limm,s12 00101110100011010111ssssssSSSSSS.  */
+{ "valgn2h", 0x2E8D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* valgn2h a,limm,limm 00101110000011010111111110AAAAAA.  */
+{ "valgn2h", 0x2E0D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* valgn2h 0,limm,limm 00101110000011010111111110111110.  */
+{ "valgn2h", 0x2E0D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* valgn2h<.cc> 0,limm,limm 001011101100110101111111100QQQQQ.  */
+{ "valgn2h", 0x2ECD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasl2h a,b,c 00101bbb001000010BBBCCCCCCAAAAAA.  */
+{ "vasl2h", 0x28210000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vasl2h 0,b,c 00101bbb001000010BBBCCCCCC111110.  */
+{ "vasl2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasl2h<.cc> b,b,c 00101bbb111000010BBBCCCCCC0QQQQQ.  */
+{ "vasl2h", 0x28E10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vasl2h a,b,u6 00101bbb011000010BBBuuuuuuAAAAAA.  */
+{ "vasl2h", 0x28610000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vasl2h 0,b,u6 00101bbb011000010BBBuuuuuu111110.  */
+{ "vasl2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasl2h<.cc> b,b,u6 00101bbb111000010BBBuuuuuu1QQQQQ.  */
+{ "vasl2h", 0x28E10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasl2h b,b,s12 00101bbb101000010BBBssssssSSSSSS.  */
+{ "vasl2h", 0x28A10000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasl2h a,limm,c 00101110001000010111CCCCCCAAAAAA.  */
+{ "vasl2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vasl2h a,b,limm 00101bbb001000010BBB111110AAAAAA.  */
+{ "vasl2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vasl2h 0,limm,c 00101110011000010111CCCCCC111110.  */
+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasl2h 0,b,limm 00101bbb001000010BBB111110111110.  */
+{ "vasl2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasl2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ.  */
+{ "vasl2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vasl2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ.  */
+{ "vasl2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasl2h a,limm,u6 00101110011000010111uuuuuuAAAAAA.  */
+{ "vasl2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasl2h 0,limm,u6 00101110011000010111uuuuuu111110.  */
+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasl2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ.  */
+{ "vasl2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasl2h 0,limm,s12 00101110101000010111ssssssSSSSSS.  */
+{ "vasl2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasl2h a,limm,limm 00101110001000010111111110AAAAAA.  */
+{ "vasl2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vasl2h 0,limm,limm 00101110001000010111111110111110.  */
+{ "vasl2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasl2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ.  */
+{ "vasl2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasls2h a,b,c 00101bbb001000011BBBCCCCCCAAAAAA.  */
+{ "vasls2h", 0x28218000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vasls2h 0,b,c 00101bbb001000010BBBCCCCCC111110.  */
+{ "vasls2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasls2h<.cc> b,b,c 00101bbb111000011BBBCCCCCC0QQQQQ.  */
+{ "vasls2h", 0x28E18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vasls2h a,b,u6 00101bbb011000011BBBuuuuuuAAAAAA.  */
+{ "vasls2h", 0x28618000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vasls2h 0,b,u6 00101bbb011000010BBBuuuuuu111110.  */
+{ "vasls2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasls2h<.cc> b,b,u6 00101bbb111000011BBBuuuuuu1QQQQQ.  */
+{ "vasls2h", 0x28E18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasls2h b,b,s12 00101bbb101000011BBBssssssSSSSSS.  */
+{ "vasls2h", 0x28A18000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasls2h a,limm,c 00101110001000010111CCCCCCAAAAAA.  */
+{ "vasls2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vasls2h a,b,limm 00101bbb001000010BBB111110AAAAAA.  */
+{ "vasls2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vasls2h 0,limm,c 00101110011000010111CCCCCC111110.  */
+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasls2h 0,b,limm 00101bbb001000010BBB111110111110.  */
+{ "vasls2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasls2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ.  */
+{ "vasls2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vasls2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ.  */
+{ "vasls2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasls2h a,limm,u6 00101110011000010111uuuuuuAAAAAA.  */
+{ "vasls2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasls2h 0,limm,u6 00101110011000010111uuuuuu111110.  */
+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasls2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ.  */
+{ "vasls2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasls2h 0,limm,s12 00101110101000010111ssssssSSSSSS.  */
+{ "vasls2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasls2h a,limm,limm 00101110001000010111111110AAAAAA.  */
+{ "vasls2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vasls2h 0,limm,limm 00101110001000010111111110111110.  */
+{ "vasls2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasls2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ.  */
+{ "vasls2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasr2h a,b,c 00101bbb001000100BBBCCCCCCAAAAAA.  */
+{ "vasr2h", 0x28220000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vasr2h 0,b,c 00101bbb001000100BBBCCCCCC111110.  */
+{ "vasr2h", 0x2822003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasr2h<.cc> b,b,c 00101bbb111000100BBBCCCCCC0QQQQQ.  */
+{ "vasr2h", 0x28E20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vasr2h a,b,u6 00101bbb011000100BBBuuuuuuAAAAAA.  */
+{ "vasr2h", 0x28620000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vasr2h 0,b,u6 00101bbb011000100BBBuuuuuu111110.  */
+{ "vasr2h", 0x2862003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasr2h<.cc> b,b,u6 00101bbb111000100BBBuuuuuu1QQQQQ.  */
+{ "vasr2h", 0x28E20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasr2h b,b,s12 00101bbb101000100BBBssssssSSSSSS.  */
+{ "vasr2h", 0x28A20000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasr2h a,limm,c 00101110001000100111CCCCCCAAAAAA.  */
+{ "vasr2h", 0x2E227000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vasr2h a,b,limm 00101bbb001000100BBB111110AAAAAA.  */
+{ "vasr2h", 0x28220F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vasr2h 0,limm,c 00101110011000100111CCCCCC111110.  */
+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasr2h 0,b,limm 00101bbb001000100BBB111110111110.  */
+{ "vasr2h", 0x28220FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasr2h<.cc> b,b,limm 00101bbb111000100BBB1111100QQQQQ.  */
+{ "vasr2h", 0x28E20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vasr2h<.cc> 0,limm,c 00101110111000100111CCCCCC0QQQQQ.  */
+{ "vasr2h", 0x2EE27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasr2h a,limm,u6 00101110011000100111uuuuuuAAAAAA.  */
+{ "vasr2h", 0x2E627000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasr2h 0,limm,u6 00101110011000100111uuuuuu111110.  */
+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasr2h<.cc> 0,limm,u6 00101110111000100111uuuuuu1QQQQQ.  */
+{ "vasr2h", 0x2EE27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasr2h 0,limm,s12 00101110101000100111ssssssSSSSSS.  */
+{ "vasr2h", 0x2EA27000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasr2h a,limm,limm 00101110001000100111111110AAAAAA.  */
+{ "vasr2h", 0x2E227F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vasr2h 0,limm,limm 00101110001000100111111110111110.  */
+{ "vasr2h", 0x2E227FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasr2h<.cc> 0,limm,limm 001011101110001001111111100QQQQQ.  */
+{ "vasr2h", 0x2EE27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasrs2h a,b,c 00101bbb001000101BBBCCCCCCAAAAAA.  */
+{ "vasrs2h", 0x28228000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vasrs2h 0,b,c 00101bbb001000101BBBCCCCCC111110.  */
+{ "vasrs2h", 0x2822803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasrs2h<.cc> b,b,c 00101bbb111000101BBBCCCCCC0QQQQQ.  */
+{ "vasrs2h", 0x28E28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vasrs2h a,b,u6 00101bbb011000101BBBuuuuuuAAAAAA.  */
+{ "vasrs2h", 0x28628000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vasrs2h 0,b,u6 00101bbb011000101BBBuuuuuu111110.  */
+{ "vasrs2h", 0x2862803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasrs2h<.cc> b,b,u6 00101bbb111000101BBBuuuuuu1QQQQQ.  */
+{ "vasrs2h", 0x28E28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasrs2h b,b,s12 00101bbb101000101BBBssssssSSSSSS.  */
+{ "vasrs2h", 0x28A28000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasrs2h a,limm,c 00101110001000101111CCCCCCAAAAAA.  */
+{ "vasrs2h", 0x2E22F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vasrs2h a,b,limm 00101bbb001000101BBB111110AAAAAA.  */
+{ "vasrs2h", 0x28228F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vasrs2h 0,limm,c 00101110011000101111CCCCCC111110.  */
+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasrs2h 0,b,limm 00101bbb001000101BBB111110111110.  */
+{ "vasrs2h", 0x28228FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasrs2h<.cc> b,b,limm 00101bbb111000101BBB1111100QQQQQ.  */
+{ "vasrs2h", 0x28E28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vasrs2h<.cc> 0,limm,c 00101110111000101111CCCCCC0QQQQQ.  */
+{ "vasrs2h", 0x2EE2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasrs2h a,limm,u6 00101110011000101111uuuuuuAAAAAA.  */
+{ "vasrs2h", 0x2E62F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrs2h 0,limm,u6 00101110011000101111uuuuuu111110.  */
+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrs2h<.cc> 0,limm,u6 00101110111000101111uuuuuu1QQQQQ.  */
+{ "vasrs2h", 0x2EE2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasrs2h 0,limm,s12 00101110101000101111ssssssSSSSSS.  */
+{ "vasrs2h", 0x2EA2F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasrs2h a,limm,limm 00101110001000101111111110AAAAAA.  */
+{ "vasrs2h", 0x2E22FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vasrs2h 0,limm,limm 00101110001000101111111110111110.  */
+{ "vasrs2h", 0x2E22FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasrs2h<.cc> 0,limm,limm 001011101110001011111111100QQQQQ.  */
+{ "vasrs2h", 0x2EE2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasrsr2h a,b,c 00101bbb001000111BBBCCCCCCAAAAAA.  */
+{ "vasrsr2h", 0x28238000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vasrsr2h 0,b,c 00101bbb001000111BBBCCCCCC111110.  */
+{ "vasrsr2h", 0x2823803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasrsr2h<.cc> b,b,c 00101bbb111000111BBBCCCCCC0QQQQQ.  */
+{ "vasrsr2h", 0x28E38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vasrsr2h a,b,u6 00101bbb011000111BBBuuuuuuAAAAAA.  */
+{ "vasrsr2h", 0x28638000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h 0,b,u6 00101bbb011000111BBBuuuuuu111110.  */
+{ "vasrsr2h", 0x2863803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h<.cc> b,b,u6 00101bbb111000111BBBuuuuuu1QQQQQ.  */
+{ "vasrsr2h", 0x28E38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasrsr2h b,b,s12 00101bbb101000111BBBssssssSSSSSS.  */
+{ "vasrsr2h", 0x28A38000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasrsr2h a,limm,c 00101110001000111111CCCCCCAAAAAA.  */
+{ "vasrsr2h", 0x2E23F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vasrsr2h a,b,limm 00101bbb001000111BBB111110AAAAAA.  */
+{ "vasrsr2h", 0x28238F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vasrsr2h 0,limm,c 00101110011000111111CCCCCC111110.  */
+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasrsr2h 0,b,limm 00101bbb001000111BBB111110111110.  */
+{ "vasrsr2h", 0x28238FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasrsr2h<.cc> b,b,limm 00101bbb111000111BBB1111100QQQQQ.  */
+{ "vasrsr2h", 0x28E38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vasrsr2h<.cc> 0,limm,c 00101110111000111111CCCCCC0QQQQQ.  */
+{ "vasrsr2h", 0x2EE3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasrsr2h a,limm,u6 00101110011000111111uuuuuuAAAAAA.  */
+{ "vasrsr2h", 0x2E63F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h 0,limm,u6 00101110011000111111uuuuuu111110.  */
+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h<.cc> 0,limm,u6 00101110111000111111uuuuuu1QQQQQ.  */
+{ "vasrsr2h", 0x2EE3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasrsr2h 0,limm,s12 00101110101000111111ssssssSSSSSS.  */
+{ "vasrsr2h", 0x2EA3F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasrsr2h a,limm,limm 00101110001000111111111110AAAAAA.  */
+{ "vasrsr2h", 0x2E23FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vasrsr2h 0,limm,limm 00101110001000111111111110111110.  */
+{ "vasrsr2h", 0x2E23FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasrsr2h<.cc> 0,limm,limm 001011101110001111111111100QQQQQ.  */
+{ "vasrsr2h", 0x2EE3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001010.  */
+{ "vbfdw", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, RC }, { C_F }},
+
+/* vbfdw<.f> 0,c 0010111000101111F111CCCCCC001010.  */
+{ "vbfdw", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* vbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001010.  */
+{ "vbfdw", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* vbfdw<.f> 0,u6 0010111001101111F111uuuuuu001010.  */
+{ "vbfdw", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* vbfdw<.f> b,limm 00101bbb00101111FBBB111110001010.  */
+{ "vbfdw", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { RB, LIMM }, { C_F }},
+
+/* vbfdw<.f> 0,limm 0010111000101111F111111110001010.  */
+{ "vbfdw", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* vext2bhl b,c 00101bbb001011110BBBCCCCCC100100.  */
+{ "vext2bhl", 0x282F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vext2bhl 0,c 00101110001011110111CCCCCC100100.  */
+{ "vext2bhl", 0x2E2F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vext2bhl b,u6 00101bbb011011110BBBuuuuuu100100.  */
+{ "vext2bhl", 0x286F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vext2bhl 0,u6 00101110011011110111uuuuuu100100.  */
+{ "vext2bhl", 0x2E6F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vext2bhl b,limm 00101bbb001011110BBB111110100100.  */
+{ "vext2bhl", 0x282F0FA4, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vext2bhl 0,limm 00101110001011110111111110100100.  */
+{ "vext2bhl", 0x2E2F7FA4, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vext2bhm b,c 00101bbb001011110BBBCCCCCC100101.  */
+{ "vext2bhm", 0x282F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vext2bhm 0,c 00101110001011110111CCCCCC100101.  */
+{ "vext2bhm", 0x2E2F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vext2bhm b,u6 00101bbb011011110BBBuuuuuu100101.  */
+{ "vext2bhm", 0x286F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vext2bhm 0,u6 00101110011011110111uuuuuu100101.  */
+{ "vext2bhm", 0x2E6F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vext2bhm b,limm 00101bbb001011110BBB111110100101.  */
+{ "vext2bhm", 0x282F0FA5, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vext2bhm 0,limm 00101110001011110111111110100101.  */
+{ "vext2bhm", 0x2E2F7FA5, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vlsr2h a,b,c 00101bbb001000110BBBCCCCCCAAAAAA.  */
+{ "vlsr2h", 0x28230000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vlsr2h 0,b,c 00101bbb001000110BBBCCCCCC111110.  */
+{ "vlsr2h", 0x2823003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vlsr2h<.cc> b,b,c 00101bbb111000110BBBCCCCCC0QQQQQ.  */
+{ "vlsr2h", 0x28E30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vlsr2h a,b,u6 00101bbb011000110BBBuuuuuuAAAAAA.  */
+{ "vlsr2h", 0x28630000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vlsr2h 0,b,u6 00101bbb011000110BBBuuuuuu111110.  */
+{ "vlsr2h", 0x2863003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vlsr2h<.cc> b,b,u6 00101bbb111000110BBBuuuuuu1QQQQQ.  */
+{ "vlsr2h", 0x28E30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vlsr2h b,b,s12 00101bbb101000110BBBssssssSSSSSS.  */
+{ "vlsr2h", 0x28A30000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vlsr2h a,limm,c 00101110001000110111CCCCCCAAAAAA.  */
+{ "vlsr2h", 0x2E237000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vlsr2h a,b,limm 00101bbb001000110BBB111110AAAAAA.  */
+{ "vlsr2h", 0x28230F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vlsr2h 0,limm,c 00101110011000110111CCCCCC111110.  */
+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vlsr2h 0,b,limm 00101bbb001000110BBB111110111110.  */
+{ "vlsr2h", 0x28230FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vlsr2h<.cc> b,b,limm 00101bbb111000110BBB1111100QQQQQ.  */
+{ "vlsr2h", 0x28E30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vlsr2h<.cc> 0,limm,c 00101110111000110111CCCCCC0QQQQQ.  */
+{ "vlsr2h", 0x2EE37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vlsr2h a,limm,u6 00101110011000110111uuuuuuAAAAAA.  */
+{ "vlsr2h", 0x2E637000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vlsr2h 0,limm,u6 00101110011000110111uuuuuu111110.  */
+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vlsr2h<.cc> 0,limm,u6 00101110111000110111uuuuuu1QQQQQ.  */
+{ "vlsr2h", 0x2EE37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vlsr2h 0,limm,s12 00101110101000110111ssssssSSSSSS.  */
+{ "vlsr2h", 0x2EA37000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vlsr2h a,limm,limm 00101110001000110111111110AAAAAA.  */
+{ "vlsr2h", 0x2E237F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vlsr2h 0,limm,limm 00101110001000110111111110111110.  */
+{ "vlsr2h", 0x2E237FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vlsr2h<.cc> 0,limm,limm 001011101110001101111111100QQQQQ.  */
+{ "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA.  */
+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110.  */
+{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ.  */
+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA.  */
+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110.  */
+{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ.  */
+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS.  */
+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA.  */
+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA.  */
+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110.  */
+{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110.  */
+{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ.  */
+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ.  */
+{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA.  */
+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110.  */
+{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ.  */
+{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS.  */
+{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA.  */
+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2h 0,limm,limm 00101110000111100111111110111110.  */
+{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ.  */
+{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hf a,b,c 00101bbb000111101BBBCCCCCCAAAAAA.  */
+{ "vmac2hf", 0x281E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmac2hf 0,b,c 00101bbb000111101BBBCCCCCC111110.  */
+{ "vmac2hf", 0x281E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hf<.cc> b,b,c 00101bbb110111101BBBCCCCCC0QQQQQ.  */
+{ "vmac2hf", 0x28DE8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmac2hf a,b,u6 00101bbb010111101BBBuuuuuuAAAAAA.  */
+{ "vmac2hf", 0x285E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hf 0,b,u6 00101bbb010111101BBBuuuuuu111110.  */
+{ "vmac2hf", 0x285E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hf<.cc> b,b,u6 00101bbb110111101BBBuuuuuu1QQQQQ.  */
+{ "vmac2hf", 0x28DE8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hf b,b,s12 00101bbb100111101BBBssssssSSSSSS.  */
+{ "vmac2hf", 0x289E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hf a,limm,c 00101110000111101111CCCCCCAAAAAA.  */
+{ "vmac2hf", 0x2E1EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmac2hf a,b,limm 00101bbb000111101BBB111110AAAAAA.  */
+{ "vmac2hf", 0x281E8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmac2hf 0,limm,c 00101110000111101111CCCCCC111110.  */
+{ "vmac2hf", 0x2E1EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hf 0,b,limm 00101bbb000111101BBB111110111110.  */
+{ "vmac2hf", 0x281E8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hf<.cc> b,b,limm 00101bbb110111101BBB1111100QQQQQ.  */
+{ "vmac2hf", 0x28DE8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hf<.cc> 0,limm,c 00101110110111101111CCCCCC0QQQQQ.  */
+{ "vmac2hf", 0x2EDEF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hf a,limm,u6 00101110010111101111uuuuuuAAAAAA.  */
+{ "vmac2hf", 0x2E5EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hf 0,limm,u6 00101110010111101111uuuuuu111110.  */
+{ "vmac2hf", 0x2E5EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hf<.cc> 0,limm,u6 00101110110111101111uuuuuu1QQQQQ.  */
+{ "vmac2hf", 0x2EDEF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hf 0,limm,s12 00101110100111101111ssssssSSSSSS.  */
+{ "vmac2hf", 0x2E9EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hf a,limm,limm 00101110000111101111111110AAAAAA.  */
+{ "vmac2hf", 0x2E1EFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hf 0,limm,limm 00101110000111101111111110111110.  */
+{ "vmac2hf", 0x2E1EFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hf<.cc> 0,limm,limm 001011101101111011111111100QQQQQ.  */
+{ "vmac2hf", 0x2EDEFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hfr a,b,c 00101bbb000111111BBBCCCCCCAAAAAA.  */
+{ "vmac2hfr", 0x281F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmac2hfr 0,b,c 00101bbb000111111BBBCCCCCC111110.  */
+{ "vmac2hfr", 0x281F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hfr<.cc> b,b,c 00101bbb110111111BBBCCCCCC0QQQQQ.  */
+{ "vmac2hfr", 0x28DF8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmac2hfr a,b,u6 00101bbb010111111BBBuuuuuuAAAAAA.  */
+{ "vmac2hfr", 0x285F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr 0,b,u6 00101bbb010111111BBBuuuuuu111110.  */
+{ "vmac2hfr", 0x285F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr<.cc> b,b,u6 00101bbb110111111BBBuuuuuu1QQQQQ.  */
+{ "vmac2hfr", 0x28DF8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hfr b,b,s12 00101bbb100111111BBBssssssSSSSSS.  */
+{ "vmac2hfr", 0x289F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hfr a,limm,c 00101110000111111111CCCCCCAAAAAA.  */
+{ "vmac2hfr", 0x2E1FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmac2hfr a,b,limm 00101bbb000111111BBB111110AAAAAA.  */
+{ "vmac2hfr", 0x281F8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmac2hfr 0,limm,c 00101110000111111111CCCCCC111110.  */
+{ "vmac2hfr", 0x2E1FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hfr 0,b,limm 00101bbb000111111BBB111110111110.  */
+{ "vmac2hfr", 0x281F8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hfr<.cc> b,b,limm 00101bbb110111111BBB1111100QQQQQ.  */
+{ "vmac2hfr", 0x28DF8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hfr<.cc> 0,limm,c 00101110110111111111CCCCCC0QQQQQ.  */
+{ "vmac2hfr", 0x2EDFF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hfr a,limm,u6 00101110010111111111uuuuuuAAAAAA.  */
+{ "vmac2hfr", 0x2E5FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr 0,limm,u6 00101110010111111111uuuuuu111110.  */
+{ "vmac2hfr", 0x2E5FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr<.cc> 0,limm,u6 00101110110111111111uuuuuu1QQQQQ.  */
+{ "vmac2hfr", 0x2EDFF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hfr 0,limm,s12 00101110100111111111ssssssSSSSSS.  */
+{ "vmac2hfr", 0x2E9FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hfr a,limm,limm 00101110000111111111111110AAAAAA.  */
+{ "vmac2hfr", 0x2E1FFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hfr 0,limm,limm 00101110000111111111111110111110.  */
+{ "vmac2hfr", 0x2E1FFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hfr<.cc> 0,limm,limm 001011101101111111111111100QQQQQ.  */
+{ "vmac2hfr", 0x2EDFFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hnfr a,b,c 00110bbb000100010BBBCCCCCCAAAAAA.  */
+{ "vmac2hnfr", 0x30110000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmac2hnfr 0,b,c 00110bbb000100010BBBCCCCCC111110.  */
+{ "vmac2hnfr", 0x3011003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hnfr<.cc> b,b,c 00110bbb110100010BBBCCCCCC0QQQQQ.  */
+{ "vmac2hnfr", 0x30D10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmac2hnfr a,b,u6 00110bbb010100010BBBuuuuuuAAAAAA.  */
+{ "vmac2hnfr", 0x30510000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr 0,b,u6 00110bbb010100010BBBuuuuuu111110.  */
+{ "vmac2hnfr", 0x3051003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr<.cc> b,b,u6 00110bbb110100010BBBuuuuuu1QQQQQ.  */
+{ "vmac2hnfr", 0x30D10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hnfr b,b,s12 00110bbb100100010BBBssssssSSSSSS.  */
+{ "vmac2hnfr", 0x30910000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hnfr a,limm,c 00110110000100010111CCCCCCAAAAAA.  */
+{ "vmac2hnfr", 0x36117000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmac2hnfr a,b,limm 00110bbb000100010BBB111110AAAAAA.  */
+{ "vmac2hnfr", 0x30110F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmac2hnfr 0,limm,c 00110110000100010111CCCCCC111110.  */
+{ "vmac2hnfr", 0x3611703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hnfr 0,b,limm 00110bbb000100010BBB111110111110.  */
+{ "vmac2hnfr", 0x30110FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hnfr<.cc> b,b,limm 00110bbb110100010BBB1111100QQQQQ.  */
+{ "vmac2hnfr", 0x30D10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hnfr<.cc> 0,limm,c 00110110110100010111CCCCCC0QQQQQ.  */
+{ "vmac2hnfr", 0x36D17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hnfr a,limm,u6 00110110010100010111uuuuuuAAAAAA.  */
+{ "vmac2hnfr", 0x36517000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr 0,limm,u6 00110110010100010111uuuuuu111110.  */
+{ "vmac2hnfr", 0x3651703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr<.cc> 0,limm,u6 00110110110100010111uuuuuu1QQQQQ.  */
+{ "vmac2hnfr", 0x36D17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hnfr 0,limm,s12 00110110100100010111ssssssSSSSSS.  */
+{ "vmac2hnfr", 0x36917000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hnfr a,limm,limm 00110110000100010111111110AAAAAA.  */
+{ "vmac2hnfr", 0x36117F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hnfr 0,limm,limm 00110110000100010111111110111110.  */
+{ "vmac2hnfr", 0x36117FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hnfr<.cc> 0,limm,limm 001101101101000101111111100QQQQQ.  */
+{ "vmac2hnfr", 0x36D17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA.  */
+{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110.  */
+{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ.  */
+{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA.  */
+{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110.  */
+{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ.  */
+{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS.  */
+{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA.  */
+{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA.  */
+{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110.  */
+{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110.  */
+{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ.  */
+{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ.  */
+{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA.  */
+{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110.  */
+{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ.  */
+{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS.  */
+{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA.  */
+{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hu 0,limm,limm 00101110000111110111111110111110.  */
+{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ.  */
+{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmax2h a,b,c 00101bbb001001001BBBCCCCCCAAAAAA.  */
+{ "vmax2h", 0x28248000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmax2h 0,b,c 00101bbb001001001BBBCCCCCC111110.  */
+{ "vmax2h", 0x2824803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmax2h<.cc> b,b,c 00101bbb111001001BBBCCCCCC0QQQQQ.  */
+{ "vmax2h", 0x28E48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmax2h a,b,u6 00101bbb011001001BBBuuuuuuAAAAAA.  */
+{ "vmax2h", 0x28648000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmax2h 0,b,u6 00101bbb011001001BBBuuuuuu111110.  */
+{ "vmax2h", 0x2864803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmax2h<.cc> b,b,u6 00101bbb111001001BBBuuuuuu1QQQQQ.  */
+{ "vmax2h", 0x28E48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmax2h b,b,s12 00101bbb101001001BBBssssssSSSSSS.  */
+{ "vmax2h", 0x28A48000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmax2h a,limm,c 00101110001001001111CCCCCCAAAAAA.  */
+{ "vmax2h", 0x2E24F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmax2h a,b,limm 00101bbb001001001BBB111110AAAAAA.  */
+{ "vmax2h", 0x28248F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmax2h 0,limm,c 00101110011001001111CCCCCC111110.  */
+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmax2h 0,b,limm 00101bbb001001001BBB111110111110.  */
+{ "vmax2h", 0x28248FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmax2h<.cc> b,b,limm 00101bbb111001001BBB1111100QQQQQ.  */
+{ "vmax2h", 0x28E48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmax2h<.cc> 0,limm,c 00101110111001001111CCCCCC0QQQQQ.  */
+{ "vmax2h", 0x2EE4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmax2h a,limm,u6 00101110011001001111uuuuuuAAAAAA.  */
+{ "vmax2h", 0x2E64F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmax2h 0,limm,u6 00101110011001001111uuuuuu111110.  */
+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmax2h<.cc> 0,limm,u6 00101110111001001111uuuuuu1QQQQQ.  */
+{ "vmax2h", 0x2EE4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmax2h 0,limm,s12 00101110101001001111ssssssSSSSSS.  */
+{ "vmax2h", 0x2EA4F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmax2h a,limm,limm 00101110001001001111111110AAAAAA.  */
+{ "vmax2h", 0x2E24FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmax2h 0,limm,limm 00101110001001001111111110111110.  */
+{ "vmax2h", 0x2E24FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmax2h<.cc> 0,limm,limm 001011101110010011111111100QQQQQ.  */
+{ "vmax2h", 0x2EE4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmin2h a,b,c 00101bbb001001011BBBCCCCCCAAAAAA.  */
+{ "vmin2h", 0x28258000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmin2h 0,b,c 00101bbb001001011BBBCCCCCC111110.  */
+{ "vmin2h", 0x2825803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmin2h<.cc> b,b,c 00101bbb111001011BBBCCCCCC0QQQQQ.  */
+{ "vmin2h", 0x28E58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmin2h a,b,u6 00101bbb011001011BBBuuuuuuAAAAAA.  */
+{ "vmin2h", 0x28658000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmin2h 0,b,u6 00101bbb011001011BBBuuuuuu111110.  */
+{ "vmin2h", 0x2865803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmin2h<.cc> b,b,u6 00101bbb111001011BBBuuuuuu1QQQQQ.  */
+{ "vmin2h", 0x28E58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmin2h b,b,s12 00101bbb101001011BBBssssssSSSSSS.  */
+{ "vmin2h", 0x28A58000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmin2h a,limm,c 00101110001001011111CCCCCCAAAAAA.  */
+{ "vmin2h", 0x2E25F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmin2h a,b,limm 00101bbb001001011BBB111110AAAAAA.  */
+{ "vmin2h", 0x28258F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmin2h 0,limm,c 00101110011001011111CCCCCC111110.  */
+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmin2h 0,b,limm 00101bbb001001011BBB111110111110.  */
+{ "vmin2h", 0x28258FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmin2h<.cc> b,b,limm 00101bbb111001011BBB1111100QQQQQ.  */
+{ "vmin2h", 0x28E58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmin2h<.cc> 0,limm,c 00101110111001011111CCCCCC0QQQQQ.  */
+{ "vmin2h", 0x2EE5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmin2h a,limm,u6 00101110011001011111uuuuuuAAAAAA.  */
+{ "vmin2h", 0x2E65F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmin2h 0,limm,u6 00101110011001011111uuuuuu111110.  */
+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmin2h<.cc> 0,limm,u6 00101110111001011111uuuuuu1QQQQQ.  */
+{ "vmin2h", 0x2EE5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmin2h 0,limm,s12 00101110101001011111ssssssSSSSSS.  */
+{ "vmin2h", 0x2EA5F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmin2h a,limm,limm 00101110001001011111111110AAAAAA.  */
+{ "vmin2h", 0x2E25FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmin2h 0,limm,limm 00101110001001011111111110111110.  */
+{ "vmin2h", 0x2E25FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmin2h<.cc> 0,limm,limm 001011101110010111111111100QQQQQ.  */
+{ "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA.  */
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110.  */
+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ.  */
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA.  */
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { 0 }},
+
+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110.  */
+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ.  */
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA.  */
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110.  */
+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ.  */
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA.  */
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110.  */
+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ.  */
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS.  */
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS.  */
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA.  */
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA.  */
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110.  */
+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110.  */
+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ.  */
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ.  */
+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA.  */
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA.  */
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110.  */
+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110.  */
+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ.  */
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ.  */
+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA.  */
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110.  */
+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ.  */
+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA.  */
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110.  */
+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ.  */
+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS.  */
+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS.  */
+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA.  */
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h 0,limm,limm 00101110000111000111111110111110.  */
+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ.  */
+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA.  */
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h 0,limm,limm 00101110000111000111111110111110.  */
+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ.  */
+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hf a,b,c 00101bbb000111001BBBCCCCCCAAAAAA.  */
+{ "vmpy2hf", 0x281C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmpy2hf 0,b,c 00101bbb000111001BBBCCCCCC111110.  */
+{ "vmpy2hf", 0x281C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hf<.cc> b,b,c 00101bbb110111001BBBCCCCCC0QQQQQ.  */
+{ "vmpy2hf", 0x28DC8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2hf a,b,u6 00101bbb010111001BBBuuuuuuAAAAAA.  */
+{ "vmpy2hf", 0x285C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf 0,b,u6 00101bbb010111001BBBuuuuuu111110.  */
+{ "vmpy2hf", 0x285C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf<.cc> b,b,u6 00101bbb110111001BBBuuuuuu1QQQQQ.  */
+{ "vmpy2hf", 0x28DC8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hf b,b,s12 00101bbb100111001BBBssssssSSSSSS.  */
+{ "vmpy2hf", 0x289C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hf a,limm,c 00101110000111001111CCCCCCAAAAAA.  */
+{ "vmpy2hf", 0x2E1CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2hf a,b,limm 00101bbb000111001BBB111110AAAAAA.  */
+{ "vmpy2hf", 0x281C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2hf 0,limm,c 00101110000111001111CCCCCC111110.  */
+{ "vmpy2hf", 0x2E1CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hf 0,b,limm 00101bbb000111001BBB111110111110.  */
+{ "vmpy2hf", 0x281C8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hf<.cc> b,b,limm 00101bbb110111001BBB1111100QQQQQ.  */
+{ "vmpy2hf", 0x28DC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hf<.cc> 0,limm,c 00101110110111001111CCCCCC0QQQQQ.  */
+{ "vmpy2hf", 0x2EDCF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hf a,limm,u6 00101110010111001111uuuuuuAAAAAA.  */
+{ "vmpy2hf", 0x2E5CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf 0,limm,u6 00101110010111001111uuuuuu111110.  */
+{ "vmpy2hf", 0x2E5CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf<.cc> 0,limm,u6 00101110110111001111uuuuuu1QQQQQ.  */
+{ "vmpy2hf", 0x2EDCF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hf 0,limm,s12 00101110100111001111ssssssSSSSSS.  */
+{ "vmpy2hf", 0x2E9CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hf a,limm,limm 00101110000111001111111110AAAAAA.  */
+{ "vmpy2hf", 0x2E1CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hf 0,limm,limm 00101110000111001111111110111110.  */
+{ "vmpy2hf", 0x2E1CFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hf<.cc> 0,limm,limm 001011101101110011111111100QQQQQ.  */
+{ "vmpy2hf", 0x2EDCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hfr a,b,c 00101bbb000111011BBBCCCCCCAAAAAA.  */
+{ "vmpy2hfr", 0x281D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmpy2hfr 0,b,c 00101bbb000111011BBBCCCCCC111110.  */
+{ "vmpy2hfr", 0x281D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hfr<.cc> b,b,c 00101bbb110111011BBBCCCCCC0QQQQQ.  */
+{ "vmpy2hfr", 0x28DD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2hfr a,b,u6 00101bbb010111011BBBuuuuuuAAAAAA.  */
+{ "vmpy2hfr", 0x285D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr 0,b,u6 00101bbb010111011BBBuuuuuu111110.  */
+{ "vmpy2hfr", 0x285D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr<.cc> b,b,u6 00101bbb110111011BBBuuuuuu1QQQQQ.  */
+{ "vmpy2hfr", 0x28DD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hfr b,b,s12 00101bbb100111011BBBssssssSSSSSS.  */
+{ "vmpy2hfr", 0x289D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hfr a,limm,c 00101110000111011111CCCCCCAAAAAA.  */
+{ "vmpy2hfr", 0x2E1DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2hfr a,b,limm 00101bbb000111011BBB111110AAAAAA.  */
+{ "vmpy2hfr", 0x281D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2hfr 0,limm,c 00101110000111011111CCCCCC111110.  */
+{ "vmpy2hfr", 0x2E1DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hfr 0,b,limm 00101bbb000111011BBB111110111110.  */
+{ "vmpy2hfr", 0x281D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hfr<.cc> b,b,limm 00101bbb110111011BBB1111100QQQQQ.  */
+{ "vmpy2hfr", 0x28DD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hfr<.cc> 0,limm,c 00101110110111011111CCCCCC0QQQQQ.  */
+{ "vmpy2hfr", 0x2EDDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hfr a,limm,u6 00101110010111011111uuuuuuAAAAAA.  */
+{ "vmpy2hfr", 0x2E5DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr 0,limm,u6 00101110010111011111uuuuuu111110.  */
+{ "vmpy2hfr", 0x2E5DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr<.cc> 0,limm,u6 00101110110111011111uuuuuu1QQQQQ.  */
+{ "vmpy2hfr", 0x2EDDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hfr 0,limm,s12 00101110100111011111ssssssSSSSSS.  */
+{ "vmpy2hfr", 0x2E9DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hfr a,limm,limm 00101110000111011111111110AAAAAA.  */
+{ "vmpy2hfr", 0x2E1DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hfr 0,limm,limm 00101110000111011111111110111110.  */
+{ "vmpy2hfr", 0x2E1DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hfr<.cc> 0,limm,limm 001011101101110111111111100QQQQQ.  */
+{ "vmpy2hfr", 0x2EDDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA.  */
+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110.  */
+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ.  */
+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA.  */
+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { 0 }},
+
+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110.  */
+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ.  */
+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA.  */
+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110.  */
+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ.  */
+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA.  */
+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110.  */
+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ.  */
+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS.  */
+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS.  */
+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA.  */
+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA.  */
+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110.  */
+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110.  */
+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ.  */
+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ.  */
+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA.  */
+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA.  */
+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110.  */
+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110.  */
+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ.  */
+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ.  */
+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA.  */
+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110.  */
+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ.  */
+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA.  */
+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110.  */
+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ.  */
+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS.  */
+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS.  */
+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA.  */
+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110.  */
+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ.  */
+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA.  */
+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110.  */
+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ.  */
+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hwf a,b,c 00101bbb001000000BBBCCCCCCAAAAAA.  */
+{ "vmpy2hwf", 0x28200000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmpy2hwf 0,b,c 00101bbb001000000BBBCCCCCC111110.  */
+{ "vmpy2hwf", 0x2820003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hwf<.cc> b,b,c 00101bbb111000000BBBCCCCCC0QQQQQ.  */
+{ "vmpy2hwf", 0x28E00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmpy2hwf a,b,u6 00101bbb011000000BBBuuuuuuAAAAAA.  */
+{ "vmpy2hwf", 0x28600000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf 0,b,u6 00101bbb011000000BBBuuuuuu111110.  */
+{ "vmpy2hwf", 0x2860003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf<.cc> b,b,u6 00101bbb111000000BBBuuuuuu1QQQQQ.  */
+{ "vmpy2hwf", 0x28E00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hwf b,b,s12 00101bbb101000000BBBssssssSSSSSS.  */
+{ "vmpy2hwf", 0x28A00000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hwf a,limm,c 00101110001000000111CCCCCCAAAAAA.  */
+{ "vmpy2hwf", 0x2E207000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmpy2hwf a,b,limm 00101bbb001000000BBB111110AAAAAA.  */
+{ "vmpy2hwf", 0x28200F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmpy2hwf 0,limm,c 00101110011000000111CCCCCC111110.  */
+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hwf 0,b,limm 00101bbb001000000BBB111110111110.  */
+{ "vmpy2hwf", 0x28200FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hwf<.cc> b,b,limm 00101bbb111000000BBB1111100QQQQQ.  */
+{ "vmpy2hwf", 0x28E00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hwf<.cc> 0,limm,c 00101110111000000111CCCCCC0QQQQQ.  */
+{ "vmpy2hwf", 0x2EE07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hwf a,limm,u6 00101110011000000111uuuuuuAAAAAA.  */
+{ "vmpy2hwf", 0x2E607000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf 0,limm,u6 00101110011000000111uuuuuu111110.  */
+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf<.cc> 0,limm,u6 00101110111000000111uuuuuu1QQQQQ.  */
+{ "vmpy2hwf", 0x2EE07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hwf 0,limm,s12 00101110101000000111ssssssSSSSSS.  */
+{ "vmpy2hwf", 0x2EA07000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hwf a,limm,limm 00101110001000000111111110AAAAAA.  */
+{ "vmpy2hwf", 0x2E207F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hwf 0,limm,limm 00101110001000000111111110111110.  */
+{ "vmpy2hwf", 0x2E207FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hwf<.cc> 0,limm,limm 001011101110000001111111100QQQQQ.  */
+{ "vmpy2hwf", 0x2EE07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmsub2hf a,b,c 00110bbb000001000BBBCCCCCCAAAAAA.  */
+{ "vmsub2hf", 0x30040000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmsub2hf 0,b,c 00110bbb000001000BBBCCCCCC111110.  */
+{ "vmsub2hf", 0x3004003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmsub2hf<.cc> b,b,c 00110bbb110001000BBBCCCCCC0QQQQQ.  */
+{ "vmsub2hf", 0x30C40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmsub2hf a,b,u6 00110bbb010001000BBBuuuuuuAAAAAA.  */
+{ "vmsub2hf", 0x30440000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf 0,b,u6 00110bbb010001000BBBuuuuuu111110.  */
+{ "vmsub2hf", 0x3044003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf<.cc> b,b,u6 00110bbb110001000BBBuuuuuu1QQQQQ.  */
+{ "vmsub2hf", 0x30C40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hf b,b,s12 00110bbb100001000BBBssssssSSSSSS.  */
+{ "vmsub2hf", 0x30840000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmsub2hf a,limm,c 00110110000001000111CCCCCCAAAAAA.  */
+{ "vmsub2hf", 0x36047000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmsub2hf a,b,limm 00110bbb000001000BBB111110AAAAAA.  */
+{ "vmsub2hf", 0x30040F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmsub2hf 0,limm,c 00110110000001000111CCCCCC111110.  */
+{ "vmsub2hf", 0x3604703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmsub2hf 0,b,limm 00110bbb000001000BBB111110111110.  */
+{ "vmsub2hf", 0x30040FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmsub2hf<.cc> b,b,limm 00110bbb110001000BBB1111100QQQQQ.  */
+{ "vmsub2hf", 0x30C40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmsub2hf<.cc> 0,limm,c 00110110110001000111CCCCCC0QQQQQ.  */
+{ "vmsub2hf", 0x36C47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmsub2hf a,limm,u6 00110110010001000111uuuuuuAAAAAA.  */
+{ "vmsub2hf", 0x36447000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf 0,limm,u6 00110110010001000111uuuuuu111110.  */
+{ "vmsub2hf", 0x3644703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf<.cc> 0,limm,u6 00110110110001000111uuuuuu1QQQQQ.  */
+{ "vmsub2hf", 0x36C47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hf 0,limm,s12 00110110100001000111ssssssSSSSSS.  */
+{ "vmsub2hf", 0x36847000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmsub2hf a,limm,limm 00110110000001000111111110AAAAAA.  */
+{ "vmsub2hf", 0x36047F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hf 0,limm,limm 00110110000001000111111110111110.  */
+{ "vmsub2hf", 0x36047FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hf<.cc> 0,limm,limm 001101101100010001111111100QQQQQ.  */
+{ "vmsub2hf", 0x36C47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmsub2hfr a,b,c 00110bbb000000110BBBCCCCCCAAAAAA.  */
+{ "vmsub2hfr", 0x30030000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmsub2hfr 0,b,c 00110bbb000000110BBBCCCCCC111110.  */
+{ "vmsub2hfr", 0x3003003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmsub2hfr<.cc> b,b,c 00110bbb110000110BBBCCCCCC0QQQQQ.  */
+{ "vmsub2hfr", 0x30C30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmsub2hfr a,b,u6 00110bbb010000110BBBuuuuuuAAAAAA.  */
+{ "vmsub2hfr", 0x30430000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr 0,b,u6 00110bbb010000110BBBuuuuuu111110.  */
+{ "vmsub2hfr", 0x3043003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr<.cc> b,b,u6 00110bbb110000110BBBuuuuuu1QQQQQ.  */
+{ "vmsub2hfr", 0x30C30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hfr b,b,s12 00110bbb100000110BBBssssssSSSSSS.  */
+{ "vmsub2hfr", 0x30830000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmsub2hfr a,limm,c 00110110000000110111CCCCCCAAAAAA.  */
+{ "vmsub2hfr", 0x36037000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmsub2hfr a,b,limm 00110bbb000000110BBB111110AAAAAA.  */
+{ "vmsub2hfr", 0x30030F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmsub2hfr 0,limm,c 00110110000000110111CCCCCC111110.  */
+{ "vmsub2hfr", 0x3603703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmsub2hfr 0,b,limm 00110bbb000000110BBB111110111110.  */
+{ "vmsub2hfr", 0x30030FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmsub2hfr<.cc> b,b,limm 00110bbb110000110BBB1111100QQQQQ.  */
+{ "vmsub2hfr", 0x30C30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmsub2hfr<.cc> 0,limm,c 00110110110000110111CCCCCC0QQQQQ.  */
+{ "vmsub2hfr", 0x36C37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmsub2hfr a,limm,u6 00110110010000110111uuuuuuAAAAAA.  */
+{ "vmsub2hfr", 0x36437000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr 0,limm,u6 00110110010000110111uuuuuu111110.  */
+{ "vmsub2hfr", 0x3643703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr<.cc> 0,limm,u6 00110110110000110111uuuuuu1QQQQQ.  */
+{ "vmsub2hfr", 0x36C37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hfr 0,limm,s12 00110110100000110111ssssssSSSSSS.  */
+{ "vmsub2hfr", 0x36837000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmsub2hfr a,limm,limm 00110110000000110111111110AAAAAA.  */
+{ "vmsub2hfr", 0x36037F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hfr 0,limm,limm 00110110000000110111111110111110.  */
+{ "vmsub2hfr", 0x36037FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hfr<.cc> 0,limm,limm 001101101100001101111111100QQQQQ.  */
+{ "vmsub2hfr", 0x36C37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmsub2hnfr a,b,c 00110bbb000100011BBBCCCCCCAAAAAA.  */
+{ "vmsub2hnfr", 0x30118000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vmsub2hnfr 0,b,c 00110bbb000100011BBBCCCCCC111110.  */
+{ "vmsub2hnfr", 0x3011803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmsub2hnfr<.cc> b,b,c 00110bbb110100011BBBCCCCCC0QQQQQ.  */
+{ "vmsub2hnfr", 0x30D18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vmsub2hnfr a,b,u6 00110bbb010100011BBBuuuuuuAAAAAA.  */
+{ "vmsub2hnfr", 0x30518000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr 0,b,u6 00110bbb010100011BBBuuuuuu111110.  */
+{ "vmsub2hnfr", 0x3051803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr<.cc> b,b,u6 00110bbb110100011BBBuuuuuu1QQQQQ.  */
+{ "vmsub2hnfr", 0x30D18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hnfr b,b,s12 00110bbb100100011BBBssssssSSSSSS.  */
+{ "vmsub2hnfr", 0x30918000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmsub2hnfr a,limm,c 00110110000100011111CCCCCCAAAAAA.  */
+{ "vmsub2hnfr", 0x3611F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vmsub2hnfr a,b,limm 00110bbb000100011BBB111110AAAAAA.  */
+{ "vmsub2hnfr", 0x30118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vmsub2hnfr 0,limm,c 00110110000100011111CCCCCC111110.  */
+{ "vmsub2hnfr", 0x3611F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmsub2hnfr 0,b,limm 00110bbb000100011BBB111110111110.  */
+{ "vmsub2hnfr", 0x30118FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmsub2hnfr<.cc> b,b,limm 00110bbb110100011BBB1111100QQQQQ.  */
+{ "vmsub2hnfr", 0x30D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vmsub2hnfr<.cc> 0,limm,c 00110110110100011111CCCCCC0QQQQQ.  */
+{ "vmsub2hnfr", 0x36D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmsub2hnfr a,limm,u6 00110110010100011111uuuuuuAAAAAA.  */
+{ "vmsub2hnfr", 0x3651F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr 0,limm,u6 00110110010100011111uuuuuu111110.  */
+{ "vmsub2hnfr", 0x3651F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr<.cc> 0,limm,u6 00110110110100011111uuuuuu1QQQQQ.  */
+{ "vmsub2hnfr", 0x36D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hnfr 0,limm,s12 00110110100100011111ssssssSSSSSS.  */
+{ "vmsub2hnfr", 0x3691F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmsub2hnfr a,limm,limm 00110110000100011111111110AAAAAA.  */
+{ "vmsub2hnfr", 0x3611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hnfr 0,limm,limm 00110110000100011111111110111110.  */
+{ "vmsub2hnfr", 0x3611FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hnfr<.cc> 0,limm,limm 001101101101000111111111100QQQQQ.  */
+{ "vmsub2hnfr", 0x36D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vneg2h b,c 00101bbb001011110BBBCCCCCC101010.  */
+{ "vneg2h", 0x282F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vneg2h 0,c 00101110001011110111CCCCCC101010.  */
+{ "vneg2h", 0x2E2F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vneg2h b,u6 00101bbb011011110BBBuuuuuu101010.  */
+{ "vneg2h", 0x286F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vneg2h 0,u6 00101110011011110111uuuuuu101010.  */
+{ "vneg2h", 0x2E6F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vneg2h b,limm 00101bbb001011110BBB111110101010.  */
+{ "vneg2h", 0x282F0FAA, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vneg2h 0,limm 00101110001011110111111110101010.  */
+{ "vneg2h", 0x2E2F7FAA, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vnegs2h b,c 00101bbb001011110BBBCCCCCC101011.  */
+{ "vnegs2h", 0x282F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vnegs2h 0,c 00101110001011110111CCCCCC101011.  */
+{ "vnegs2h", 0x2E2F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vnegs2h b,u6 00101bbb011011110BBBuuuuuu101011.  */
+{ "vnegs2h", 0x286F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vnegs2h 0,u6 00101110011011110111uuuuuu101011.  */
+{ "vnegs2h", 0x2E6F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vnegs2h b,limm 00101bbb001011110BBB111110101011.  */
+{ "vnegs2h", 0x282F0FAB, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vnegs2h 0,limm 00101110001011110111111110101011.  */
+{ "vnegs2h", 0x2E2F7FAB, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vnorm2h b,c 00101bbb001011110BBBCCCCCC101100.  */
+{ "vnorm2h", 0x282F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vnorm2h 0,c 00101110001011110111CCCCCC101100.  */
+{ "vnorm2h", 0x2E2F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vnorm2h b,u6 00101bbb011011110BBBuuuuuu101100.  */
+{ "vnorm2h", 0x286F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vnorm2h 0,u6 00101110011011110111uuuuuu101100.  */
+{ "vnorm2h", 0x2E6F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vnorm2h b,limm 00101bbb001011110BBB111110101100.  */
+{ "vnorm2h", 0x282F0FAC, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vnorm2h 0,limm 00101110001011110111111110101100.  */
+{ "vnorm2h", 0x2E2F7FAC, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vrep2hl b,c 00101bbb001011110BBBCCCCCC100010.  */
+{ "vrep2hl", 0x282F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vrep2hl 0,c 00101110001011110111CCCCCC100010.  */
+{ "vrep2hl", 0x2E2F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vrep2hl b,u6 00101bbb011011110BBBuuuuuu100010.  */
+{ "vrep2hl", 0x286F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vrep2hl 0,u6 00101110011011110111uuuuuu100010.  */
+{ "vrep2hl", 0x2E6F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vrep2hl b,limm 00101bbb001011110BBB111110100010.  */
+{ "vrep2hl", 0x282F0FA2, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vrep2hl 0,limm 00101110001011110111111110100010.  */
+{ "vrep2hl", 0x2E2F7FA2, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vrep2hm b,c 00101bbb001011110BBBCCCCCC100011.  */
+{ "vrep2hm", 0x282F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vrep2hm 0,c 00101110001011110111CCCCCC100011.  */
+{ "vrep2hm", 0x2E2F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vrep2hm b,u6 00101bbb011011110BBBuuuuuu100011.  */
+{ "vrep2hm", 0x286F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vrep2hm 0,u6 00101110011011110111uuuuuu100011.  */
+{ "vrep2hm", 0x2E6F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vrep2hm b,limm 00101bbb001011110BBB111110100011.  */
+{ "vrep2hm", 0x282F0FA3, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vrep2hm 0,limm 00101110001011110111111110100011.  */
+{ "vrep2hm", 0x2E2F7FA3, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vsext2bhl b,c 00101bbb001011110BBBCCCCCC100110.  */
+{ "vsext2bhl", 0x282F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vsext2bhl 0,c 00101110001011110111CCCCCC100110.  */
+{ "vsext2bhl", 0x2E2F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vsext2bhl b,u6 00101bbb011011110BBBuuuuuu100110.  */
+{ "vsext2bhl", 0x286F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vsext2bhl 0,u6 00101110011011110111uuuuuu100110.  */
+{ "vsext2bhl", 0x2E6F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vsext2bhl b,limm 00101bbb001011110BBB111110100110.  */
+{ "vsext2bhl", 0x282F0FA6, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vsext2bhl 0,limm 00101110001011110111111110100110.  */
+{ "vsext2bhl", 0x2E2F7FA6, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vsext2bhm b,c 00101bbb001011110BBBCCCCCC100111.  */
+{ "vsext2bhm", 0x282F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+
+/* vsext2bhm 0,c 00101110001011110111CCCCCC100111.  */
+{ "vsext2bhm", 0x2E2F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vsext2bhm b,u6 00101bbb011011110BBBuuuuuu100111.  */
+{ "vsext2bhm", 0x286F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* vsext2bhm 0,u6 00101110011011110111uuuuuu100111.  */
+{ "vsext2bhm", 0x2E6F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vsext2bhm b,limm 00101bbb001011110BBB111110100111.  */
+{ "vsext2bhm", 0x282F0FA7, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+
+/* vsext2bhm 0,limm 00101110001011110111111110100111.  */
+{ "vsext2bhm", 0x2E2F7FA7, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA.  */
+{ "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110.  */
+{ "vsub2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ.  */
+{ "vsub2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA.  */
+{ "vsub2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110.  */
+{ "vsub2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ.  */
+{ "vsub2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS.  */
+{ "vsub2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA.  */
+{ "vsub2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA.  */
+{ "vsub2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vsub2 0,limm,c 00101110001111010111CCCCCC111110.  */
+{ "vsub2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub2 0,b,limm 00101bbb001111010BBB111110111110.  */
+{ "vsub2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ.  */
+{ "vsub2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ.  */
+{ "vsub2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA.  */
+{ "vsub2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110.  */
+{ "vsub2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ.  */
+{ "vsub2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS.  */
+{ "vsub2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA.  */
+{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2 0,limm,limm 00101110001111010111111110111110.  */
+{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ.  */
+{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA.  */
+{ "vsub2h", 0x28150000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }},
+
+/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110.  */
+{ "vsub2h", 0x2815003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ.  */
+{ "vsub2h", 0x28D50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }},
+
+/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA.  */
+{ "vsub2h", 0x28550000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110.  */
+{ "vsub2h", 0x2855003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ.  */
+{ "vsub2h", 0x28D50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS.  */
+{ "vsub2h", 0x28950000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA.  */
+{ "vsub2h", 0x2E157000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }},
+
+/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA.  */
+{ "vsub2h", 0x28150F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }},
+
+/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110.  */
+{ "vsub2h", 0x2E15703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110.  */
+{ "vsub2h", 0x28150FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ.  */
+{ "vsub2h", 0x28D50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ.  */
+{ "vsub2h", 0x2ED57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA.  */
+{ "vsub2h", 0x2E557000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110.  */
+{ "vsub2h", 0x2E55703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ.  */
+{ "vsub2h", 0x2ED57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS.  */
+{ "vsub2h", 0x2E957000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA.  */
+{ "vsub2h", 0x2E157F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2h 0,limm,limm 00101110000101010111111110111110.  */
+{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ.  */
+{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub4b a,b,c 00101bbb001001010BBBCCCCCCAAAAAA.  */
+{ "vsub4b", 0x28250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vsub4b 0,b,c 00101bbb001001010BBBCCCCCC111110.  */
+{ "vsub4b", 0x2825003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vsub4b<.cc> b,b,c 00101bbb111001010BBBCCCCCC0QQQQQ.  */
+{ "vsub4b", 0x28E50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vsub4b a,b,u6 00101bbb011001010BBBuuuuuuAAAAAA.  */
+{ "vsub4b", 0x28650000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4b 0,b,u6 00101bbb011001010BBBuuuuuu111110.  */
+{ "vsub4b", 0x2865003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4b<.cc> b,b,u6 00101bbb111001010BBBuuuuuu1QQQQQ.  */
+{ "vsub4b", 0x28E50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub4b b,b,s12 00101bbb101001010BBBssssssSSSSSS.  */
+{ "vsub4b", 0x28A50000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub4b a,limm,c 00101110001001010111CCCCCCAAAAAA.  */
+{ "vsub4b", 0x2E257000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vsub4b a,b,limm 00101bbb001001010BBB111110AAAAAA.  */
+{ "vsub4b", 0x28250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vsub4b 0,limm,c 00101110011001010111CCCCCC111110.  */
+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub4b 0,b,limm 00101bbb001001010BBB111110111110.  */
+{ "vsub4b", 0x28250FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub4b<.cc> b,b,limm 00101bbb111001010BBB1111100QQQQQ.  */
+{ "vsub4b", 0x28E50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsub4b<.cc> 0,limm,c 00101110111001010111CCCCCC0QQQQQ.  */
+{ "vsub4b", 0x2EE57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub4b a,limm,u6 00101110011001010111uuuuuuAAAAAA.  */
+{ "vsub4b", 0x2E657000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4b 0,limm,u6 00101110011001010111uuuuuu111110.  */
+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4b<.cc> 0,limm,u6 00101110111001010111uuuuuu1QQQQQ.  */
+{ "vsub4b", 0x2EE57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub4b 0,limm,s12 00101110101001010111ssssssSSSSSS.  */
+{ "vsub4b", 0x2EA57000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub4b a,limm,limm 00101110001001010111111110AAAAAA.  */
+{ "vsub4b", 0x2E257F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4b 0,limm,limm 00101110001001010111111110111110.  */
+{ "vsub4b", 0x2E257FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4b<.cc> 0,limm,limm 001011101110010101111111100QQQQQ.  */
+{ "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA.  */
+{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110.  */
+{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ.  */
+{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA.  */
+{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110.  */
+{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ.  */
+{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS.  */
+{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA.  */
+{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA.  */
+{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110.  */
+{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110.  */
+{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ.  */
+{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ.  */
+{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA.  */
+{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110.  */
+{ "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ.  */
+{ "vsub4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS.  */
+{ "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA.  */
+{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4h 0,limm,limm 00101110001110010111111110111110.  */
+{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ.  */
+{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA.  */
+{ "vsubadd", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110.  */
+{ "vsubadd", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ.  */
+{ "vsubadd", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA.  */
+{ "vsubadd", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110.  */
+{ "vsubadd", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ.  */
+{ "vsubadd", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS.  */
+{ "vsubadd", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA.  */
+{ "vsubadd", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA.  */
+{ "vsubadd", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110.  */
+{ "vsubadd", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110.  */
+{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ.  */
+{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ.  */
+{ "vsubadd", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA.  */
+{ "vsubadd", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110.  */
+{ "vsubadd", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ.  */
+{ "vsubadd", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS.  */
+{ "vsubadd", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA.  */
+{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd 0,limm,limm 00101110001111110111111110111110.  */
+{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ.  */
+{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA.  */
+{ "vsubadd2h", 0x28170000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }},
+
+/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110.  */
+{ "vsubadd2h", 0x2817003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ.  */
+{ "vsubadd2h", 0x28D70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }},
+
+/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA.  */
+{ "vsubadd2h", 0x28570000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110.  */
+{ "vsubadd2h", 0x2857003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ.  */
+{ "vsubadd2h", 0x28D70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS.  */
+{ "vsubadd2h", 0x28970000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA.  */
+{ "vsubadd2h", 0x2E177000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }},
+
+/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA.  */
+{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }},
+
+/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110.  */
+{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110.  */
+{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ.  */
+{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ.  */
+{ "vsubadd2h", 0x2ED77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA.  */
+{ "vsubadd2h", 0x2E577000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110.  */
+{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ.  */
+{ "vsubadd2h", 0x2ED77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS.  */
+{ "vsubadd2h", 0x2E977000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA.  */
+{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd2h 0,limm,limm 00101110000101110111111110111110.  */
+{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ.  */
+{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA.  */
+{ "vsubadd4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }},
+
+/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110.  */
+{ "vsubadd4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ.  */
+{ "vsubadd4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }},
+
+/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA.  */
+{ "vsubadd4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110.  */
+{ "vsubadd4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ.  */
+{ "vsubadd4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS.  */
+{ "vsubadd4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA.  */
+{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }},
+
+/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA.  */
+{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }},
+
+/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110.  */
+{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110.  */
+{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ.  */
+{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ.  */
+{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA.  */
+{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110.  */
+{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ.  */
+{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS.  */
+{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA.  */
+{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd4h 0,limm,limm 00101110001110110111111110111110.  */
+{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ.  */
+{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadds2h a,b,c 00101bbb000101111BBBCCCCCCAAAAAA.  */
+{ "vsubadds2h", 0x28178000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vsubadds2h 0,b,c 00101bbb000101111BBBCCCCCC111110.  */
+{ "vsubadds2h", 0x2817803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vsubadds2h<.cc> b,b,c 00101bbb110101111BBBCCCCCC0QQQQQ.  */
+{ "vsubadds2h", 0x28D78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vsubadds2h a,b,u6 00101bbb010101111BBBuuuuuuAAAAAA.  */
+{ "vsubadds2h", 0x28578000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h 0,b,u6 00101bbb010101111BBBuuuuuu111110.  */
+{ "vsubadds2h", 0x2857803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h<.cc> b,b,u6 00101bbb110101111BBBuuuuuu1QQQQQ.  */
+{ "vsubadds2h", 0x28D78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadds2h b,b,s12 00101bbb100101111BBBssssssSSSSSS.  */
+{ "vsubadds2h", 0x28978000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadds2h a,limm,c 00101110000101111111CCCCCCAAAAAA.  */
+{ "vsubadds2h", 0x2E17F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vsubadds2h a,b,limm 00101bbb000101111BBB111110AAAAAA.  */
+{ "vsubadds2h", 0x28178F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vsubadds2h 0,limm,c 00101110000101111111CCCCCC111110.  */
+{ "vsubadds2h", 0x2E17F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadds2h 0,b,limm 00101bbb000101111BBB111110111110.  */
+{ "vsubadds2h", 0x28178FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadds2h<.cc> b,b,limm 00101bbb110101111BBB1111100QQQQQ.  */
+{ "vsubadds2h", 0x28D78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsubadds2h<.cc> 0,limm,c 00101110110101111111CCCCCC0QQQQQ.  */
+{ "vsubadds2h", 0x2ED7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadds2h a,limm,u6 00101110010101111111uuuuuuAAAAAA.  */
+{ "vsubadds2h", 0x2E57F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h 0,limm,u6 00101110010101111111uuuuuu111110.  */
+{ "vsubadds2h", 0x2E57F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h<.cc> 0,limm,u6 00101110110101111111uuuuuu1QQQQQ.  */
+{ "vsubadds2h", 0x2ED7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadds2h 0,limm,s12 00101110100101111111ssssssSSSSSS.  */
+{ "vsubadds2h", 0x2E97F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadds2h a,limm,limm 00101110000101111111111110AAAAAA.  */
+{ "vsubadds2h", 0x2E17FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds2h 0,limm,limm 00101110000101111111111110111110.  */
+{ "vsubadds2h", 0x2E17FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds2h<.cc> 0,limm,limm 001011101101011111111111100QQQQQ.  */
+{ "vsubadds2h", 0x2ED7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubs2h a,b,c 00101bbb000101011BBBCCCCCCAAAAAA.  */
+{ "vsubs2h", 0x28158000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+
+/* vsubs2h 0,b,c 00101bbb000101011BBBCCCCCC111110.  */
+{ "vsubs2h", 0x2815803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vsubs2h<.cc> b,b,c 00101bbb110101011BBBCCCCCC0QQQQQ.  */
+{ "vsubs2h", 0x28D58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* vsubs2h a,b,u6 00101bbb010101011BBBuuuuuuAAAAAA.  */
+{ "vsubs2h", 0x28558000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs2h 0,b,u6 00101bbb010101011BBBuuuuuu111110.  */
+{ "vsubs2h", 0x2855803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs2h<.cc> b,b,u6 00101bbb110101011BBBuuuuuu1QQQQQ.  */
+{ "vsubs2h", 0x28D58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubs2h b,b,s12 00101bbb100101011BBBssssssSSSSSS.  */
+{ "vsubs2h", 0x28958000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubs2h a,limm,c 00101110000101011111CCCCCCAAAAAA.  */
+{ "vsubs2h", 0x2E15F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* vsubs2h a,b,limm 00101bbb000101011BBB111110AAAAAA.  */
+{ "vsubs2h", 0x28158F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* vsubs2h 0,limm,c 00101110000101011111CCCCCC111110.  */
+{ "vsubs2h", 0x2E15F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubs2h 0,b,limm 00101bbb000101011BBB111110111110.  */
+{ "vsubs2h", 0x28158FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubs2h<.cc> b,b,limm 00101bbb110101011BBB1111100QQQQQ.  */
+{ "vsubs2h", 0x28D58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* vsubs2h<.cc> 0,limm,c 00101110110101011111CCCCCC0QQQQQ.  */
+{ "vsubs2h", 0x2ED5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubs2h a,limm,u6 00101110010101011111uuuuuuAAAAAA.  */
+{ "vsubs2h", 0x2E55F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs2h 0,limm,u6 00101110010101011111uuuuuu111110.  */
+{ "vsubs2h", 0x2E55F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs2h<.cc> 0,limm,u6 00101110110101011111uuuuuu1QQQQQ.  */
+{ "vsubs2h", 0x2ED5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubs2h 0,limm,s12 00101110100101011111ssssssSSSSSS.  */
+{ "vsubs2h", 0x2E95F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubs2h a,limm,limm 00101110000101011111111110AAAAAA.  */
+{ "vsubs2h", 0x2E15FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs2h 0,limm,limm 00101110000101011111111110111110.  */
+{ "vsubs2h", 0x2E15FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs2h<.cc> 0,limm,limm 001011101101010111111111100QQQQQ.  */
+{ "vsubs2h", 0x2ED5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* wevt c 00100000001011110001CCCCCC111111.  */
+{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }},
+
+/* wevt u6 00100000011011110001uuuuuu111111.  */
+{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* wlfc c 00100001001011110001CCCCCC111111.  */
+{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }},
+
+/* wlfc u6 00100001011011110001uuuuuu111111.  */
+{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA.  */
+{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110.  */
+{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ.  */
+{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA.  */
+{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110.  */
+{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ.  */
+{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS.  */
+{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA.  */
+{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA.  */
+{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110.  */
+{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110.  */
+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ.  */
+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ.  */
+{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA.  */
+{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110.  */
+{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ.  */
+{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS.  */
+{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA.  */
+{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110.  */
+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ.  */
+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA.  */
+{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110.  */
+{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ.  */
+{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA.  */
+{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110.  */
+{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ.  */
+{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS.  */
+{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA.  */
+{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA.  */
+{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110.  */
+{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110.  */
+{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ.  */
+{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ.  */
+{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA.  */
+{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110.  */
+{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ.  */
+{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS.  */
+{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA.  */
+{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xor<.f> 0,limm,limm 0010011000000111F111111110111110.  */
+{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ.  */
+{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xor_s b,b,c 01111bbbccc00111.  */
+{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* xpkqb<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA.  */
+{ "xpkqb", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* xpkqb<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ.  */
+{ "xpkqb", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xpkqb<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA.  */
+{ "xpkqb", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xpkqb<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ.  */
+{ "xpkqb", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xpkqb<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS.  */
+
+{ "xpkqb", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xpkqb<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA.  */
+{ "xpkqb", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xpkqb<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA.  */
+{ "xpkqb", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xpkqb<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ.  */
+{ "xpkqb", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+