arm64: dts: mt7986: add spi related device nodes

This patch adds spi support for MT7986.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
index 1dd54e8..9b83925 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -59,6 +59,20 @@
 };
 
 &pio {
+       spi_flash_pins: spi-flash-pins {
+               mux {
+                       function = "spi";
+                       groups = "spi0", "spi0_wp_hold";
+               };
+       };
+
+       spic_pins: spic-pins {
+               mux {
+                       function = "spi";
+                       groups = "spi1_2";
+               };
+       };
+
        uart1_pins: uart1-pins {
                mux {
                        function = "uart";
@@ -105,6 +119,27 @@
        };
 };
 
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi_flash_pins>;
+       cs-gpios = <0>, <0>;
+       status = "okay";
+       spi_nand: spi_nand@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+               spi-tx-buswidth = <4>;
+               spi-rx-buswidth = <4>;
+       };
+};
+
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spic_pins>;
+       cs-gpios = <0>, <0>;
+       status = "okay";
+};
+
 &switch {
        ports {
                #address-cells = <1>;

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index cf6c490..ed70302 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -254,6 +254,34 @@
                        status = "disabled";
                };
 
+               spi0: spi@1100a000 {
+                       compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0 0x1100a000 0 0x100>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
+                                <&topckgen CLK_TOP_SPI_SEL>,
+                                <&infracfg CLK_INFRA_SPI0_CK>,
+                                <&infracfg CLK_INFRA_SPI0_HCK_CK>;
+                       clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+                       status = "disabled";
+               };
+
+               spi1: spi@1100b000 {
+                       compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0 0x1100b000 0 0x100>;
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
+                                <&topckgen CLK_TOP_SPIM_MST_SEL>,
+                                <&infracfg CLK_INFRA_SPI1_CK>,
+                                <&infracfg CLK_INFRA_SPI1_HCK_CK>;
+                       clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+                       status = "disabled";
+               };
+
                ethsys: syscon@15000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;

diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
index 7cfcbb9..243760c 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -100,6 +100,20 @@
 };
 
 &pio {
+       spi_flash_pins: spi-flash-pins {
+               mux {
+                       function = "spi";
+                       groups = "spi0", "spi0_wp_hold";
+               };
+       };
+
+       spic_pins: spic-pins {
+               mux {
+                       function = "spi";
+                       groups = "spi1_2";
+               };
+       };
+
        wf_2g_5g_pins: wf-2g-5g-pins {
                mux {
                        function = "wifi";
@@ -132,6 +146,27 @@
        };
 };
 
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi_flash_pins>;
+       cs-gpios = <0>, <0>;
+       status = "okay";
+       spi_nand: spi_nand@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+               spi-tx-buswidth = <4>;
+               spi-rx-buswidth = <4>;
+       };
+};
+
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spic_pins>;
+       cs-gpios = <0>, <0>;
+       status = "okay";
+};
+
 &uart0 {
        status = "okay";
 };