struct list_head head;
int id; /* idr assigned */
unsigned int pitch;
- unsigned long offset;
unsigned int width;
unsigned int height;
/* depth can be 15 or 16 */
return -EINVAL;
}
- fb->offset = fbo->offset;
fb->bo = fbo;
printk("allocated %dx%d fb: 0x%08lx, bo %p\n", fb->width,
fb->height, fbo->offset, fbo);
info->fix.mmio_start = 0;
info->fix.mmio_len = 0;
info->fix.line_length = fb->pitch;
- info->fix.smem_start = fb->offset + dev->mode_config.fb_base;
+ info->fix.smem_start = fb->bo->offset + dev->mode_config.fb_base;
info->fix.smem_len = info->fix.line_length * fb->height;
info->flags = FBINFO_DEFAULT;
return -EINVAL;
}
- fb->offset = fb->bo->offset;
DRM_INFO("[radeon_ms] framebuffer %dx%d at 0x%08lX\n",
fb->width, fb->height, fb->bo->offset);
info->fix.mmio_start = 0;
info->fix.mmio_len = 0;
info->fix.line_length = fb->pitch;
- info->fix.smem_start = fb->offset + dev->mode_config.fb_base;
+ info->fix.smem_start = fb->bo->offset + dev->mode_config.fb_base;
info->fix.smem_len = info->fix.line_length * fb->height;
info->flags = FBINFO_DEFAULT;
DRM_INFO("[radeon_ms] fb physical start : 0x%lX\n", info->fix.smem_start);
}
radeon_pll1_compute(crtc, adjusted_mode);
- state->crtc_offset = REG_S(CRTC_OFFSET, CRTC_OFFSET, crtc->fb->offset);
+ state->crtc_offset = REG_S(CRTC_OFFSET, CRTC_OFFSET, crtc->fb->bo->offset);
state->crtc_gen_cntl = CRTC_GEN_CNTL__CRTC_EXT_DISP_EN |
CRTC_GEN_CNTL__CRTC_EN |
REG_S(CRTC_GEN_CNTL, CRTC_PIX_WIDTH, format);