omap: mailbox: Flush posted write when acking mailbox irq

The only way to flush posted write to L4 bus is to do a read back
of the same register right after the write.

This seems to be mostly needed in interrupt handlers to avoid
causing spurious interrupts.

The earlier fix has been to mark the L4 bus as strongly ordered
memory, which solves the problem, but causes performance penalties.

Similar to the fix, 03803a71041e3bc3c077f4e7b92f6ceaa9426df3

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 5bf9a2fdb682125b1f9acdb67664dd2739607c7d..f3fefca584949831d0905bd35a74627927b91d9e 100644 (file)
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -176,6 +176,9 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
        mbox_write_reg(bit, p->irqstatus);
+
+       /* Flush posted write for irq status to avoid spurious interrupts */
+       mbox_read_reg(p->irqstatus);
 }
 
 static int omap2_mbox_is_irq(struct omap_mbox *mbox,