Fix MIPS MT GPR accesses, thanks Stefan Weil.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4307 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/op.c b/target-mips/op.c
index c5187fe9a3e23c73df8a2c4ebdd99e0dba5479b5..b19c4394b75bd4581119db0ee17183081c58d2f8 100644 (file)
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -2300,7 +2300,7 @@ void op_mftgpr(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2308,7 +2308,7 @@ void op_mftlo(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2316,7 +2316,7 @@ void op_mfthi(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2324,7 +2324,7 @@ void op_mftacx(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2340,7 +2340,7 @@ void op_mttgpr(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2348,7 +2348,7 @@ void op_mttlo(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2356,7 +2356,7 @@ void op_mtthi(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2364,7 +2364,7 @@ void op_mttacx(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }
 

diff --git a/target-mips/op_template.c b/target-mips/op_template.c
index c683330024424031f780a4ea375bb3e01ff090d2..e7e3750fa88ddd221724e9841328a4647cb71acf 100644 (file)
--- a/target-mips/op_template.c
+++ b/target-mips/op_template.c
@@ -52,13 +52,13 @@ void glue(op_load_gpr_T2_gpr, REG) (void)
 
 void glue(op_load_srsgpr_T0_gpr, REG) (void)
 {
-    T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf];
+    T0 = env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG];
     FORCE_RET();
 }
 
 void glue(op_store_T0_srsgpr_gpr, REG) (void)
 {
-    env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0;
+    env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG] = T0;
     FORCE_RET();
 }
 #endif