assembler: switch the order of swizzle and regtype to match the BNF of the assembly
authorXiang, Haihao <haihao.xiang@intel.com>
Tue, 25 Mar 2014 05:41:25 +0000 (13:41 +0800)
committerDamien Lespiau <damien.lespiau@intel.com>
Mon, 19 May 2014 21:49:11 +0000 (22:49 +0100)
Fortunately our existing source didn't use swizzle.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631
Tested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
assembler/gram.y

index f4d270d..e56533d 100644 (file)
@@ -2262,21 +2262,21 @@ directsrcoperand:       negate abs symbol_reg region regtype
                    $$.reg.type = $3.type;
                  }
                }
-               | negate abs directgenreg region regtype swizzle
+               | negate abs directgenreg region swizzle regtype
                {
                  memset (&$$, '\0', sizeof ($$));
                  $$.reg.address_mode = BRW_ADDRESS_DIRECT;
                  $$.reg.file = $3.file;
                  $$.reg.nr = $3.nr;
                  $$.reg.subnr = $3.subnr;
-                 $$.reg.type = $5.type;
+                 $$.reg.type = $6.type;
                  $$.reg.vstride = $4.vert_stride;
                  $$.reg.width = $4.width;
                  $$.reg.hstride = $4.horiz_stride;
                  $$.default_region = $4.is_default;
                  $$.reg.negate = $1;
                  $$.reg.abs = $2;
-                 $$.reg.dw1.bits.swizzle = $6.reg.dw1.bits.swizzle;
+                 $$.reg.dw1.bits.swizzle = $5.reg.dw1.bits.swizzle;
                }
                | srcarchoperandex
 ;