arm64: dts: imx8qm: add cpu frequency table

Add A53 and A72 opp_table.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 9fff867..effd84e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -62,6 +62,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x0>;
+                       clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
                        i-cache-size = <0x8000>;
                        i-cache-line-size = <64>;
@@ -70,12 +71,14 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                };
 
                A53_1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x1>;
+                       clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
                        i-cache-size = <0x8000>;
                        i-cache-line-size = <64>;
@@ -84,12 +87,14 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                };
 
                A53_2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x2>;
+                       clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
                        i-cache-size = <0x8000>;
                        i-cache-line-size = <64>;
@@ -98,12 +103,14 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                };
 
                A53_3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x3>;
+                       clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
                        i-cache-size = <0x8000>;
                        i-cache-line-size = <64>;
@@ -112,12 +119,14 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                };
 
                A72_0: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72";
                        reg = <0x0 0x100>;
+                       clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
                        i-cache-size = <0xC000>;
                        i-cache-line-size = <64>;
@@ -126,14 +135,17 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&A72_L2>;
+                       operating-points-v2 = <&a72_opp_table>;
                };
 
                A72_1: cpu@101 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72";
                        reg = <0x0 0x101>;
+                       clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
                        next-level-cache = <&A72_L2>;
+                       operating-points-v2 = <&a72_opp_table>;
                };
 
                A53_L2: l2-cache0 {
@@ -155,6 +167,66 @@
                };
        };
 
+       a53_opp_table: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-896000000 {
+                       opp-hz = /bits/ 64 <896000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1104000000 {
+                       opp-hz = /bits/ 64 <1104000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
+       a72_opp_table: opp-table-1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1056000000 {
+                       opp-hz = /bits/ 64 <1056000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1296000000 {
+                       opp-hz = /bits/ 64 <1296000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1596000000 {
+                       opp-hz = /bits/ 64 <1596000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
        gic: interrupt-controller@51a00000 {
                compatible = "arm,gic-v3";
                reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */