arm64: dts: Update cache properties for ti

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-24-pierre.gondois@arm.com

diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi
index cea2cc7..acc7f8a 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am625.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi
@@ -146,6 +146,7 @@
 
        L2_0: l2-cache0 {
                compatible = "cache";
+               cache-unified;
                cache-level = <2>;
                cache-size = <0x40000>;
                cache-line-size = <64>;

diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
index 331d89f..9734549 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
@@ -95,6 +95,7 @@
 
        L2_0: l2-cache0 {
                compatible = "cache";
+               cache-unified;
                cache-level = <2>;
                cache-size = <0x40000>;
                cache-line-size = <64>;

diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
index 8a76f48..7a6eede 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
@@ -58,6 +58,7 @@
        L2_0: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
                cache-size = <0x40000>;
                cache-line-size = <64>;
                cache-sets = <256>;

diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi
index a892579..4cc329b 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am654.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi
@@ -93,6 +93,7 @@
        L2_0: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
                cache-size = <0x80000>;
                cache-line-size = <64>;
                cache-sets = <512>;
@@ -102,6 +103,7 @@
        L2_1: l2-cache1 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
                cache-size = <0x80000>;
                cache-line-size = <64>;
                cache-sets = <512>;

diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index b6da045..d74f86b 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -84,6 +84,7 @@
        L2_0: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
                cache-size = <0x100000>;
                cache-line-size = <64>;
                cache-sets = <1024>;

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 0e23886..6975cae 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -86,6 +86,7 @@
        L2_0: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
                cache-size = <0x100000>;
                cache-line-size = <64>;
                cache-sets = <1024>;

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index 7b930a8..78295ee 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -69,6 +69,7 @@
 
        L2_0: l2-cache0 {
                compatible = "cache";
+               cache-unified;
                cache-level = <2>;
                cache-size = <0x100000>;
                cache-line-size = <64>;