drm/i915/dg2: Skip shared DPLL handling

DG2 has no shared DPLL's or DDI clock muxing.  The Port PLL is embedded
within the PHY.

Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-13-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 834d285..4c66620 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3471,7 +3471,8 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
                 * Enable sequence steps 1-7 on bigjoiner master
                 */
                intel_encoders_pre_pll_enable(state, master);
-               intel_enable_shared_dpll(master_crtc_state);
+               if (master_crtc_state->shared_dpll)
+                       intel_enable_shared_dpll(master_crtc_state);
                intel_encoders_pre_enable(state, master);
 
                /* and DSC on slave */
@@ -8630,10 +8631,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
        PIPE_CONF_CHECK_BOOL(double_wide);
 
-       PIPE_CONF_CHECK_P(shared_dpll);
+       if (dev_priv->dpll.mgr)
+               PIPE_CONF_CHECK_P(shared_dpll);
 
        /* FIXME do the readout properly and get rid of this quirk */
-       if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+       if (dev_priv->dpll.mgr && !PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
                PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
                PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
                PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
@@ -8665,7 +8667,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
                PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
                PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
                PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+       }
 
+       if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
                PIPE_CONF_CHECK_X(dsi_pll.ctrl);
                PIPE_CONF_CHECK_X(dsi_pll.div);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9b5324d..d180aec 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4462,7 +4462,10 @@ void intel_shared_dpll_init(struct drm_device *dev)
        const struct dpll_info *dpll_info;
        int i;
 
-       if (IS_ALDERLAKE_P(dev_priv))
+       if (IS_DG2(dev_priv))
+               /* No shared DPLLs on DG2; port PLLs are part of the PHY */
+               dpll_mgr = NULL;
+       else if (IS_ALDERLAKE_P(dev_priv))
                dpll_mgr = &adlp_pll_mgr;
        else if (IS_ALDERLAKE_S(dev_priv))
                dpll_mgr = &adls_pll_mgr;