tu: Implement extendedDynamicState3AlphaToCoverageEnable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18912>

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 60ddfa0ba9c2c2496aea3560060174c2abb3708b..b7071158e8250492c5a318635d998435069afa01 100644 (file)
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -3198,6 +3198,23 @@ tu_CmdSetRasterizationSamplesEXT(VkCommandBuffer commandBuffer,
    tu6_update_msaa_samples(cmd, rasterizationSamples);
 }
 
+VKAPI_ATTR void VKAPI_CALL
+tu_CmdSetAlphaToCoverageEnableEXT(VkCommandBuffer commandBuffer,
+                                  VkBool32 alphaToCoverageEnable)
+{
+   TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+
+   cmd->state.alpha_to_coverage = alphaToCoverageEnable;
+   cmd->state.rb_blend_cntl =
+      (cmd->state.rb_blend_cntl & ~A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
+      COND(alphaToCoverageEnable, A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE);
+   cmd->state.sp_blend_cntl =
+      (cmd->state.sp_blend_cntl & ~A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
+      COND(alphaToCoverageEnable, A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE);
+
+   cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
+}
+
 static void
 tu_flush_for_access(struct tu_cache_state *cache,
                     enum tu_cmd_access_mask src_mask,
@@ -4440,8 +4457,14 @@ tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
                  : A6XX_LATE_Z;
    }
 
-   if ((cmd->state.pipeline->lrz.force_late_z &&
-        !cmd->state.pipeline->lrz.fs.force_early_z) || !depth_test_enable)
+   bool force_late_z = cmd->state.pipeline->lrz.force_late_z ||
+      /* If enabled dynamically, alpha-to-coverage can behave like a discard.
+       */
+      ((cmd->state.pipeline->dynamic_state_mask &
+        BIT(TU_DYNAMIC_STATE_ALPHA_TO_COVERAGE)) &&
+       cmd->state.alpha_to_coverage);
+   if ((force_late_z && !cmd->state.pipeline->lrz.fs.force_early_z) ||
+       !depth_test_enable)
       zmode = A6XX_LATE_Z;
 
    /* User defined early tests take precedence above all else */
@@ -4465,7 +4488,14 @@ tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
        BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE))
       color_write_enable &= cmd->state.color_write_enable;
 
-   for (unsigned i = 0; i < pipeline->blend.num_rts; i++) {
+   unsigned num_rts = pipeline->blend.num_rts;
+   if (num_rts == 0 &&
+       (pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_ALPHA_TO_COVERAGE)) &&
+       cmd->state.alpha_to_coverage) {
+      num_rts = 1;
+   }
+
+   for (unsigned i = 0; i < num_rts; i++) {
       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
       if (color_write_enable & BIT(i)) {
          tu_cs_emit(cs, cmd->state.rb_mrt_control[i] |
@@ -4482,8 +4512,8 @@ tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
    if (!(cmd->state.logic_op_enabled && cmd->state.rop_reads_dst))
       blend_enable_mask &= cmd->state.pipeline_blend_enable;
 
-   tu_cs_emit_regs(cs, A6XX_SP_FS_OUTPUT_CNTL1(.mrt = pipeline->blend.num_rts));
-   tu_cs_emit_regs(cs, A6XX_RB_FS_OUTPUT_CNTL1(.mrt = pipeline->blend.num_rts));
+   tu_cs_emit_regs(cs, A6XX_SP_FS_OUTPUT_CNTL1(.mrt = num_rts));
+   tu_cs_emit_regs(cs, A6XX_RB_FS_OUTPUT_CNTL1(.mrt = num_rts));
    tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
    tu_cs_emit(cs, cmd->state.sp_blend_cntl |
                   (A6XX_SP_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) &

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.h b/src/freedreno/vulkan/tu_cmd_buffer.h
index e47e0084670dbcf6ee1af4ac737846274528b52b..29f6efa70c31ce314f6c3d232e32aaf09781ec68 100644 (file)
--- a/src/freedreno/vulkan/tu_cmd_buffer.h
+++ b/src/freedreno/vulkan/tu_cmd_buffer.h
@@ -345,6 +345,7 @@ struct tu_cmd_state
    uint32_t color_write_enable;
    bool logic_op_enabled;
    bool rop_reads_dst;
+   bool alpha_to_coverage;
    enum pc_di_primtype primtype;
    bool primitive_restart_enable;
    bool tess_upper_left_domain_origin;

diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c
index 8f3fe44ef3d2e76e9281e504568150ed60e021b5..2add8d05b5ae0b2e85ae2272ec10e18f65d5bcbb 100644 (file)
--- a/src/freedreno/vulkan/tu_device.c
+++ b/src/freedreno/vulkan/tu_device.c
@@ -768,7 +768,7 @@ tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
          features->extendedDynamicState3LogicOpEnable = true;
          features->extendedDynamicState3SampleMask = true;
          features->extendedDynamicState3RasterizationSamples = true;
-         features->extendedDynamicState3AlphaToCoverageEnable = false;
+         features->extendedDynamicState3AlphaToCoverageEnable = true;
          features->extendedDynamicState3AlphaToOneEnable = false;
          features->extendedDynamicState3DepthClipNegativeOneToOne = false;
          features->extendedDynamicState3RasterizationStream = false;

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 4cd13a333e3ed59242580894b5de4b3ccb366b8b..020c0d4b379129b995ed4d008678c0e89a865554 100644 (file)
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -3745,6 +3745,15 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
       case VK_DYNAMIC_STATE_RASTERIZATION_SAMPLES_EXT:
          pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_MSAA_SAMPLES);
          break;
+      case VK_DYNAMIC_STATE_ALPHA_TO_COVERAGE_ENABLE_EXT:
+         pipeline->dynamic_state_mask |=
+            BIT(TU_DYNAMIC_STATE_ALPHA_TO_COVERAGE) |
+            BIT(TU_DYNAMIC_STATE_BLEND);
+         pipeline->blend.rb_blend_cntl_mask &=
+            ~A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
+         pipeline->blend.sp_blend_cntl_mask &=
+            ~A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
+         break;
       default:
          assert(!"unsupported dynamic state");
          break;
@@ -3839,7 +3848,8 @@ tu_pipeline_builder_parse_libraries(struct tu_pipeline_builder *builder,
             BIT(TU_DYNAMIC_STATE_LOGIC_OP) |
             BIT(TU_DYNAMIC_STATE_LOGIC_OP_ENABLE) |
             BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE) |
-            BIT(TU_DYNAMIC_STATE_MSAA_SAMPLES);
+            BIT(TU_DYNAMIC_STATE_MSAA_SAMPLES) |
+            BIT(TU_DYNAMIC_STATE_ALPHA_TO_COVERAGE);
       }
 
       if ((library->state &
@@ -4432,9 +4442,14 @@ tu_pipeline_builder_parse_multisample_and_color_blend(
       builder->use_color_attachments ? builder->create_info->pColorBlendState
                                      : &dummy_blend_info;
 
+   bool alpha_to_coverage =
+      !(pipeline->dynamic_state_mask &
+        BIT(TU_DYNAMIC_STATE_ALPHA_TO_COVERAGE)) &&
+      msaa_info->alphaToCoverageEnable;
+
    bool no_earlyz = builder->depth_attachment_format == VK_FORMAT_S8_UINT ||
       /* alpha to coverage can behave like a discard */
-      msaa_info->alphaToCoverageEnable;
+      alpha_to_coverage;
    pipeline->lrz.force_late_z |= no_earlyz;
 
    pipeline->output.subpass_feedback_loop_color =
@@ -4475,7 +4490,7 @@ tu_pipeline_builder_parse_multisample_and_color_blend(
                             &pipeline->blend.rop_reads_dst,
                             &pipeline->output.color_bandwidth_per_sample);
 
-   if (msaa_info->alphaToCoverageEnable && pipeline->blend.num_rts == 0) {
+   if (alpha_to_coverage && pipeline->blend.num_rts == 0) {
       /* In addition to changing the *_OUTPUT_CNTL1 registers, this will also
        * make sure we disable memory writes for MRT0 rather than using
        * whatever setting was leftover.

diff --git a/src/freedreno/vulkan/tu_pipeline.h b/src/freedreno/vulkan/tu_pipeline.h
index 3d4b95c7887998dbc1cf774edb9df1404f48ae33..74283d6a0dbcc7b3f7262f157fcfeba003a66a8f 100644 (file)
--- a/src/freedreno/vulkan/tu_pipeline.h
+++ b/src/freedreno/vulkan/tu_pipeline.h
@@ -38,6 +38,7 @@ enum tu_dynamic_state
    TU_DYNAMIC_STATE_POLYGON_MODE,
    TU_DYNAMIC_STATE_TESS_DOMAIN_ORIGIN,
    TU_DYNAMIC_STATE_MSAA_SAMPLES,
+   TU_DYNAMIC_STATE_ALPHA_TO_COVERAGE,
    /* re-use the line width enum as it uses GRAS_SU_CNTL: */
    TU_DYNAMIC_STATE_RAST = VK_DYNAMIC_STATE_LINE_WIDTH,
 };