[AArch64] Fix test failures on elf configuration

This patch fixed those failures on elf configuration by:

   * Improve the ILP32 target selector "aarch64_choose_ilp32_emul",
     makes it more robust. Target triples copied from configure.tgt

   * Updated emit-relocs-86/-overflow.d to use aarch64_choose_ilp32_emul
     which is following what have done with emit-relocs-28.

   * Those instruction encoding mismatch is because those encoding
     contains pc-relative address. As for elf, we may have different
     start address. relaxed encodind check, especially for
     aarch64-farcall-b/bl-plt, as the main purpose of those check are
     ELF text/data layout, we just want to make sure veneer to plt stub
     is generated.

2015-08-12  Jiong Wang  <jiong.wang@arm.com>

ld/testsuite/
  * ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Support all
  four triple shapes: aarch64-*-linux*, aarch64-*-elf,
  aarch64_be-*-linux*, aarch64_be-*-elf.
  * ld-aarch64/emit-relocs-86.d: Use aarch64_choose_ilp32_emul.
  * ld-aarch64/emit-relocs-86-overflow.d: Likewise.
  * ld-aarch64/ld-aarch64/farcall-b-plt.d: Relax instrucion encoding
  check when they reflect address.
  * ld-aarch64/ld-aarch64/farcall-bl-plt.d: Likewise.

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index f1c5d82..354e0fb 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2015-08-12  Jiong Wang  <jiong.wang@arm.com>
+
+       * ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Support all
+       four triple shape: aarch64-*-linux*, aarch64-*-elf,
+       aarch64_be-*-linux*, aarch64_be-*-elf.
+       * ld-aarch64/emit-relocs-86.d: Use aarch64_choose_ilp32_emul.
+       * ld-aarch64/emit-relocs-86-overflow.d: Likewise.
+       * ld-aarch64/ld-aarch64/farcall-b-plt.d: Relax instrucion encoding
+       check when they reflect address.
+       * ld-aarch64/ld-aarch64/farcall-bl-plt.d: Likewise.
+
 2015-08-12  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
        * ld-aarch64/aarch64-elf.exp: Rename relocs-257-symbolic-func to

diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index f2ce6e8..15247dc 100644 (file)
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -46,10 +46,17 @@ set aarch64elftests {
 }
 
 proc aarch64_choose_ilp32_emul {} {
-    if [istarget aarch64_be*-*-*] then {
+    if [istarget aarch64-*-linux*] then {
+        return "aarch64linux32"
+    } elseif [istarget aarch64-*-elf] {
+        return "aarch64elf32"
+    } elseif [istarget aarch64_be-*-linux*] {
+        return "aarch64linux32b"
+    } elseif [istarget aarch64_be-*-elf] {
         return "aarch64elf32b"
     } else {
-        return "aarch64linux32"
+      perror "Unknown target triple."
+      exit 1
     }
 }
 

diff --git a/ld/testsuite/ld-aarch64/emit-relocs-86-overflow.d b/ld/testsuite/ld-aarch64/emit-relocs-86-overflow.d
index fb727b3..a9781a9 100644 (file)
--- a/ld/testsuite/ld-aarch64/emit-relocs-86-overflow.d
+++ b/ld/testsuite/ld-aarch64/emit-relocs-86-overflow.d
@@ -1,5 +1,5 @@
 #source: emit-relocs-86-overflow.s
 #as: -mabi=ilp32
-#ld: -m aarch64linux32 -e0 --emit-relocs
+#ld: -m [aarch64_choose_ilp32_emul] -e0 --emit-relocs
 #objdump: -dr
 #error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 against symbol `v2' .*

diff --git a/ld/testsuite/ld-aarch64/emit-relocs-86.d b/ld/testsuite/ld-aarch64/emit-relocs-86.d
index c0f5aca..0047785 100644 (file)
--- a/ld/testsuite/ld-aarch64/emit-relocs-86.d
+++ b/ld/testsuite/ld-aarch64/emit-relocs-86.d
@@ -1,8 +1,8 @@
 #source: emit-relocs-86.s
 #as: -mabi=ilp32
-#ld: -m aarch64linux32 -e0 --emit-relocs
+#ld: -m [aarch64_choose_ilp32_emul] -e0 --emit-relocs
 #objdump: -dr
 #...
-00400094 <.text>:
-  400094:      11001134        add     w20, w9, #0x4
-                       400094: R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12     v2
+.* <\.text>:
+  .*:  .*      add     w20, w9, #0x4
+                       .*: R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 v2

diff --git a/ld/testsuite/ld-aarch64/farcall-b-plt.d b/ld/testsuite/ld-aarch64/farcall-b-plt.d
index 9e2c891..49c82eb 100644 (file)
--- a/ld/testsuite/ld-aarch64/farcall-b-plt.d
+++ b/ld/testsuite/ld-aarch64/farcall-b-plt.d
@@ -7,32 +7,32 @@
 
 Disassembly of section .plt:
 
-.* <foo@plt-0x20>:
+.* <foo@plt.*>:
 .*:    a9bf7bf0        stp     x16, x30, \[sp,#-16\]!
-.*:    90040090        adrp    x16, 8010000 <__foo_veneer\+.*>
-.*:    f941f611        ldr     x17, \[x16,#1000\]
-.*:    910fa210        add     x16, x16, #0x3e8
+.*:    .*      adrp    x16, .* <__foo_veneer\+.*>
+.*:    .*      ldr     x17, \[x16,#.*\]
+.*:    .*      add     x16, x16, #.*
 .*:    d61f0220        br      x17
 .*:    d503201f        nop
 .*:    d503201f        nop
 .*:    d503201f        nop
 
 .* <foo@plt>:
-.*:    90040090        adrp    x16, 8010000 <__foo_veneer\+.*>
-.*:    f941fa11        ldr     x17, \[x16,#1008\]
-.*:    910fc210        add     x16, x16, #0x3f0
+.*:    .*      adrp    x16, .* <__foo_veneer\+.*>
+.*:    .*      ldr     x17, \[x16,#.*\]
+.*:    .*      add     x16, x16, #.*
 .*:    d61f0220        br      x17
 
 Disassembly of section .text:
 
 .* <_start>:
        ...
-.*:    14000003        b       80002c8 <__foo_veneer>
+.*:    .*      b       .* <__foo_veneer>
 .*:    d65f03c0        ret
-.*:    14000007        b       80002e0 <__foo_veneer\+.*>
+.*:    .*      b       .* <__foo_veneer\+.*>
 
 .* <__foo_veneer>:
-.*:    90fc0010        adrp    x16, 0 <foo@plt-0x2b0>
-.*:    910ac210        add     x16, x16, #0x2b0
+.*:    .*      adrp    x16, 0 <foo@plt.*>
+.*:    .*      add     x16, x16, #.*
 .*:    d61f0200        br      x16
        ...

diff --git a/ld/testsuite/ld-aarch64/farcall-bl-plt.d b/ld/testsuite/ld-aarch64/farcall-bl-plt.d
index 205a810..457a4fa 100644 (file)
--- a/ld/testsuite/ld-aarch64/farcall-bl-plt.d
+++ b/ld/testsuite/ld-aarch64/farcall-bl-plt.d
@@ -7,32 +7,32 @@
 
 Disassembly of section .plt:
 
-.* <foo@plt-0x20>:
+.* <foo@plt.*>:
 .*:    a9bf7bf0        stp     x16, x30, \[sp,#-16\]!
-.*:    90040090        adrp    x16, 8010000 <__foo_veneer\+.*>
-.*:    f941f611        ldr     x17, \[x16,#1000\]
-.*:    910fa210        add     x16, x16, #0x3e8
+.*:    .*      adrp    x16, .* <__foo_veneer\+.*>
+.*:    .*      ldr     x17, \[x16,#.*\]
+.*:    .*      add     x16, x16, #.*
 .*:    d61f0220        br      x17
 .*:    d503201f        nop
 .*:    d503201f        nop
 .*:    d503201f        nop
 
 .* <foo@plt>:
-.*:    90040090        adrp    x16, 8010000 <__foo_veneer\+.*>
-.*:    f941fa11        ldr     x17, \[x16,#1008\]
-.*:    910fc210        add     x16, x16, #0x3f0
+.*:    .*      adrp    x16, .* <__foo_veneer\+.*>
+.*:    .*      ldr     x17, \[x16,#.*\]
+.*:    .*      add     x16, x16, #.*
 .*:    d61f0220        br      x17
 
 Disassembly of section .text:
 
 .* <_start>:
        ...
-.*:    94000003        bl      80002c8 <__foo_veneer>
+.*:    .*      bl      .* <__foo_veneer>
 .*:    d65f03c0        ret
-.*:    14000007        b       80002e0 <__foo_veneer\+.*>
+.*:    .*      b       .* <__foo_veneer\+.*>
 
 .* <__foo_veneer>:
-.*:    90fc0010        adrp    x16, 0 <foo@plt-0x2b0>
-.*:    910ac210        add     x16, x16, #0x2b0
+.*:    .*      adrp    x16, 0 <foo@plt.*>
+.*:    .*      add     x16, x16, #.*
 .*:    d61f0200        br      x16
        ...