releases in "stable" maintenance trees.
Examples:
- U-Boot v2009.11 - Release November 2009
+ U-Boot v2009.11 - Release November 2009
U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree
U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
- CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
+ CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
CONFIG_CMD_PCI * pciinfo
CONFIG_CMD_PCMCIA * PCMCIA support
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
Define a default value for the IP address to use for
the default Ethernet interface, in case this is not
determined through e.g. bootp.
+ (Environment variable "ipaddr")
- Server IP address:
CONFIG_SERVERIP
Defines a default value for the IP address of a TFTP
server to contact when using the "tftboot" command.
+ (Environment variable "serverip")
CONFIG_KEEP_SERVERADDR
Keeps the server's MAC address, in the env 'serveraddr'
for passing to bootargs (like Linux's netconsole option)
+- Gateway IP address:
+ CONFIG_GATEWAYIP
+
+ Defines a default value for the IP address of the
+ default router where packets to other networks are
+ sent to.
+ (Environment variable "gatewayip")
+
+- Subnet mask:
+ CONFIG_NETMASK
+
+ Defines a default value for the subnet mask (or
+ routing prefix) which is used to determine if an IP
+ address belongs to the local subnet or needs to be
+ forwarded through a router.
+ (Environment variable "netmask")
+
- Multicast TFTP Mode:
CONFIG_MCAST_TFTP
CONFIG_I2C_MULTI_BUS
This option allows the use of multiple I2C buses, each of which
- must have a controller. At any point in time, only one bus is
- active. To switch to a different bus, use the 'i2c dev' command.
+ must have a controller. At any point in time, only one bus is
+ active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based.
CONFIG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
- when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
+ when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
is set, specify a list of bus-device pairs. Otherwise, specify
a 1D array of device addresses
e.g.
#undef CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
+ #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
- #define CONFIG_I2C_MULTI_BUS
+ #define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
Enables a hardware SPI driver for general-purpose reads
and writes. As with CONFIG_SOFT_SPI, the board configuration
must define a list of chip-select function pointers.
- Currently supported on some MPC8xxx processors. For an
+ Currently supported on some MPC8xxx processors. For an
example, see include/configs/mpc8349emds.h.
CONFIG_MXC_SPI
13 common/image.c Start multifile image verification
14 common/image.c No initial ramdisk, no multifile, continue.
- 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
+ 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
-30 arch/powerpc/lib/board.c Fatal error, hang the system
-31 post/post.c POST test failed, detected by post_output_backlog()
See also: doc/README.Modem
+Board initialization settings:
+------------------------------
+
+During Initialization u-boot calls a number of board specific functions
+to allow the preparation of board specific prerequisites, e.g. pin setup
+before drivers are initialized. To enable these callbacks the
+following configuration macros have to be defined. Currently this is
+architecture specific, so please check arch/your_architecture/lib/board.c
+typically in board_init_f() and board_init_r().
+
+- CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
+- CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
+- CONFIG_BOARD_LATE_INIT: Call board_late_init()
+- CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
Configuration Settings:
-----------------------
used) must be put below this limit, unless "bootm_low"
enviroment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
- and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
+ and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
variable "bootm_mapsize" will override the value of
CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
aligned to an erase block boundary.
- CONFIG_ENV_RANGE (optional):
- CONFIG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should
- be set to that address. Otherwise, it should be set to the
+ be set to that address. Otherwise, it should be set to the
same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR
is typically relocated on 36-bit builds. It is recommended
that this macro be defined via the _HIGH and _LOW macros:
kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
bootm_mapsize.
- bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
+ bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
This variable is given as a hexadecimal number and it
defines the size of the memory region starting at base
address bootm_low that is accessible by the Linux kernel
boards currenlty use other variables for these purposes, and some
boards use these variables for other purposes.
-Image File Name RAM Address Flash Location
------ --------- ----------- --------------
-u-boot u-boot u-boot_addr_r u-boot_addr
-Linux kernel bootfile kernel_addr_r kernel_addr
-device tree blob fdtfile fdt_addr_r fdt_addr
-ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr
+Image File Name RAM Address Flash Location
+----- --------- ----------- --------------
+u-boot u-boot u-boot_addr_r u-boot_addr
+Linux kernel bootfile kernel_addr_r kernel_addr
+device tree blob fdtfile fdt_addr_r fdt_addr
+ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr
The following environment variables may be used and automatically
updated by the network boot commands ("bootp" and "rarpboot"),
is raised.
If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
-will be programmed into hardware as part of the initialization process. This
+will be programmed into hardware as part of the initialization process. This
may be skipped by setting the appropriate 'ethmacskip' environment variable.
The naming convention is as follows:
"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+ debug("Enable clock domain - %p\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+ debug("Enable clock module - %p\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
u32 reg;
reg = readl(&pmc->pmc_scratch20);
- debug("pmc->pmc_scratch20 (ODMData) = 0x%08lX\n", reg);
+ debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
/* bits 31:28 in OdmData are used for RAM size */
switch ((reg) >> 28) {
}
#endif
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
#define readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define readl(addr) \
- ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; })
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
#define writeb(b, addr) \
(void)((*(volatile unsigned char *) (addr)) = (b))
if (br_env)
baudrate = simple_strtoul(br_env, NULL, 10);
- debug("%s: idx %d, baudrate %d\n", __func__, idx, baudrate);
+ debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate);
}
/* calculate divisor for setting PSC CTUR and CTLR registers */
pic->gcr = MPC86xx_PICGCR_MODE;
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
- debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n",
+ debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
(get_tbclk() / 1000000),
*decrementer_count);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
- debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
+ debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
- debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2);
+ debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
- debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3);
+ debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
- debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8);
+ debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
#endif
#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
- debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9);
+ debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
#endif
pic->ctpr = 0; /* 40080 clear current task priority register */
/* Bottom 2 bits up to the top. */
bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
bsize <<= 24ULL;
- debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+ debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
return bsize;
}
/* Bottom 5 bits up to the top. */
bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
bsize <<= 27ULL;
- debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+ debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
return bsize;
}
bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
- debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
+ debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
return bsize;
}
break;
}
- debug("tr0: %x\n", tr0);
+ debug("tr0: %lx\n", tr0);
mtsdram(SDRAM0_TR0, tr0);
}
}
tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
- debug("tr1: %x\n", tr1);
+ debug("tr1: %lx\n", tr1);
/*
* program SDRAM Timing Register 1 TR1
num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
- debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
+ debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
num_row_addr, num_col_addr, num_banks);
/*
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
- debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
- dimm_num, i, ctrl_bank_num[dimm_num]+i,
- bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
+ debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
+ "bank_size_bytes=%ld\n",
+ dimm_num, i,
+ ctrl_bank_num[dimm_num] + i,
+ bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
}
}
}
bank_parms[sorted_bank_num[bx_cr_num]].cr;
mtdcr(SDRAM0_CFGDATA, temp);
bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
- debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
+ debug("SDRAM0_B%ldCR=0x%08lx\n",
+ sorted_bank_num[bx_cr_num], temp);
}
}
mtsdram(SDRAM_RQDC, rqdc_reg);
mtsdram(SDRAM_RFDC, rfdc_reg);
- debug("RQDC: 0x%08X\n", rqdc_reg);
- debug("RFDC: 0x%08X\n", rfdc_reg);
+ debug("RQDC: 0x%08lX\n", rqdc_reg);
+ debug("RFDC: 0x%08lX\n", rfdc_reg);
/* if something passed, then return the size of the largest window */
if (passed != 0) {
SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
mfsdram(SDRAM_RQDC, rqdc_reg);
- debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
+ debug("*** best_result: read value SDRAM_RQDC 0x%08lx\n",
rqdc_reg);
#if defined(CONFIG_DDR_RFDC_FIXED)
#endif /* CONFIG_DDR_RFDC_FIXED */
mfsdram(SDRAM_RFDC, rfdc_reg);
- debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
+ debug("*** best_result: read value SDRAM_RFDC 0x%08lx\n",
rfdc_reg);
mfsdram(SDRAM_RDCC, val);
debug("*** SDRAM_RDCC 0x%08x\n", val);
*/
pcie_dmer_disable ();
- debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
+ debug("%s: cfg_data=%p offset=%08x\n", __func__,
+ hose->cfg_data, offset);
switch (len) {
case 1:
*val = in_8(hose->cfg_data + offset);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
- debug("DDR0_09=0x%08lx\n", val);
+ debug("DDR0_09=0x%08x\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
- debug("DDR0_22=0x%08lx\n", val);
+ debug("DDR0_22=0x%08x\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
- debug("DDR0_17=0x%08lx\n", val);
+ debug("DDR0_17=0x%08x\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
- debug("DDR0_18=0x%08lx\n", val);
+ debug("DDR0_18=0x%08x\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
- debug("DDR0_19=0x%08lx\n", val);
+ debug("DDR0_19=0x%08x\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
printf("Install at least one DDR2 DIMM.\n\n");
spd_ddr_init_hang();
}
- debug("Total number of ranks = %d\n", *ranks);
+ debug("Total number of ranks = %ld\n", *ranks);
}
/*------------------------------------------------------------------
if (dimm_ranks[dimm_num]) {
cycle_time =
get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
- debug("cycle_time=%d ps\n", cycle_time);
+ debug("cycle_time=%ld ps\n", cycle_time);
if (cycle_time > (calc_cycle_time + 10)) {
/*
}
}
}
- debug("Number of rows = %d\n", *rows);
- debug("Number of columns = %d\n", *cols);
- debug("Number of banks = %d\n", *banks);
- debug("Data width = %d\n", *width);
+ debug("Number of rows = %ld\n", *rows);
+ debug("Number of columns = %ld\n", *cols);
+ debug("Number of banks = %ld\n", *banks);
+ debug("Data width = %ld\n", *width);
if (*rows > 14) {
printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
*rows);
/*------------------------------------------------------------------
* Get the board configuration info.
*-----------------------------------------------------------------*/
- debug("sdram_freq = %d\n", sdram_freq);
+ debug("sdram_freq = %ld\n", sdram_freq);
/*------------------------------------------------------------------
* Handle the timing. We need to find the worst case timing of all
get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
tcyc_addr[cas_index]));
- debug("cas_index = %d: cycle_time_ps = %d\n",
+ debug("cas_index = %ld: cycle_time_ps = %ld\n",
cas_index, cycle_time_ps);
/*
* DDR2 devices use the following bitmask for CAS latency:
cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
- debug("cycle_2_0_clk = %d\n", cycle_2_0_clk);
- debug("cycle_3_0_clk = %d\n", cycle_3_0_clk);
- debug("cycle_4_0_clk = %d\n", cycle_4_0_clk);
- debug("cycle_5_0_clk = %d\n", cycle_5_0_clk);
+ debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
+ debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
+ debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
+ debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
*cas_latency = 2;
cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
spd_ddr_init_hang();
}
- debug("CAS latency = %d\n", *cas_latency);
+ debug("CAS latency = %ld\n", *cas_latency);
mtsdram(DDR0_03, ddr0_03);
}
t_rtp_ps = max(t_rtp_ps, ps);
}
}
- debug("t_rc_ps = %d\n", t_rc_ps);
+ debug("t_rc_ps = %ld\n", t_rc_ps);
t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rrd_ps = %d\n", t_rrd_ps);
+ debug("t_rrd_ps = %ld\n", t_rrd_ps);
t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rtp_ps = %d\n", t_rtp_ps);
+ debug("t_rtp_ps = %ld\n", t_rtp_ps);
t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
DDR0_04_TRRD_ENCODE(t_rrd_clk) |
t_ras_ps = max(t_ras_ps, ps);
}
}
- debug("t_rp_ps = %d\n", t_rp_ps);
+ debug("t_rp_ps = %ld\n", t_rp_ps);
t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
- debug("t_ras_ps = %d\n", t_ras_ps);
+ debug("t_ras_ps = %ld\n", t_ras_ps);
t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
t_rfc_ps = max(t_rfc_ps, ps);
}
}
- debug("t_wtr_ps = %d\n", t_wtr_ps);
+ debug("t_wtr_ps = %ld\n", t_wtr_ps);
t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rfc_ps = %d\n", t_rfc_ps);
+ debug("t_rfc_ps = %ld\n", t_rfc_ps);
t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
DDR0_06_TRFC_ENCODE(t_rfc_clk));
unsigned long const t_xsnr_ps = 200000; /* 200 ns */
unsigned long t_xsnr_clk;
- debug("t_xsnr_ps = %d\n", t_xsnr_ps);
+ debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
t_xsnr_clk =
(MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
unsigned long t_ref_clk;
/* Round down t_ras_max_clk and t_ref_clk */
- debug("t_ras_max_ps = %d\n", t_ras_max_ps);
+ debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
- debug("t_ref_ps = %d\n", t_ref_ps);
+ debug("t_ref_ps = %ld\n", t_ref_ps);
t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
DDR0_26_TREF_ENCODE(t_ref_clk));
unsigned long const t_init_ps = 200000000; /* 200 us. init */
unsigned long t_init_clk;
- debug("t_init_ps = %d\n", t_init_ps);
+ debug("t_init_ps = %ld\n", t_init_ps);
t_init_clk =
(MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
t_wr_ps = max(t_wr_ps, ps);
}
}
- debug("t_wr_ps = %d\n", t_wr_ps);
+ debug("t_wr_ps = %ld\n", t_wr_ps);
t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
}
t_rcd_ps = max(t_rcd_ps, ps);
}
}
- debug("t_rcd_ps = %d\n", t_rcd_ps);
+ debug("t_rcd_ps = %ld\n", t_rcd_ps);
t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
}
/* enable exceptions */
enable_interrupts();
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
stdio_init,
console_init_r,
interrupt_init,
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
#if defined(CONFIG_CMD_NET)
#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
+/* Compat with interrupts.c */
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(0)
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(1)
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(2)
+
+#define ETHERNET0_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(0)
+#define ETHERNET1_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(1)
+#define ETHERNET2_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(2)
/* Ethernet GT64260 */
/*
{
cirrus_state_t *p = &s->c_state;
u_int mask = 0xffff;
-#if DEBUG
- char buf[200];
-
- memset (buf, 0, 200);
-#endif
+ char buf[200] = {0};
if (has_ring == -1)
has_ring = 1;
int size_val = 0;
debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
- debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
+ debug("[%s, %d] flash_info = 0x%p ...\n", __func__, __LINE__,
+ flash_info);
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
*/
param = base - (pram << 10);
printf("PARAM: @%08x\n", param);
- debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+ debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
/* clear entire PA ram */
memset((void*)param, 0, (pram << 10));
*/
param = base - (pram << 10);
printf("PARAM: @%08x\n", param);
- debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+ debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
/* clear entire PA ram */
memset((void*)param, 0, (pram << 10));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
return 0;
}
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
return 0;
}
#include <asm/arch/sys_proto.h>
#include <netdev.h>
-#ifndef BOARD_LATE_INIT
-#error "BOARD_LATE_INIT must be set for this board"
+#ifndef CONFIG_BOARD_LATE_INIT
+#error "CONFIG_BOARD_LATE_INIT must be set for this board"
#endif
#ifndef CONFIG_BOARD_EARLY_INIT_F
return 0;
}
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_MXC_SPI
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
- debug("DIU pixval = %lu\n", pixval);
+ debug("DIU pixval = %u\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
return 0;
}
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_S6E63D6
value = addr[0];
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+ debug("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
switch (value) {
case (FPW) INTEL_MANUFACT:
value = addr[1]; /* device ID */
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+ debug("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), value);
switch (value) {
case (FPW) INTEL_ID_28F320J3A:
HPI_HPIA_1 = addr1;
HPI_HPIA_2 = addr2;
- debugX(4, "writing from data=0x%lx to 0x%lx\n",
+ debug("writing from data=0x%lx to 0x%lx\n",
(ulong)data, (ulong)(data+count));
for(i=0; i<count; i++) {
HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff);
HPI_HPID_INC_2 = (u16) (data[i] & 0xffff);
- debugX(4, "hpi_write_inc: data1=0x%x, data2=0x%x\n",
+ debug("hpi_write_inc: data1=0x%x, data2=0x%x\n",
(u16) ((data[i] >> 16) & 0xffff),
(u16) (data[i] & 0xffff));
}
for(i=0; i<count; i++) {
data1 = HPI_HPID_INC_1;
data2 = HPI_HPID_INC_2;
- debugX(4, "hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2);
+ debug("hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2);
buf[i] = (((u32) data1) << 16) | (data2 & 0xffff);
}
u32 test_data[HPI_TEST_CHUNKSIZE];
u32 read_data[HPI_TEST_CHUNKSIZE];
- debugX(2, "hpi_test: activating hpi...");
+ debug("hpi_test: activating hpi...");
hpi_activate();
- debugX(2, "OK.\n");
+ debug("OK.\n");
#if 0
/* Dump the first 1024 bytes
/* HPIA read-write test
*
*/
- debugX(1, "hpi_test: starting HPIA read-write tests...\n");
+ debug("hpi_test: starting HPIA read-write tests...\n");
err |= hpi_write_addr_test(0xdeadc0de);
err |= hpi_write_addr_test(0xbeefd00d);
err |= hpi_write_addr_test(0xabcd1234);
err |= hpi_write_addr_test(0xaaaaaaaa);
if(err) {
- debugX(1, "hpi_test: HPIA read-write tests: *** FAILED ***\n");
+ debug("hpi_test: HPIA read-write tests: *** FAILED ***\n");
return -1;
}
- debugX(1, "hpi_test: HPIA read-write tests: OK\n");
+ debug("hpi_test: HPIA read-write tests: OK\n");
/* read write test using nonincremental data regs
*
*/
- debugX(1, "hpi_test: starting nonincremental tests...\n");
+ debug("hpi_test: starting nonincremental tests...\n");
for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
err |= hpi_read_write_test(i, pattern);
err |= hpi_read_write_test(i, pattern);
if(err) {
- debugX(1, "hpi_test: nonincremental tests *** FAILED ***\n");
+ debug("hpi_test: nonincremental tests *** FAILED ***\n");
return -1;
}
}
- debugX(1, "hpi_test: nonincremental test OK\n");
+ debug("hpi_test: nonincremental test OK\n");
/* read write a chunk of data using nonincremental data regs
*
*/
- debugX(1, "hpi_test: starting nonincremental chunk tests...\n");
+ debug("hpi_test: starting nonincremental chunk tests...\n");
pattern = HPI_TEST_PATTERN;
for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
hpi_write_noinc(i, pattern);
tmp = hpi_read_noinc(i);
if(tmp != pattern) {
- debugX(1, "hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp);
+ debug("hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp);
err = -1;
}
/* stolen from cmd_mem.c */
}
if(err)
return -1;
- debugX(1, "hpi_test: nonincremental chunk test OK\n");
+ debug("hpi_test: nonincremental chunk test OK\n");
#ifdef DO_TINY_TEST
/* small verbose test using autoinc and nonautoinc to compare
*
*/
- debugX(1, "hpi_test: tiny_autoinc_test...\n");
+ debug("hpi_test: tiny_autoinc_test...\n");
hpi_tiny_autoinc_test();
- debugX(1, "hpi_test: tiny_autoinc_test done\n");
+ debug("hpi_test: tiny_autoinc_test done\n");
#endif /* DO_TINY_TEST */
/* $%& write a chunk of data using the autoincremental regs
*
*/
- debugX(1, "hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n",
+ debug("hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n",
((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE),
HPI_TEST_CHUNKSIZE);
i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE);
i++) {
/* generate the pattern data */
- debugX(3, "generating pattern data: ");
+ debug("generating pattern data: ");
for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
- debugX(3, "0x%x ", pattern);
+ debug("0x%x ", pattern);
test_data[ii] = pattern;
read_data[ii] = 0x0; /* zero to be sure */
pattern = ~pattern;
}
}
- debugX(3, "done\n");
+ debug("done\n");
- debugX(2, "Writing autoinc data @ 0x%x\n", i);
+ debug("Writing autoinc data @ 0x%x\n", i);
hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE);
- debugX(2, "Reading autoinc data @ 0x%x\n", i);
+ debug("Reading autoinc data @ 0x%x\n", i);
hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE);
/* compare */
for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
- debugX(3, "hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]);
+ debug("hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]);
if(read_data[ii] != test_data[ii]) {
- debugX(0, "hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]);
+ debug("hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]);
return -1;
}
}
}
- debugX(1, "hpi_test: autoinc test OK\n");
+ debug("hpi_test: autoinc test OK\n");
return 0;
}
0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
};
- debugX(0, "hpi_test: activating hpi...");
+ debug("hpi_test: activating hpi...");
hpi_activate();
- debugX(0, "OK.\n");
+ debug("OK.\n");
while(1) {
led9(1);
- debugX(0, " writing to autoinc...\n");
+ debug(" writing to autoinc...\n");
hpi_write_inc(TINY_AUTOINC_BASE_ADDR,
dummy_data, TINY_AUTOINC_DATA_SIZE);
- debugX(0, " reading from autoinc...\n");
+ debug(" reading from autoinc...\n");
hpi_read_inc(TINY_AUTOINC_BASE_ADDR,
read_data, TINY_AUTOINC_DATA_SIZE);
for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
- debugX(0, " written=0x%x, read(inc)=0x%x\n",
+ debug(" written=0x%x, read(inc)=0x%x\n",
dummy_data[i], read_data[i]);
}
led9(0);
read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2);
if(read_back == addr) {
- debugX(2, " hpi_write_addr_test OK: written=0x%x, read=0x%x\n",
+ debug(" hpi_write_addr_test OK: written=0x%x, read=0x%x\n",
addr, read_back);
return 0;
} else {
- debugX(0, " hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n",
+ debug(" hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n",
addr, read_back);
return -1;
}
read_back = hpi_read_noinc(addr);
if(read_back == data) {
- debugX(2, " hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
+ debug(" hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
return 0;
} else {
- debugX(0, " hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
+ debug(" hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
return -1;
}
0xA03FE024, 0x00000000 /* USB */
};
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
#ifdef CONFIG_MMC
#define LDO_VAUX3_MASK 0x3
return 0;
}
-#endif /* BOARD_LATE_INIT */
+#endif /* CONFIG_BOARD_LATE_INIT */
static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
{
(long *)(CONFIG_SYS_DDR_BASE + size));
size += bank_size;
- debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
+ debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
/* exit if less than one bank */
if(size < DDR_MAX_SIZE_PER_CS) break;
*/
static void set_cs_bounds(short cs, long base, long size)
{
- debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
+ debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
if(size == 0){
im->ddr.csbnds[cs].csbnds = 0x00000000;
} else {
*/
static void set_cs_config(short cs, long config)
{
- debug("Setting config %08x for cs %d\n", config, cs);
+ debug("Setting config %08lx for cs %d\n", config, cs);
im->ddr.cs_config[cs] = config;
SYNC;
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
+
+#ifdef CONFIG_XILINX_AXIEMAC
+ ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+ XILINX_AXIDMA_BASEADDR);
+#endif
+
#ifdef CONFIG_XILINX_EMACLITE
u32 txpp = 0;
u32 rxpp = 0;
lba48 = 1;
}
#endif
- debug ("ide_read dev %d start %LX, blocks %lX buffer at %lX\n",
+ debug("ide_read dev %d start %lX, blocks %lX buffer at %lX\n",
device, blknr, blkcnt, (ulong)buffer);
ide_led (DEVICE_LED(device), 1); /* LED on */
const char *mtd_id;
unsigned int mtd_id_len;
const char *p;
-#ifdef DEBUG
const char *pend;
-#endif
LIST_HEAD(tmp_list);
struct list_head *entry, *n;
u16 num_parts;
#endif
#ifdef DEBUG
-#define USB_DEBUG
-#define USB_HUB_DEBUG
-#endif
-
-#ifdef USB_DEBUG
-#define USB_PRINTF(fmt, args...) printf(fmt , ##args)
+#define USB_DEBUG 1
+#define USB_HUB_DEBUG 1
#else
-#define USB_PRINTF(fmt, args...)
+#define USB_DEBUG 0
+#define USB_HUB_DEBUG 0
#endif
+#define USB_PRINTF(fmt, args...) debug_cond(USB_DEBUG, fmt, ##args)
+#define USB_HUB_PRINTF(fmt, args...) debug_cond(USB_HUB_DEBUG, fmt, ##args)
+
#define USB_BUFSIZ 512
static struct usb_device usb_dev[USB_MAX_DEVICE];
* Probes device for being a hub and configurate it
*/
-#ifdef USB_HUB_DEBUG
-#define USB_HUB_PRINTF(fmt, args...) printf(fmt , ##args)
-#else
-#define USB_HUB_PRINTF(fmt, args...)
-#endif
-
-
static struct usb_hub_device hub_dev[USB_MAX_HUB];
static int usb_hub_index;
#include <part.h>
#include <usb.h>
-#undef USB_STOR_DEBUG
#undef BBB_COMDAT_TRACE
#undef BBB_XPORT_TRACE
#ifdef USB_STOR_DEBUG
-#define USB_STOR_PRINTF(fmt, args...) printf(fmt , ##args)
+#define USB_BLK_DEBUG 1
#else
-#define USB_STOR_PRINTF(fmt, args...)
+#define USB_BLK_DEBUG 0
#endif
+#define USB_STOR_PRINTF(fmt, args...) debug_cond(USB_BLK_DEBUG, fmt, ##args)
+
#include <scsi.h>
/* direction table -- this indicates the direction of the data
* transfer for each command code -- a 1 indicates input
usb_clear_halt(us->pusb_dev, pipe);
us->pusb_dev->status = stat;
if (this_xfer == partial) {
- USB_STOR_PRINTF("bulk transferred with error %X, but data ok\n", us->pusb_dev->status);
+ USB_STOR_PRINTF("bulk transferred with error %lX, but data ok\n", us->pusb_dev->status);
return 0;
}
else
}
USB_STOR_PRINTF("bulk transferred with error");
if (this_xfer == partial) {
- USB_STOR_PRINTF(" %d, but data ok\n",
+ USB_STOR_PRINTF(" %ld, but data ok\n",
us->pusb_dev->status);
return 0;
}
/* if our try counter reaches 0, bail out */
- USB_STOR_PRINTF(" %d, data %d\n",
+ USB_STOR_PRINTF(" %ld, data %d\n",
us->pusb_dev->status, partial);
if (!maxtry--)
return result;
/* long wait for reset */
wait_ms(150);
- USB_STOR_PRINTF("BBB_reset result %d: status %X reset\n", result,
+ USB_STOR_PRINTF("BBB_reset result %d: status %lX reset\n", result,
us->pusb_dev->status);
pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
result = usb_clear_halt(us->pusb_dev, pipe);
/* long wait for reset */
wait_ms(150);
- USB_STOR_PRINTF("BBB_reset result %d: status %X clearing IN endpoint\n",
+ USB_STOR_PRINTF("BBB_reset result %d: status %lX clearing IN endpoint\n",
result, us->pusb_dev->status);
/* long wait for reset */
pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
result = usb_clear_halt(us->pusb_dev, pipe);
wait_ms(150);
- USB_STOR_PRINTF("BBB_reset result %d: status %X"
+ USB_STOR_PRINTF("BBB_reset result %d: status %lX"
" clearing OUT endpoint\n", result,
us->pusb_dev->status);
USB_STOR_PRINTF("BBB_reset done\n");
/* long wait for reset */
wait_ms(1500);
- USB_STOR_PRINTF("CB_reset result %d: status %X"
+ USB_STOR_PRINTF("CB_reset result %d: status %lX"
" clearing endpoint halt\n", result,
us->pusb_dev->status);
usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in));
srb->cmd, srb->cmdlen,
USB_CNTL_TIMEOUT * 5);
USB_STOR_PRINTF("CB_transport: control msg returned %d,"
- " status %X\n", result, us->pusb_dev->status);
+ " status %lX\n", result, us->pusb_dev->status);
/* check the return code for the command */
if (result < 0) {
if (us->pusb_dev->status & USB_ST_STALLED) {
us->pusb_dev->status = status;
}
USB_STOR_PRINTF(" error during command %02X"
- " Stat = %X\n", srb->cmd[0],
+ " Stat = %lX\n", srb->cmd[0],
us->pusb_dev->status);
return result;
}
usb_stor_BBB_reset(us);
return USB_STOR_TRANSPORT_FAILED;
} else if (data_actlen > srb->datalen) {
- USB_STOR_PRINTF("transferred %dB instead of %dB\n",
+ USB_STOR_PRINTF("transferred %dB instead of %ldB\n",
data_actlen, srb->datalen);
return USB_STOR_TRANSPORT_FAILED;
} else if (csw.bCSWStatus == CSWSTATUS_FAILED) {
/* issue the command */
do_retry:
result = usb_stor_CB_comdat(srb, us);
- USB_STOR_PRINTF("command / Data returned %d, status %X\n",
+ USB_STOR_PRINTF("command / Data returned %d, status %lX\n",
result, us->pusb_dev->status);
/* if this is an CBI Protocol, get IRQ */
if (us->protocol == US_PR_CBI) {
/* do we have to issue an auto request? */
/* HERE we have to check the result */
if ((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) {
- USB_STOR_PRINTF("ERROR %X\n", us->pusb_dev->status);
+ USB_STOR_PRINTF("ERROR %lX\n", us->pusb_dev->status);
us->transport_reset(us);
return USB_STOR_TRANSPORT_ERROR;
}
status = usb_stor_CBI_get_status(psrb, us);
if ((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) {
- USB_STOR_PRINTF(" AUTO REQUEST ERROR %d\n",
+ USB_STOR_PRINTF(" AUTO REQUEST ERROR %ld\n",
us->pusb_dev->status);
return USB_STOR_TRANSPORT_ERROR;
}
void print_part_efi(block_dev_desc_t * dev_desc)
{
ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
- gpt_entry **pgpt_pte = NULL;
+ gpt_entry *gpt_pte = NULL;
int i = 0;
if (!dev_desc) {
- printf("%s: Invalid Argument(s)\n", __FUNCTION__);
+ printf("%s: Invalid Argument(s)\n", __func__);
return;
}
/* This function validates AND fills in the GPT header and PTE */
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- gpt_head, pgpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
+ &(gpt_head), &gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
return;
}
- debug("%s: gpt-entry at 0x%08X\n", __FUNCTION__, (unsigned int)*pgpt_pte);
+ debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
printf("Part\tName\t\t\tStart LBA\tEnd LBA\n");
for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) {
- if (is_pte_valid(&(*pgpt_pte)[i])) {
+ if (is_pte_valid(&gpt_pte[i])) {
printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1),
- print_efiname(&(*pgpt_pte)[i]),
- le64_to_int((*pgpt_pte)[i].starting_lba),
- le64_to_int((*pgpt_pte)[i].ending_lba));
+ print_efiname(&gpt_pte[i]),
+ le64_to_int(gpt_pte[i].starting_lba),
+ le64_to_int(gpt_pte[i].ending_lba));
} else {
break; /* Stop at the first non valid PTE */
}
}
/* Remember to free pte */
- if (*pgpt_pte != NULL) {
- debug("%s: Freeing pgpt_pte\n", __FUNCTION__);
- free(*pgpt_pte);
- }
+ free(gpt_pte);
return;
}
disk_partition_t * info)
{
ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
- gpt_entry **pgpt_pte = NULL;
+ gpt_entry *gpt_pte = NULL;
/* "part" argument must be at least 1 */
if (!dev_desc || !info || part < 1) {
- printf("%s: Invalid Argument(s)\n", __FUNCTION__);
+ printf("%s: Invalid Argument(s)\n", __func__);
return -1;
}
/* This function validates AND fills in the GPT header and PTE */
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- gpt_head, pgpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
+ &(gpt_head), &gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
return -1;
}
/* The ulong casting limits the maximum disk size to 2 TB */
- info->start = (ulong) le64_to_int((*pgpt_pte)[part - 1].starting_lba);
+ info->start = (ulong) le64_to_int(gpt_pte[part - 1].starting_lba);
/* The ending LBA is inclusive, to calculate size, add 1 to it */
- info->size = ((ulong)le64_to_int((*pgpt_pte)[part - 1].ending_lba) + 1)
+ info->size = ((ulong)le64_to_int(gpt_pte[part - 1].ending_lba) + 1)
- info->start;
info->blksz = GPT_BLOCK_SIZE;
sprintf((char *)info->name, "%s",
- print_efiname(&(*pgpt_pte)[part - 1]));
+ print_efiname(&gpt_pte[part - 1]));
sprintf((char *)info->type, "U-Boot");
- debug("%s: start 0x%lX, size 0x%lX, name %s", __FUNCTION__,
+ debug("%s: start 0x%lX, size 0x%lX, name %s", __func__,
info->start, info->size, info->name);
/* Remember to free pte */
- if (*pgpt_pte != NULL) {
- debug("%s: Freeing pgpt_pte\n", __FUNCTION__);
- free(*pgpt_pte);
- }
+ free(gpt_pte);
return 0;
}
unsigned long long lastlba;
if (!dev_desc || !pgpt_head) {
- printf("%s: Invalid Argument(s)\n", __FUNCTION__);
+ printf("%s: Invalid Argument(s)\n", __func__);
return 0;
}
le32_to_int(pgpt_head->partition_entry_array_crc32),
calc_crc32);
- if (*pgpt_pte != NULL) {
- free(*pgpt_pte);
- }
+ free(*pgpt_pte);
return 0;
}
gpt_entry *pte = NULL;
if (!dev_desc || !pgpt_head) {
- printf("%s: Invalid Argument(s)\n", __FUNCTION__);
+ printf("%s: Invalid Argument(s)\n", __func__);
return NULL;
}
count = le32_to_int(pgpt_head->num_partition_entries) *
le32_to_int(pgpt_head->sizeof_partition_entry);
- debug("%s: count = %lu * %lu = %u\n", __FUNCTION__,
+ debug("%s: count = %lu * %lu = %u\n", __func__,
le32_to_int(pgpt_head->num_partition_entries),
le32_to_int(pgpt_head->sizeof_partition_entry), count);
if (count == 0 || pte == NULL) {
printf("%s: ERROR: Can't allocate 0x%X bytes for GPT Entries\n",
- __FUNCTION__, count);
+ __func__, count);
return NULL;
}
efi_guid_t unused_guid;
if (!pte) {
- printf("%s: Invalid Argument(s)\n", __FUNCTION__);
+ printf("%s: Invalid Argument(s)\n", __func__);
return 0;
}
if (memcmp(pte->partition_type_guid.b, unused_guid.b,
sizeof(unused_guid.b)) == 0) {
- debug("%s: Found an unused PTE GUID at 0x%08X\n", __FUNCTION__,
+ debug("%s: Found an unused PTE GUID at 0x%08X\n", __func__,
(unsigned int)pte);
return 0;
* 32 bytes each in size
*/
pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
- debug("cmd_slot = 0x%x\n", pp->cmd_slot);
+ debug("cmd_slot = %p\n", pp->cmd_slot);
mem += (AHCI_CMD_SLOT_SZ + 224);
/*
sata_dev_desc[devno].removable = 0;
sata_dev_desc[devno].lba = (u32) n_sectors;
- debug ("lba=0x%x\n", sata_dev_desc[devno].lba);
+ debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iobuf[83] & (1 << 10)) {
read_bytes = 0;
bufsize = bsize;
debug("%s: Launching the Lattice ISPVME Loader:"
- " addr 0x%x size 0x%x...\n",
+ " addr %p size 0x%lx...\n",
__func__, fpga_image, bufsize);
ret_val = ispVM();
if (ret_val)
/****************************************************/
{
static uint32_t resp[4], a, b, c;
- ulong status;
+ uint32_t status;
int i;
debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
int
/****************************************************/
-mmc_block_read(uchar * dst, ulong src, ulong len)
+mmc_block_read(uchar * dst, uint32_t src, int len)
/****************************************************/
{
ushort argh, argl;
return 0;
}
- debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong) dst, src, len);
+ debug("mmc_block_rd dst %p src %08x len %d\n", dst, src, len);
argh = len >> 16;
argl = len & 0xffff;
int
/****************************************************/
-pxa_mmc_write(uchar * src, ulong dst, int size)
+pxa_mmc_write(uchar * src, uint32_t dst, int size)
/****************************************************/
{
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
/* all block aligned accesses */
debug
- ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
+ ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if (part_start) {
part_len = mmc_block_size - part_start;
debug
- ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- (ulong) src, dst, end, part_start, part_end, aligned_start,
+ ("ps src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
0) {
src += part_len;
}
debug
- ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
+ ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, dst, end, part_start, part_end, aligned_start,
aligned_end);
for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
debug
- ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
+ ("al src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_write(dst, (uchar *) src, mmc_block_size)) < 0) {
return -1;
}
}
debug
- ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
+ ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if (part_end && dst < end) {
debug
- ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
+ ("pe src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
return -1;
#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) {
- debug("autoprotecting from %08x to %08x\n",
+ debug("autoprotecting from %08lx to %08lx\n",
apl[i].start, apl[i].start + apl[i].size - 1);
flash_protect(FLAG_PROTECT_SET,
apl[i].start,
debug("unlock address index %d\n", uaddr_idx);
info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
- debug("unlock addresses are 0x%x/0x%x\n", info->addr_unlock1, info->addr_unlock2);
+ debug("unlock addresses are 0x%lx/0x%lx\n",
+ info->addr_unlock1, info->addr_unlock2);
sect_cnt = 0;
total_size = 0;
ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
total_size += erase_region_size * erase_region_count;
- debug ("erase_region_count = %d erase_region_size = %d\n",
+ debug("erase_region_count = %ld erase_region_size = %ld\n",
erase_region_count, erase_region_size);
for (j = 0; j < erase_region_count; j++) {
if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
struct nand_chip *chip = mtd->priv;
struct s3c2410_nand *nand = s3c2410_get_base_nand();
- debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
+ debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong)nand;
static int s3c2410_dev_ready(struct mtd_info *mtd)
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
- debugX(1, "dev_ready\n");
+ debug("dev_ready\n");
return readl(&nand->nfstat) & 0x01;
}
void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
- debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
+ debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
}
ecc_code[0] = readb(&nand->nfecc);
ecc_code[1] = readb(&nand->nfecc + 1);
ecc_code[2] = readb(&nand->nfecc + 2);
- debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
+ debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
return 0;
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
- debugX(1, "board_nand_init()\n");
+ debug("board_nand_init()\n");
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
nand->options = 0;
#endif
- debugX(1, "end of nand_init\n");
+ debug("end of nand_init\n");
return 0;
}
hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
hw_p->tx = (mal_desc_t *)(bd_uncached);
hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
- debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
+ debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
}
for (i = 0; i < NUM_TX_BUFF; i++) {
if ((NUM_TX_BUFF - 1) == i)
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
hw_p->tx_run[i] = -1;
- debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
+ debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
}
for (i = 0; i < NUM_RX_BUFF; i++) {
hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
hw_p->rx_ready[i] = -1;
- debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
+ debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
}
reg = 0x00000000;
*/
writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
&fec->eth->mii_speed);
- debug("fec_init: mii_speed %#lx\n",
+ debug("fec_init: mii_speed %08x\n",
readl(&fec->eth->mii_speed));
}
static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
*/
ievent = readl(&fec->eth->ievent);
writel(ievent, &fec->eth->ievent);
- debug("fec_recv: ievent 0x%x\n", ievent);
+ debug("fec_recv: ievent 0x%lx\n", ievent);
if (ievent & FEC_IEVENT_BABR) {
fec_halt(dev);
fec_init(dev, fec->bd);
volatile struct ks8695_txdesc *dp;
static int next = 0;
- debug ("%s(%d): eth_send(packet=%x,len=%d)\n", __FILE__, __LINE__,
+ debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
packet, len);
dp = &ks8695_tx[next];
inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
for (r = 0; r < hose->region_count; r++)
- debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
+ debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
(u64)hose->regions[r].phys_start,
- hose->regions[r].bus_start,
- hose->regions[r].size,
+ (u64)hose->regions[r].bus_start,
+ (u64)hose->regions[r].size,
hose->regions[r].flags);
pci_register_hose(hose);
setbits_be32(&pci->pdb_stat, 0x08000000);
(void) in_be32(&pci->pdb_stat);
udelay(100);
- debug(" Asserting PCIe reset @%x = %x\n",
+ debug(" Asserting PCIe reset @%p = %x\n",
&pci->pdb_stat, in_be32(&pci->pdb_stat));
/* clear PCIe reset */
clrbits_be32(&pci->pdb_stat, 0x08000000);
{
cirrus_state_t *p = &s->c_state;
u_int mask = 0xffff;
-#if DEBUG
- char buf[200];
-
- memset (buf, 0, 200);
-#endif
+ char buf[200] = {0};
if (has_ring == -1)
has_ring = 1;
static inline void power_off(int slot)
{
- out_be32(PCMCIA_CTRL, 0);
+ volatile unsigned __iomem *addr;
+ addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
+
+ out_be32(addr, 0);
}
static inline void power_on_5_0(int slot)
{
+ volatile unsigned __iomem *addr;
+ addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
+
/* Enable 5V Vccout */
- out_be32(PCMCIA_CTRL, 2);
+ out_be32(addr, 2);
}
static inline void power_on_3_3(int slot)
{
+ volatile unsigned __iomem *addr;
+ addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
+
/* Enable 3.3V Vccout */
- out_be32(PCMCIA_CTRL, 1);
+ out_be32(addr, 1);
}
#else
pm = spibrg / (max_hz * 16 * 2);
if (pm > 16) {
pm = 16;
- debug("Requested speed is too low: %d Hz, "
- "%d Hz is used.\n", max_hz, spibrg / (32 * 16));
+ debug("Requested speed is too low: %d Hz, %ld Hz "
+ "is used.\n", max_hz, spibrg / (32 * 16));
}
} else
pm = spibrg / (max_hz * 2);
break;
}
- debug("spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n",
+ debug("spi_xfer: slave %u:%u dout %08X(%p) din %08X(%p) len %u\n",
slave->bus, slave->cs, *(uint *) dout,
dout, *(uint *) din, din, len);
unsigned int tmpdout, tmpdin;
int tm, isread = 0;
- debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+ debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
slave->bus, slave->cs, dout, din, bitlen);
if (flags & SPI_XFER_BEGIN)
isread = 1;
tmpdin = readl(&spireg->din);
debug
- ("spi_xfer: din %08x..%08x read\n",
+ ("spi_xfer: din %p..%08x read\n",
din, tmpdin);
if (din) {
/* set hardware address */
debug("** %s()\n", __func__);
- addr_lo = cpu_to_le32(*((u32 *)eth->enetaddr));
+ addr_lo = cpu_to_le32(*eth->enetaddr);
addr_hi = cpu_to_le16(*((u16 *)(eth->enetaddr + 4)));
ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
if (ret < 0) {
#else
#error CONFIG_SYS_VCXK_DEFAULT_LINEALIGN is invalid
#endif
- debug("linesize ((%d + 15) / 8 & ~0x1) = %d\n",
+ debug("linesize ((%ld + 15) / 8 & ~0x1) = %ld\n",
display_width, display_bwidth);
#ifdef CONFIG_SYS_VCXK_AUTODETECT
colors = le32_to_cpu(bmp->header.colors_used);
compression = le32_to_cpu(bmp->header.compression);
- debug("Display-bmp: %d x %d with %d colors\n",
+ debug("Display-bmp: %ld x %ld with %d colors\n",
width, height, colors);
if (compression != BMP_BI_RGB
static block_dev_desc_t *cur_dev = NULL;
static unsigned long part_offset = 0;
-static unsigned long part_size;
static int cur_part = 1;
if (!get_partition_info(dev_desc, part_no, &info)) {
part_offset = info.start;
cur_part = part_no;
- part_size = info.size;
} else if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) == 0) ||
(strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], "FAT32", 5) == 0)) {
/* ok, we assume we are on a PBR only */
}
if ((dentptr->attr & ATTR_VOLUME)) {
#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) &&
- (dentptr-> name[0] & LAST_LONG_ENTRY_MASK)) {
+ if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
+ (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
prevcksum = ((dir_slot *)dentptr)->alias_checksum;
get_vfatname(mydata, curclust,
get_dentfromdir_block,
}
if ((dentptr->attr & ATTR_VOLUME)) {
#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) &&
+ if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
prevcksum =
((dir_slot *)dentptr)->alias_checksum;
int force, int isShrink, int shadows);
static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj);
static int yaffs_CheckStructures(void);
-static int yaffs_DeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, __u32 level,
- int chunkOffset, int *limit);
static int yaffs_DoGenericObjectDeletion(yaffs_Object * in);
static yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blockNo);
obj->objectId));
}
-
-
-static int yaffs_VerifyTnodeWorker(yaffs_Object * obj, yaffs_Tnode * tn,
- __u32 level, int chunkOffset)
-{
- int i;
- yaffs_Device *dev = obj->myDev;
- int ok = 1;
-
- if (tn) {
- if (level > 0) {
-
- for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++){
- if (tn->internal[i]) {
- ok = yaffs_VerifyTnodeWorker(obj,
- tn->internal[i],
- level - 1,
- (chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
- }
- }
- } else if (level == 0) {
- int i;
- yaffs_ExtendedTags tags;
- __u32 objectId = obj->objectId;
-
- chunkOffset <<= YAFFS_TNODES_LEVEL0_BITS;
-
- for(i = 0; i < YAFFS_NTNODES_LEVEL0; i++){
- __u32 theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
-
- if(theChunk > 0){
- /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),tags.objectId,tags.chunkId,theChunk)); */
- yaffs_ReadChunkWithTagsFromNAND(dev,theChunk,NULL, &tags);
- if(tags.objectId != objectId || tags.chunkId != chunkOffset){
- T(~0,(TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
- objectId, chunkOffset, theChunk,
- tags.objectId, tags.chunkId));
- }
- }
- chunkOffset++;
- }
- }
- }
-
- return ok;
-
-}
-
-
static void yaffs_VerifyFile(yaffs_Object *obj)
{
int requiredTallness;
return -1;
}
-
-/* DeleteWorker scans backwards through the tnode tree and deletes all the
- * chunks and tnodes in the file
- * Returns 1 if the tree was deleted.
- * Returns 0 if it stopped early due to hitting the limit and the delete is incomplete.
- */
-
-static int yaffs_DeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, __u32 level,
- int chunkOffset, int *limit)
-{
- int i;
- int chunkInInode;
- int theChunk;
- yaffs_ExtendedTags tags;
- int foundChunk;
- yaffs_Device *dev = in->myDev;
-
- int allDone = 1;
-
- if (tn) {
- if (level > 0) {
-
- for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
- i--) {
- if (tn->internal[i]) {
- if (limit && (*limit) < 0) {
- allDone = 0;
- } else {
- allDone =
- yaffs_DeleteWorker(in,
- tn->
- internal
- [i],
- level -
- 1,
- (chunkOffset
- <<
- YAFFS_TNODES_INTERNAL_BITS)
- + i,
- limit);
- }
- if (allDone) {
- yaffs_FreeTnode(dev,
- tn->
- internal[i]);
- tn->internal[i] = NULL;
- }
- }
-
- }
- return (allDone) ? 1 : 0;
- } else if (level == 0) {
- int hitLimit = 0;
-
- for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0 && !hitLimit;
- i--) {
- theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
- if (theChunk) {
-
- chunkInInode =
- (chunkOffset <<
- YAFFS_TNODES_LEVEL0_BITS) + i;
-
- foundChunk =
- yaffs_FindChunkInGroup(dev,
- theChunk,
- &tags,
- in->objectId,
- chunkInInode);
-
- if (foundChunk > 0) {
- yaffs_DeleteChunk(dev,
- foundChunk, 1,
- __LINE__);
- in->nDataChunks--;
- if (limit) {
- *limit = *limit - 1;
- if (*limit <= 0) {
- hitLimit = 1;
- }
- }
-
- }
-
- yaffs_PutLevel0Tnode(dev,tn,i,0);
- }
-
- }
- return (i < 0) ? 1 : 0;
-
- }
-
- }
-
- return 1;
-
-}
-
static void yaffs_SoftDeleteChunk(yaffs_Device * dev, int chunk)
{
int nBytes)
{
- __u32 chunk;
- __u32 start;
+ __u32 chunk = 0;
+ __u32 start = 0;
int nToCopy;
int n = nBytes;
int nDone = 0;
int nBytes, int writeThrough)
{
- __u32 chunk;
- __u32 start;
+ __u32 chunk = 0;
+ __u32 start = 0;
int nToCopy;
int n = nBytes;
int nDone = 0;
{
int oldFileSize = in->variant.fileVariant.fileSize;
- __u32 newSizeOfPartialChunk;
- __u32 newFullChunks;
+ __u32 newSizeOfPartialChunk = 0;
+ __u32 newFullChunks = 0;
yaffs_Device *dev = in->myDev;
#include <flash.h>
#include <image.h>
-#ifdef DEBUG
-#define debug(fmt,args...) printf (fmt ,##args)
-#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args);
-#else
-#define debug(fmt,args...)
-#define debugX(level,fmt,args...)
-#endif /* DEBUG */
-
#ifdef DEBUG
-# define _DEBUG 1
+#define _DEBUG 1
#else
-# define _DEBUG 0
+#define _DEBUG 0
#endif
/*
+ * Output a debug text when condition "cond" is met. The "cond" should be
+ * computed by a preprocessor in the best case, allowing for the best
+ * optimization.
+ */
+#define debug_cond(cond, fmt, args...) \
+ do { \
+ if (cond) \
+ printf(fmt, ##args); \
+ } while (0)
+
+#define debug(fmt, args...) \
+ debug_cond(_DEBUG, fmt, ##args)
+
+/*
* An assertion is run-time check done in debug mode only. If DEBUG is not
* defined then it is skipped. If DEBUG is defined and the assertion fails,
* then it calls panic*( which may or may not reset/halt U-Boot (see
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
/*
* BOOTP options
*/
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
/*
* BOOTP options
*/
#define CONFIG_CMD_BSP
#define CONFIG_CMD_NAND
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
*/
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_CERF250 1 /* on Cerf PXA Board */
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BAUDRATE 38400
#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */
-#undef BOARD_LATE_INIT
+#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
/*
* Hardware drivers
/* EET platform additions */
#ifdef CONFIG_IMX31_PHYCORE_EET
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
/*
* Compressions
#define CONFIG_SHARP_LM8V31
#endif
#define CONFIG_MMC
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
# define CONFIG_XILINX_LL_TEMAC 1
# define CONFIG_SYS_ENET
#endif
+#if defined(XILINX_AXIEMAC_BASEADDR)
+# define CONFIG_XILINX_AXIEMAC 1
+# define CONFIG_SYS_ENET
+#endif
#undef ET_DEBUG
#undef CONFIG_ECC /* disable ECC support */
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
/* Board-specific Initialization Functions to be called */
#define CONFIG_SYS_BOARD_ASM_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_SCIF1 1
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC0,38400"
/* #define _CONFIG_UART2 */ /* internal uart 2 */
/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define USE_920T_MMU 1
#if 0
*/
#undef CONFIG_CMD_IMLS
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_64BIT_VSPRINTF
#define CONFIG_BOARD_EARLY_INIT_F
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
/*
* Hardware drivers
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
-#define BOARD_LATE_INIT /* call board_late_init during start up */
+#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */
/* timing informazion */
#define CONFIG_SYS_HZ 1000 /* Mandatory... */
#define L2_ENABLE (L2_INIT | L2CR_L2E)
+#ifndef __ASSEMBLY__
+#include <../board/Marvell/include/core.h>
+#endif
+
#endif /* __CONFIG_H */
#define CONFIG_PLEB2 1 /* on an PLEB2 Board */
#undef CONFIG_LCD
#undef CONFIG_MMC
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
/*
* Monitor configuration
*
#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 5
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF1 1
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
#define SH7757LCR_ETHERNET_MAC_SIZE 17
#define SH7757LCR_ETHERNET_NUM_CH 2
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
/* Gigabit Ether */
#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
#define CONFIG_MMC 1
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_FEC_MXC_PHYADDR 0x1f
#define CONFIG_MII
#define CONFIG_CMD_NET
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTDELAY 5
#define CONFIG_SYS_HZ 1000 /* must be 1000 */
#define CONFIG_BOARD_EARLY_INIT_F
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
/*
* Size of malloc() pool
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
#define CONFIG_SYS_TEXT_BASE 0x0
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
#define CONFIG_SYS_TEXT_BASE 0x0
-#undef BOARD_LATE_INIT
+#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
/*
* Compressions
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#if defined(CONFIG_I2C_MULTI_BUS)
-#if !defined(CONFIG_SYS_MAX_I2C_BUS)
-#define CONFIG_SYS_MAX_I2C_BUS 2
-#endif
-#define I2C_GET_BUS() i2c_get_bus_num()
-#define I2C_SET_BUS(a) i2c_set_bus_num(a)
+#ifdef CONFIG_I2C_MULTI_BUS
+#define MAX_I2C_BUS 2
+#define I2C_MULTI_BUS 1
#else
-#define CONFIG_SYS_MAX_I2C_BUS 1
-#define I2C_GET_BUS() 0
-#define I2C_SET_BUS(a)
+#define MAX_I2C_BUS 1
+#define I2C_MULTI_BUS 0
+#endif
+
+#if !defined(CONFIG_SYS_MAX_I2C_BUS)
+#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS
#endif
/* define the I2C bus number for RTC and DTT if not already done */
unsigned int i2c_get_bus_speed(void);
+/* NOTE: These two functions MUST be always_inline to avoid code growth! */
+static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
+static inline unsigned int I2C_GET_BUS(void)
+{
+ return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
+}
+
+static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
+static inline void I2C_SET_BUS(unsigned int bus)
+{
+ if (I2C_MULTI_BUS)
+ i2c_set_bus_num(bus);
+}
+
#endif /* _I2C_H_ */
#ifndef USE_HOSTCC
static inline int fit_image_check_target_arch(const void *fdt, int node)
{
- return !fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
+ return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
}
#endif /* USE_HOSTCC */
#elif defined(CONFIG_ATMEL_LCD)
typedef struct vidinfo {
- u_long vl_col; /* Number of columns (i.e. 640) */
- u_long vl_row; /* Number of rows (i.e. 480) */
+ ushort vl_col; /* Number of columns (i.e. 640) */
+ ushort vl_row; /* Number of rows (i.e. 480) */
u_long vl_clk; /* pixel clock in ps */
/* LCD configuration register */
extern void NetReceive(volatile uchar *, int);
/*
+ * Check if autoload is enabled. If so, use either NFS or TFTP to download
+ * the boot file.
+ */
+void net_auto_load(void);
+
+/*
* The following functions are a bit ugly, but necessary to deal with
* alignment restrictions on ARM.
*
ELzmaStatus state;
SizeT compressedSize = (SizeT)(length - LZMA_PROPS_SIZE);
- debug ("LZMA: Image address............... 0x%lx\n", inStream);
- debug ("LZMA: Properties address.......... 0x%lx\n", inStream + LZMA_PROPERTIES_OFFSET);
- debug ("LZMA: Uncompressed size address... 0x%lx\n", inStream + LZMA_SIZE_OFFSET);
- debug ("LZMA: Compressed data address..... 0x%lx\n", inStream + LZMA_DATA_OFFSET);
- debug ("LZMA: Destination address......... 0x%lx\n", outStream);
+ debug ("LZMA: Image address............... 0x%p\n", inStream);
+ debug ("LZMA: Properties address.......... 0x%p\n", inStream + LZMA_PROPERTIES_OFFSET);
+ debug ("LZMA: Uncompressed size address... 0x%p\n", inStream + LZMA_SIZE_OFFSET);
+ debug ("LZMA: Compressed data address..... 0x%p\n", inStream + LZMA_DATA_OFFSET);
+ debug ("LZMA: Destination address......... 0x%p\n", outStream);
memset(&state, 0, sizeof(state));
}
}
- debug ("LZMA: Uncompresed size............ 0x%lx\n", outSizeFull);
- debug ("LZMA: Compresed size.............. 0x%lx\n", compressedSize);
+ debug ("LZMA: Uncompresed size............ 0x%x\n", outSizeFull);
+ debug ("LZMA: Compresed size.............. 0x%x\n", compressedSize);
g_Alloc.Alloc = SzAlloc;
g_Alloc.Free = SzFree;
return (curlen);
}
-/*
- * Check if autoload is enabled. If so, use either NFS or TFTP to download
- * the boot file.
- */
-static void auto_load(void)
-{
- const char *s = getenv("autoload");
-
- if (s != NULL) {
- if (*s == 'n') {
- /*
- * Just use BOOTP to configure system;
- * Do not use TFTP to load the bootfile.
- */
- NetState = NETLOOP_SUCCESS;
- return;
- }
-#if defined(CONFIG_CMD_NFS)
- if (strcmp(s, "NFS") == 0) {
- /*
- * Use NFS to load the bootfile.
- */
- NfsStart();
- return;
- }
-#endif
- }
- TftpStart(TFTPGET);
-}
-
#if !defined(CONFIG_CMD_DHCP)
static void BootpVendorFieldProcess (u8 * ext)
debug("Got good BOOTP\n");
- auto_load();
+ net_auto_load();
}
#endif
dhcp_state = BOUND;
printf ("DHCP client bound to address %pI4\n", &NetOurIP);
- auto_load();
+ net_auto_load();
return;
}
break;
/* Current RX packet handler */
static rxhand_f *packetHandler;
+#ifdef CONFIG_CMD_TFTPPUT
static rxhand_icmp_f *packet_icmp_handler; /* Current ICMP rx handler */
+#endif
/* Current timeout handler */
static thand_f *timeHandler;
/* Time base value */
void ArpRequest(void)
{
- int i;
volatile uchar *pkt;
ARP_t *arp;
memcpy(&arp->ar_data[0], NetOurEther, 6);
/* source IP addr */
NetWriteIP((uchar *) &arp->ar_data[6], NetOurIP);
- for (i = 10; i < 16; ++i) {
- /* dest ET addr = 0 */
- arp->ar_data[i] = 0;
- }
-
+ /* dest ET addr = 0 */
+ memset(&arp->ar_data[10], '\0', 6);
if ((NetArpWaitPacketIP & NetOurSubnetMask) !=
(NetOurIP & NetOurSubnetMask)) {
if (NetOurGatewayIP == 0) {
}
}
+/*
+ * Check if autoload is enabled. If so, use either NFS or TFTP to download
+ * the boot file.
+ */
+void net_auto_load(void)
+{
+ const char *s = getenv("autoload");
+
+ if (s != NULL) {
+ if (*s == 'n') {
+ /*
+ * Just use BOOTP/RARP to configure system;
+ * Do not use TFTP to load the bootfile.
+ */
+ NetState = NETLOOP_SUCCESS;
+ return;
+ }
+#if defined(CONFIG_CMD_NFS)
+ if (strcmp(s, "NFS") == 0) {
+ /*
+ * Use NFS to load the bootfile.
+ */
+ NfsStart();
+ return;
+ }
+#endif
+ }
+ TftpStart(TFTPGET);
+}
+
static void NetInitLoop(enum proto_t protocol)
{
static int env_changed_id;
}
done:
+#ifdef CONFIG_CMD_TFTPPUT
/* Clear out the handlers */
NetSetHandler(NULL);
net_set_icmp_handler(NULL);
+#endif
return ret;
}
packetHandler = f;
}
+#ifdef CONFIG_CMD_TFTPPUT
void net_set_icmp_handler(rxhand_icmp_f *f)
{
packet_icmp_handler = f;
}
+#endif
void
NetSetTimeout(ulong iv, thand_f *f)
break;
#endif
default:
+#ifdef CONFIG_CMD_TFTPPUT
if (packet_icmp_handler)
packet_icmp_handler(icmph->type, icmph->code,
ntohs(ip->udp_dst), src_ip, ntohs(ip->udp_src),
icmph->un.data, ntohs(ip->udp_len));
+#endif
break;
}
}
RarpHandler(uchar *dummi0, unsigned dummi1, IPaddr_t sip, unsigned dummi2,
unsigned dummi3)
{
- char *s;
debug("Got good RARP\n");
- if ((s = getenv("autoload")) != NULL) {
- if (*s == 'n') {
- /*
- * Just use RARP to configure system;
- * Do not use TFTP/NFS to to load the bootfile.
- */
- NetState = NETLOOP_SUCCESS;
- return;
-#if defined(CONFIG_CMD_NFS)
- } else if ((s != NULL) && !strcmp(s, "NFS")) {
- NfsStart();
- return;
-#endif
- }
- }
- TftpStart ();
+ net_auto_load();
}
}
/* Clear our state ready for a new transfer */
-void new_transfer(void)
+static void new_transfer(void)
{
TftpLastBlock = 0;
TftpBlockWrap = 0;
case STATE_SEND_WRQ:
xp = pkt;
s = (ushort *)pkt;
+#ifdef CONFIG_CMD_TFTPPUT
*s++ = htons(TftpState == STATE_SEND_RRQ ? TFTP_RRQ :
TFTP_WRQ);
+#else
+ *s++ = htons(TFTP_RRQ);
+#endif
pkt = (uchar *)s;
strcpy((char *)pkt, tftp_filename);
pkt += strlen(tftp_filename) + 1;
TftpOurPort, len);
}
-
+#ifdef CONFIG_CMD_TFTPPUT
static void icmp_handler(unsigned type, unsigned code, unsigned dest,
IPaddr_t sip, unsigned src, uchar *pkt, unsigned len)
{
restart("TFTP server died");
}
}
+#endif
static void
TftpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
printf("Using %s device\n", eth_get_name());
printf("TFTP %s server %pI4; our IP address is %pI4",
- protocol == TFTPPUT ? "to" : "from", &TftpRemoteIP, &NetOurIP);
+#ifdef CONFIG_CMD_TFTPPUT
+ protocol == TFTPPUT ? "to" : "from",
+#else
+ "from",
+#endif
+ &TftpRemoteIP, &NetOurIP);
/* Check if we need to send across this subnet */
if (NetOurGatewayIP && NetOurSubnetMask) {
NetSetTimeout(TftpTimeoutMSecs, TftpTimeout);
NetSetHandler(TftpHandler);
+#ifdef CONFIG_CMD_TFTPPUT
net_set_icmp_handler(icmp_handler);
-
+#endif
TftpRemotePort = WELL_KNOWN_PORT;
TftpTimeoutCount = 0;
/* Use a pseudo-random port unless a specific port is set */
projects / platform / kernel / u-boot.git / commitdiff