drm/i915: Bump GLK CDCLK frequency when driving multiple pipes

commit 0cb89cd42fd22bbdec0b046c48f35775f5b88bdb upstream.

On GLK CDCLK frequency needs to be at least 2*96 MHz when accessing
the audio hardware. Currently we bump the CDCLK frequency up
temporarily (if not high enough already) whenever audio hardware
is being accessed, and drop it back down afterwards.

With a single active pipe this works just fine as we can switch
between all the valid CDCLK frequencies by changing the cd2x
divider, which doesn't require a full modeset. However with
multiple active pipes the cd2x divider trick no longer works,
and thus we end up blinking all displays off and back on.

To avoid this let's just bump the CDCLK frequency to >=2*96MHz
whenever multiple pipes are active. The downside is slightly
higher power consumption, but that seems like an acceptable
tradeoff. With a single active pipe we can stick to the current
more optiomal (from power comsumption POV) behaviour.

Cc: stable@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9599
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231031160800.18371-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit 451eaa1a614c911f5a51078dcb68022874e4cb12)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2fb030b..f99cf80 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2688,6 +2688,18 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
        for_each_pipe(dev_priv, pipe)
                min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
 
+       /*
+        * Avoid glk_force_audio_cdclk() causing excessive screen
+        * blinking when multiple pipes are active by making sure
+        * CDCLK frequency is always high enough for audio. With a
+        * single active pipe we can always change CDCLK frequency
+        * by changing the cd2x divider (see glk_cdclk_table[]) and
+        * thus a full modeset won't be needed then.
+        */
+       if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
+           !is_power_of_2(cdclk_state->active_pipes))
+               min_cdclk = max(2 * 96000, min_cdclk);
+
        if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
                drm_dbg_kms(&dev_priv->drm,
                            "required cdclk (%d kHz) exceeds max (%d kHz)\n",