ice: Create a generic name for the ice_rx_flg64_bits structure
authorChinh T Cao <chinh.t.cao@intel.com>
Wed, 13 Feb 2019 18:51:11 +0000 (10:51 -0800)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Mon, 25 Mar 2019 17:40:04 +0000 (10:40 -0700)
This structure is used to define the packet flags. These flags are
applicable for both TX and RX packet. Thus, this patch changes its
name from ice_rx_flag64_bits to ice_flg64_bits, and its member definition.

Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com>
Reviewed-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/ice/ice_common.c
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

index ca9a8c5..5e7a314 100644 (file)
@@ -358,22 +358,22 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
         */
        case ICE_RXDID_FLEX_NIC:
        case ICE_RXDID_FLEX_NIC_2:
-               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,
-                                  ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,
-                                  ICE_RXFLG_FIN, idx++);
+               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
+                                  ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
+                                  ICE_FLG_FIN, idx++);
                /* flex flag 1 is not used for flexi-flag programming, skipping
                 * these four FLG64 bits.
                 */
-               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,
-                                  ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);
-               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,
-                                  ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,
-                                  ICE_RXFLG_EVLAN_x9100, idx++);
-               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,
-                                  ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,
-                                  ICE_RXFLG_TNL0, idx++);
-               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,
-                                  ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);
+               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
+                                  ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
+               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
+                                  ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
+                                  ICE_FLG_EVLAN_x9100, idx++);
+               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
+                                  ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
+                                  ICE_FLG_TNL0, idx++);
+               ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
+                                  ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
                break;
 
        default:
index ef4c79b..2e87b69 100644 (file)
@@ -208,23 +208,23 @@ enum ice_flex_rx_mdid {
        ICE_RX_MDID_HASH_HIGH,
 };
 
-/* Rx Flag64 packet flag bits */
-enum ice_rx_flg64_bits {
-       ICE_RXFLG_PKT_DSI       = 0,
-       ICE_RXFLG_EVLAN_x8100   = 15,
-       ICE_RXFLG_EVLAN_x9100,
-       ICE_RXFLG_VLAN_x8100,
-       ICE_RXFLG_TNL_MAC       = 22,
-       ICE_RXFLG_TNL_VLAN,
-       ICE_RXFLG_PKT_FRG,
-       ICE_RXFLG_FIN           = 32,
-       ICE_RXFLG_SYN,
-       ICE_RXFLG_RST,
-       ICE_RXFLG_TNL0          = 38,
-       ICE_RXFLG_TNL1,
-       ICE_RXFLG_TNL2,
-       ICE_RXFLG_UDP_GRE,
-       ICE_RXFLG_RSVD          = 63
+/* RX/TX Flag64 packet flag bits */
+enum ice_flg64_bits {
+       ICE_FLG_PKT_DSI         = 0,
+       ICE_FLG_EVLAN_x8100     = 15,
+       ICE_FLG_EVLAN_x9100,
+       ICE_FLG_VLAN_x8100,
+       ICE_FLG_TNL_MAC         = 22,
+       ICE_FLG_TNL_VLAN,
+       ICE_FLG_PKT_FRG,
+       ICE_FLG_FIN             = 32,
+       ICE_FLG_SYN,
+       ICE_FLG_RST,
+       ICE_FLG_TNL0            = 38,
+       ICE_FLG_TNL1,
+       ICE_FLG_TNL2,
+       ICE_FLG_UDP_GRE,
+       ICE_FLG_RSVD            = 63
 };
 
 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */