arm64: dts: imx8dxl_evk: add flexspi0 support

Enable flexspi0 at imx8dxl_evk boards dts.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 11b1ff9..f8d416f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -181,6 +181,23 @@
        };
 };
 
+&flexspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       nxp,fspi-dll-slvdly = <4>;
+       status = "okay";
+
+       mt35xu512aba0: flash@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <133000000>;
+               spi-tx-bus-width = <8>;
+               spi-rx-bus-width = <8>;
+       };
+};
+
 &i2c2 {
        #address-cells = <1>;
        #size-cells = <0>;
@@ -386,6 +403,25 @@
                >;
        };
 
+       pinctrl_flexspi0: flexspi0grp {
+               fsl,pins = <
+                       IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
+                       IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
+                       IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
+                       IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
+                       IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
+                       IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
+                       IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
+                       IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
+                       IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
+                       IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
+                       IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
+                       IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
+                       IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
+                       IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
+               >;
+       };
+
        pinctrl_fec1: fec1grp {
                fsl,pins = <
                        IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD           0x000014a0