rdar://12329730 (2nd part, revised)

The type of shirt-right (logical or arithemetic) should remain unchanged
when transforming  "X << C1 >> C2" into "X << (C1-C2)"

llvm-svn: 169209

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index c65076e..c832ca5 100644 (file)
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -876,7 +876,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
       New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
     } else {
       Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
-      New = BinaryOperator::CreateLShr(VarX, Amt);
+      New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
+                     BinaryOperator::CreateAShr(VarX, Amt);
     }
 
     return InsertNewInstWith(New, *Shl);

diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index b152816..fad0bd7 100644 (file)
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -723,7 +723,7 @@ define i32 @test60(i32 %x) {
   %or = or i32 %shl, 1
   ret i32 %or
 ; CHECK: @test60
-; CHECK: lshr i32 %x, 3
+; CHECK: ashr i32 %x, 3
 }