arm64: dts: sc7180: Add cpufreq HW node for cpu scaling

cpufreq hw node required to scale CPU frequency on sc7180.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/0101016ed02b6356-5165eaaa-6c54-47ff-a008-821c91831e56-000000@us-west-2.amazonses.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e156710..1dd016c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -54,6 +54,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -69,6 +70,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        next-level-cache = <&L2_100>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -81,6 +83,7 @@
                        reg = <0x0 0x200>;
                        enable-method = "psci";
                        next-level-cache = <&L2_200>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -93,6 +96,7 @@
                        reg = <0x0 0x300>;
                        enable-method = "psci";
                        next-level-cache = <&L2_300>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -105,6 +109,7 @@
                        reg = <0x0 0x400>;
                        enable-method = "psci";
                        next-level-cache = <&L2_400>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_400: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -117,6 +122,7 @@
                        reg = <0x0 0x500>;
                        enable-method = "psci";
                        next-level-cache = <&L2_500>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_500: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -129,6 +135,7 @@
                        reg = <0x0 0x600>;
                        enable-method = "psci";
                        next-level-cache = <&L2_600>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -141,6 +148,7 @@
                        reg = <0x0 0x700>;
                        enable-method = "psci";
                        next-level-cache = <&L2_700>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_700: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;
@@ -1132,6 +1140,17 @@
                                #clock-cells = <1>;
                        };
                };
+
+               cpufreq_hw: cpufreq@18323000 {
+                       compatible = "qcom,cpufreq-hw";
+                       reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
+                       reg-names = "freq-domain0", "freq-domain1";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+               };
        };
 
        timer {