gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_fold_builtin): Fold float conversions.
* config/aarch64/aarch64-simd-builtins.def
(floatv2si, floatv4si, floatv2di): New.
(floatunsv2si, floatunsv4si, floatunsv2di): Likewise.
* config/aarch64/aarch64-simd.md
(<optab><fcvt_target><VDQF:mode>2): New, expands to float and floatuns.
* config/aarch64/iterators.md (FLOATUORS): New.
(optab): Add float, floatuns.
(su_optab): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198399
138bc75d-0d04-0410-961f-
82ee72b054a4
2013-04-29 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
+ (aarch64_fold_builtin): Fold float conversions.
+ * config/aarch64/aarch64-simd-builtins.def
+ (floatv2si, floatv4si, floatv2di): New.
+ (floatunsv2si, floatunsv4si, floatunsv2di): Likewise.
+ * config/aarch64/aarch64-simd.md
+ (<optab><fcvt_target><VDQF:mode>2): New, expands to float and floatuns.
+ * config/aarch64/iterators.md (FLOATUORS): New.
+ (optab): Add float, floatuns.
+ (su_optab): Likewise.
+
+2013-04-29 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Use new names for
fcvt builtins.
* config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as...
BUILTIN_VDQF (UNOP, abs, 2)
return fold_build1 (ABS_EXPR, type, args[0]);
break;
+ VAR1 (UNOP, floatv2si, 2, v2sf)
+ VAR1 (UNOP, floatv4si, 2, v4sf)
+ VAR1 (UNOP, floatv2di, 2, v2df)
+ return fold_build1 (FLOAT_EXPR, type, args[0]);
+ break;
default:
break;
}
VAR1 (UNOP, lfrintnusf, 2, si)
VAR1 (UNOP, lfrintnudf, 2, di)
+ /* Implemented by <optab><fcvt_target><VDQF:mode>2. */
+ VAR1 (UNOP, floatv2si, 2, v2sf)
+ VAR1 (UNOP, floatv4si, 2, v4sf)
+ VAR1 (UNOP, floatv2di, 2, v2df)
+
+ VAR1 (UNOP, floatunsv2si, 2, v2sf)
+ VAR1 (UNOP, floatunsv4si, 2, v4sf)
+ VAR1 (UNOP, floatunsv2di, 2, v2df)
+
/* Implemented by
aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */
BUILTIN_VALL (BINOP, zip1, 0)
(set_attr "simd_mode" "<MODE>")]
)
+(define_insn "<optab><fcvt_target><VDQF:mode>2"
+ [(set (match_operand:VDQF 0 "register_operand" "=w")
+ (FLOATUORS:VDQF
+ (match_operand:<FCVT_TARGET> 1 "register_operand" "w")))]
+ "TARGET_SIMD"
+ "<su_optab>cvtf\\t%0.<Vtype>, %1.<Vtype>"
+ [(set_attr "simd_type" "simd_icvtf")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
(define_insn "aarch64_vmls<mode>"
[(set (match_operand:VDQF 0 "register_operand" "=w")
(minus:VDQF (match_operand:VDQF 1 "register_operand" "0")
;; Iterator for integer conversions
(define_code_iterator FIXUORS [fix unsigned_fix])
+;; Iterator for float conversions
+(define_code_iterator FLOATUORS [float unsigned_float])
+
;; Code iterator for variants of vector max and min.
(define_code_iterator MAXMIN [smax smin umax umin])
(zero_extend "zero_extend")
(sign_extract "extv")
(zero_extract "extzv")
+ (float "float")
+ (unsigned_float "floatuns")
(and "and")
(ior "ior")
(xor "xor")
(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
(div "") (udiv "u")
(fix "") (unsigned_fix "u")
+ (float "s") (unsigned_float "u")
(ss_plus "s") (us_plus "u")
(ss_minus "s") (us_minus "u")])