iommu/mediatek: Introduce new flag TF_PORT_TO_ADDR_MT8173
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tue, 13 Sep 2022 15:11:47 +0000 (17:11 +0200)
committerJoerg Roedel <jroedel@suse.de>
Mon, 26 Sep 2022 11:33:03 +0000 (13:33 +0200)
In preparation for adding support for MT6795, add a new flag named
TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat
type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat
checks there in the future.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20220913151148.412312-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/mtk_iommu.c

index 7e363b1..b511359 100644 (file)
 #define PM_CLK_AO                      BIT(15)
 #define IFA_IOMMU_PCIE_SUPPORT         BIT(16)
 #define PGTABLE_PA_35_EN               BIT(17)
+#define TF_PORT_TO_ADDR_MT8173         BIT(18)
 
 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)       \
                                ((((pdata)->flags) & (mask)) == (_x))
@@ -955,7 +956,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int ban
         * Global control settings are in bank0. May re-init these global registers
         * since no sure if there is bank0 consumers.
         */
-       if (data->plat_data->m4u_plat == M4U_MT8173) {
+       if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
                regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
                         F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
        } else {
@@ -1427,7 +1428,8 @@ static const struct mtk_iommu_plat_data mt8167_data = {
 static const struct mtk_iommu_plat_data mt8173_data = {
        .m4u_plat     = M4U_MT8173,
        .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
-                       HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
+                       HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
+                       TF_PORT_TO_ADDR_MT8173,
        .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
        .banks_num    = 1,
        .banks_enable = {true},