arm64: dts: qcom: use UFS symbol clocks provided by PHY

Remove manually created symbol clocks and replace them with clocks
provided by PHY.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221123104443.3415267-5-dmitry.baryshkov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index f4da50b..b8cf5c4 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -720,7 +720,9 @@
                                 <&pciephy_1>,
                                 <&pciephy_2>,
                                 <&ssusb_phy_0>,
-                                <0>, <0>, <0>;
+                                <&ufsphy_lane 0>,
+                                <&ufsphy_lane 1>,
+                                <&ufsphy_lane 2>;
                        clock-names = "cxo",
                                      "cxo2",
                                      "sleep_clk",
@@ -2052,6 +2054,7 @@
                                reg = <0x627400 0x12c>,
                                      <0x627600 0x200>,
                                      <0x627c00 0x1b4>;
+                               #clock-cells = <1>;
                                #phy-cells = <0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 10ea2ed..f853673 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -37,24 +37,6 @@
                        clock-frequency = <32000>;
                        #clock-cells = <0>;
                };
-
-               ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
-                       compatible = "fixed-clock";
-                       clock-frequency = <1000>;
-                       #clock-cells = <0>;
-               };
-
-               ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
-                       compatible = "fixed-clock";
-                       clock-frequency = <1000>;
-                       #clock-cells = <0>;
-               };
-
-               ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
-                       compatible = "fixed-clock";
-                       clock-frequency = <1000>;
-                       #clock-cells = <0>;
-               };
        };
 
        cpus {
@@ -666,9 +648,9 @@
                                 <0>,
                                 <0>,
                                 <0>,
-                                <&ufs_phy_rx_symbol_0_clk>,
-                                <&ufs_phy_rx_symbol_1_clk>,
-                                <&ufs_phy_tx_symbol_0_clk>,
+                                <&ufs_mem_phy_lanes 0>,
+                                <&ufs_mem_phy_lanes 1>,
+                                <&ufs_mem_phy_lanes 2>,
                                 <0>,
                                 <0>;
                };
@@ -2371,6 +2353,7 @@
                                      <0 0x01d87c00 0 0x200>,
                                      <0 0x01d87800 0 0x188>,
                                      <0 0x01d87a00 0 0x200>;
+                               #clock-cells = <1>;
                                #phy-cells = <0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 5ba6578..a196ca8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -743,11 +743,21 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&sleep_clk>,
                                 <&pcie0_lane>,
-                                <&pcie1_lane>;
+                                <&pcie1_lane>,
+                                <0>,
+                                <&ufs_mem_phy_lanes 0>,
+                                <&ufs_mem_phy_lanes 1>,
+                                <&ufs_mem_phy_lanes 2>,
+                                <0>;
                        clock-names = "bi_tcxo",
                                      "sleep_clk",
                                      "pcie_0_pipe_clk",
-                                     "pcie_1_pipe_clk";
+                                     "pcie_1_pipe_clk",
+                                     "pcie_1_phy_aux_clk",
+                                     "ufs_phy_rx_symbol_0_clk",
+                                     "ufs_phy_rx_symbol_1_clk",
+                                     "ufs_phy_tx_symbol_0_clk",
+                                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";
                };
 
                gpi_dma2: dma-controller@800000 {
@@ -4049,6 +4059,7 @@
                                      <0 0x01d87c00 0 0x200>,
                                      <0 0x01d87800 0 0x188>,
                                      <0 0x01d87a00 0 0x200>;
+                               #clock-cells = <1>;
                                #phy-cells = <0>;
                        };
                };