armv8: fsl-layerscape: Consolidate the LSCH2 common defines

Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 44fe0c0..7116f9d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -149,43 +149,43 @@
 #define CONFIG_ARM_ERRATA_833471
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-#elif defined(CONFIG_LS1043A)
-#define CONFIG_MAX_CPUS                                4
+#elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_CACHELINE_SIZE              64
-#define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_NUM_FMAN                    1
-#define CONFIG_SYS_NUM_FM1_DTSEC               7
-#define CONFIG_SYS_NUM_FM1_10GEC               1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
 #define CONFIG_NUM_DDR_CONTROLLERS             1
-#define CONFIG_SYS_CCSRBAR_DEFAULT             0x01000000
 #define CONFIG_SYS_FSL_SEC_COMPAT              5
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
-#define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00200000 /* 2M */
+#define CONFIG_SYS_CCSRBAR_DEFAULT             0x01000000
 
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_PEX_LUT_BE
+#define CONFIG_SYS_FSL_SEC_BE
+
+#define CONFIG_SYS_FSL_SRDS_1
+/* SoC related */
+#ifdef CONFIG_LS1043A
+#define CONFIG_MAX_CPUS                                4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN                    1
+#define CONFIG_SYS_NUM_FM1_DTSEC               7
+#define CONFIG_SYS_NUM_FM1_10GEC               1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE          0x6000UL
 #define MAX_QE_RISC            1
 #define QE_NUM_OF_SNUM         28
 
-#define SRDS_MAX_LANES         4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT             "fsl,qoriq-pcie-v2.4"
-
+#define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION
@@ -205,32 +205,13 @@
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #elif defined(CONFIG_LS1012A)
 #define CONFIG_MAX_CPUS                         1
-#define CONFIG_SYS_CACHELINE_SIZE              64
-#define CONFIG_NUM_DDR_CONTROLLERS             1
-#define CONFIG_SYS_CCSRBAR_DEFAULT             0x01000000
-#define CONFIG_SYS_FSL_SEC_COMPAT              5
 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
-#define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
-
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
-
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
-#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
-#define CONFIG_SYS_FSL_PEX_LUT_BE
-
-#define SRDS_MAX_LANES         4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT             "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif
+#endif
 
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */