}
if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (SFmode, operands[1]);
+ {
+ operands[1] = force_reg (SFmode, operands[1]);
+ if (! TARGET_POWERPC)
+ if (reload_in_progress || reload_completed)
+ emit_insn (gen_truncdfsf2 (operands[1],
+ gen_rtx (SUBREG, DFmode, operands[1], 0)));
+ else
+ {
+ rtx newreg = gen_reg_rtx (SFmode);
+ emit_insn (gen_truncdfsf2 (newreg,
+ gen_rtx (SUBREG, DFmode, operands[1], 0)));
+ operands[1] = newreg;
+ }
+ }
if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
{
"@
fmr %0,%1
lfs%U1%X1 %0,%1
- frsp %1,%1\;stfs%U0%X0 %1,%0"
+ stfs%U0%X0 %1,%0"
[(set_attr "type" "fp,fpload,*")
(set_attr "length" "*,*,8")])
\f
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- frsp %3,%3\;stfsux %3,%0,%2
- frsp %3,%3\;stfsu %3,%2(%0)")
+ stfsux %3,%0,%2
+ stfsu %3,%2(%0)")
(define_insn ""
[(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")