[objdump][ARM] Fix evaluating the target address of a Thumb BLX(i)
authorIgor Kudrin <ikudrin@accesssoftek.com>
Fri, 18 Jun 2021 03:40:55 +0000 (10:40 +0700)
committerIgor Kudrin <ikudrin@accesssoftek.com>
Fri, 18 Jun 2021 03:40:55 +0000 (10:40 +0700)
The instruction can be 16-bit aligned while targeting 32-bit aligned
code. To calculate the target address correctly, the address of the
instruction has to be adjusted.

Differential Revision: https://reviews.llvm.org/D104446

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s [new file with mode: 0644]

index a827125..3fad668 100644 (file)
@@ -429,6 +429,14 @@ public:
     // is 4 bytes.
     uint64_t Offset = ((Desc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
 
+    // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
+    // which is 32-bit aligned. The target address for the case is calculated as
+    //   targetAddress = Align(PC,4) + imm32;
+    // where
+    //   Align(x, y) = y * (x DIV y);
+    if (Inst.getOpcode() == ARM::tBLXi)
+      Addr &= ~0x3;
+
     Target = Addr + Imm + Offset;
     return true;
   }
diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s b/llvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s
new file mode 100644 (file)
index 0000000..096c1a3
--- /dev/null
@@ -0,0 +1,26 @@
+## Check that the disassembler reports the target address of a Thumb BLX(i)
+## instruction correctly even if the instruction is not 32-bit aligned.
+
+# RUN: llvm-mc %s --triple=armv8a -filetype=obj | \
+# RUN:   llvm-objdump -dr - --triple armv8a --no-show-raw-insn | \
+# RUN:   FileCheck %s
+
+# CHECK:      <test>:
+# CHECK-NEXT:   4:  nop
+# CHECK-NEXT:   6:  blx  #-8 <foo>
+# CHECK-NEXT:   a:  blx  #4 <bar>
+
+  .arm
+foo:
+  nop
+
+  .thumb
+test:
+  nop
+  blx #-8
+  blx #4
+
+  .arm
+  .p2align 2
+bar:
+  nop