imx8ulp: clock: Fix lcd clock algo

The div loop uses reassign and reuse parent_rate, which causes
the parent rate reference to be wrong after the first loop, the
resulting clock becomes incorrect for div != 1.

Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock")
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 3e71a4f..3e88f46 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -440,10 +440,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
        debug("PLL4 rate %ukhz\n", pll4_rate);
 
        for (pfd = 12; pfd <= 35; pfd++) {
-               parent_rate = pll4_rate;
-               parent_rate = parent_rate * 18 / pfd;
-
                for (div = 1; div <= 64; div++) {
+                       parent_rate = pll4_rate;
+                       parent_rate = parent_rate * 18 / pfd;
                        parent_rate = parent_rate / div;
 
                        for (pcd = 0; pcd < 8; pcd++) {