radv: add support for smooth lines

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index 67585ad..ceb8623 100644 (file)
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -78,6 +78,7 @@ libradv_files = files(
   'nir/radv_nir_lower_fs_intrinsics.c',
   'nir/radv_nir_lower_intrinsics_early.c',
   'nir/radv_nir_lower_io.c',
+  'nir/radv_nir_lower_poly_line_smooth.c',
   'nir/radv_nir_lower_primitive_shading_rate.c',
   'nir/radv_nir_lower_ray_queries.c',
   'nir/radv_nir_lower_view_index.c',

diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h
index 99bb361..8b38572 100644 (file)
--- a/src/amd/vulkan/nir/radv_nir.h
+++ b/src/amd/vulkan/nir/radv_nir.h
@@ -76,6 +76,8 @@ void radv_nir_lower_io(struct radv_device *device, nir_shader *nir);
 
 bool radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *stage);
 
+void radv_nir_lower_poly_line_smooth(nir_shader *nir, const struct radv_pipeline_key *key);
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c b/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c
new file mode 100644 (file)
index 0000000..ab58fe4
--- /dev/null
+++ b/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright © 2023 Valve Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+#include "radv_nir.h"
+#include "radv_private.h"
+
+static bool
+radv_should_lower_poly_line_smooth(nir_shader *nir, const struct radv_pipeline_key *key)
+{
+   nir_function_impl *impl = nir_shader_get_entrypoint(nir);
+
+   if (!key->ps.line_smooth_enabled && !key->dynamic_line_rast_mode)
+      return false;
+
+   nir_builder b;
+   nir_builder_init(&b, impl);
+
+   nir_foreach_block (block, impl) {
+      nir_foreach_instr (instr, block) {
+         if (instr->type != nir_instr_type_intrinsic)
+            continue;
+
+         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
+         if (intr->intrinsic != nir_intrinsic_store_output)
+            continue;
+
+         /* Line smooth lowering is only valid for vec4. */
+         if (intr->num_components != 4)
+            return false;
+      }
+   }
+
+   return true;
+}
+
+void
+radv_nir_lower_poly_line_smooth(nir_shader *nir, const struct radv_pipeline_key *key)
+{
+   bool progress = false;
+
+   if (!radv_should_lower_poly_line_smooth(nir, key))
+      return;
+
+   NIR_PASS(progress, nir, nir_lower_poly_line_smooth, RADV_NUM_SMOOTH_AA_SAMPLES);
+   if (progress)
+      nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+}

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d189d8d..409992d 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -970,6 +970,11 @@ radv_get_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
       return 1;
    }
 
+   if (d->vk.rs.line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT &&
+       radv_rast_prim_is_line(radv_get_rasterization_prim(cmd_buffer))) {
+      return RADV_NUM_SMOOTH_AA_SAMPLES;
+   }
+
    return MAX2(1, d->vk.ms.rasterization_samples);
 }
 
@@ -4479,6 +4484,9 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
                          S_028BE0_MAX_SAMPLE_DIST(max_sample_dist) |
                          S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) |
                          S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3);
+
+      if (d->vk.rs.line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT)
+         db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
    }
 
    pa_sc_aa_config |= S_028BE0_COVERAGE_TO_SHADER_SELECT(ps && ps->info.ps.reads_fully_covered);
@@ -4509,6 +4517,7 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
 static void
 radv_emit_line_rasterization_mode(struct radv_cmd_buffer *cmd_buffer)
 {
+   const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
    const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 
    /* The DX10 diamond test is unnecessary with Vulkan and it decreases line rasterization
@@ -4517,6 +4526,15 @@ radv_emit_line_rasterization_mode(struct radv_cmd_buffer *cmd_buffer)
    radeon_set_context_reg(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL,
                           S_028BDC_PERPENDICULAR_ENDCAP_ENA(
                              d->vk.rs.line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT));
+
+   if (cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]) {
+      const struct radv_userdata_info *loc = radv_get_user_sgpr(
+         cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT], AC_UD_PS_LINE_RAST_MODE);
+      if (loc->sgpr_idx != -1) {
+         uint32_t base_reg = ps->info.user_data_0;
+         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, d->vk.rs.line.mode);
+      }
+   }
 }
 
 static void
@@ -6640,6 +6658,11 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
    }
 
+   /* Re-emit the line rasterization mode state because the SGPR idx can be different. */
+   if (radv_get_user_sgpr(ps, AC_UD_PS_LINE_RAST_MODE)->sgpr_idx != -1) {
+      cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE;
+   }
+
    /* Re-emit the conservative rasterization mode because inner coverage is different. */
    if (previous_ps && previous_ps->info.ps.reads_fully_covered != ps->info.ps.reads_fully_covered)
       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;

diff --git a/src/amd/vulkan/radv_constants.h b/src/amd/vulkan/radv_constants.h
index 946c66c..6d8d12b 100644 (file)
--- a/src/amd/vulkan/radv_constants.h
+++ b/src/amd/vulkan/radv_constants.h
@@ -152,4 +152,7 @@
 #define RADV_NGG_QUERY_PRIM_GEN_OFFSET(stream) (20 + stream * 4)
 #define RADV_NGG_QUERY_PRIM_XFB_OFFSET(stream) (36 + stream * 4)
 
+/* Number of samples for line smooth lowering (hw requirement). */
+#define RADV_NUM_SMOOTH_AA_SAMPLES 4
+
 #endif /* RADV_CONSTANTS_H */

diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 6f8176b..3ee8521 100644 (file)
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -2761,6 +2761,10 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline,
       stages[i].feedback.duration += os_time_get_nano() - stage_start;
    }
 
+   if (stages[MESA_SHADER_FRAGMENT].nir) {
+      radv_nir_lower_poly_line_smooth(stages[MESA_SHADER_FRAGMENT].nir, pipeline_key);
+   }
+
    radv_fill_shader_info(device, pipeline, pipeline_layout, pipeline_key, stages,
                          active_nir_stages);