.send_immediate_char = cls_send_immediate_char
};
-
static inline void cls_set_cts_flow_control(struct channel_t *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char ier = readb(&ch->ch_cls_uart->ier);
unsigned char isr_fcr = 0;
-
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
}
-
static inline void cls_set_ixon_flow_control(struct channel_t *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char ier = readb(&ch->ch_cls_uart->ier);
unsigned char isr_fcr = 0;
-
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
}
-
static inline void cls_set_no_output_flow_control(struct channel_t *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char ier = readb(&ch->ch_cls_uart->ier);
unsigned char isr_fcr = 0;
-
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
}
-
static inline void cls_set_rts_flow_control(struct channel_t *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char ier = readb(&ch->ch_cls_uart->ier);
unsigned char isr_fcr = 0;
-
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
-
ch->ch_r_watermark = 4;
ch->ch_r_tlevel = 8;
}
-
static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char ier = readb(&ch->ch_cls_uart->ier);
unsigned char isr_fcr = 0;
-
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
}
-
static inline void cls_set_no_input_flow_control(struct channel_t *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char ier = readb(&ch->ch_cls_uart->ier);
unsigned char isr_fcr = 0;
-
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
}
-
/*
* cls_clear_break.
* Determines whether its time to shut off break condition.
spin_unlock_irqrestore(&ch->ch_lock, flags);
}
-
/* Parse the ISR register for the specific port */
static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
{
}
}
-
/*
* cls_param()
* Send any/all changes to the line to the UART.
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
}
-
/*
* Our board poller function.
*/
}
-
/*
* cls_intr()
*
return IRQ_HANDLED;
}
-
static void cls_disable_receiver(struct channel_t *ch)
{
unsigned char tmp = readb(&ch->ch_cls_uart->ier);
writeb(tmp, &ch->ch_cls_uart->ier);
}
-
static void cls_enable_receiver(struct channel_t *ch)
{
unsigned char tmp = readb(&ch->ch_cls_uart->ier);
writeb(tmp, &ch->ch_cls_uart->ier);
}
-
static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
{
int qleft = 0;
spin_unlock_irqrestore(&ch->ch_lock, flags);
}
-
/*
* This function basically goes to sleep for secs, or until
* it gets signalled that the port has fully drained.
((un->un_flags & UN_EMPTY) == 0));
}
-
/* Channel lock MUST be held before calling this function! */
static void cls_flush_uart_write(struct channel_t *ch)
{
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
}
-
/* Channel lock MUST be held before calling this function! */
static void cls_flush_uart_read(struct channel_t *ch)
{
udelay(10);
}
-
static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
{
ushort head;
spin_unlock_irqrestore(&ch->ch_lock, flags);
}
-
static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
{
unsigned char msignals = signals;
spin_unlock_irqrestore(&ch->ch_lock, flags);
}
-
/* Make the UART raise any of the output signals we want up */
static void cls_assert_modem_signals(struct channel_t *ch)
{
udelay(10);
}
-
static void cls_send_start_character(struct channel_t *ch)
{
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
}
}
-
static void cls_send_stop_character(struct channel_t *ch)
{
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
}
}
-
/* Inits UART */
static void cls_uart_init(struct channel_t *ch)
{
readb(&ch->ch_cls_uart->msr);
}
-
/*
* Turns off UART.
*/
writeb(0, &ch->ch_cls_uart->ier);
}
-
/*
* cls_get_uarts_bytes_left.
* Returns 0 is nothing left in the FIFO, returns 1 otherwise.
return left;
}
-
/*
* cls_send_break.
* Starts sending a break thru the UART.
}
}
-
/*
* cls_send_immediate_char.
* Sends a specific character as soon as possible to the UART,
u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */
int i = 0;
-
vpdbase = pci_resource_start(brd->pdev, 3);
/* No VPD */
if (re_map_vpdbase)
iounmap(re_map_vpdbase);
}
-