[RISCV] Update debug scratch register names

Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78764

diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 0f28471..e239870 100644 (file)
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1177,6 +1177,8 @@ RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
       return MatchOperand_ParseFail;
 
     auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
+    if (!SysReg)
+      SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
     // Accept a named Sys Reg if the required features are present.
     if (SysReg) {
       if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) {

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index a46a32c..853dca0 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -20,6 +20,8 @@ include "llvm/TableGen/SearchableTable.td"
 class SysReg<string name, bits<12> op> {
   string Name = name;
   bits<12> Encoding = op;
+  // A maximum of one alias is supported right now.
+  string AltName = name;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
   // Privilege Mode: User = 0, System = 1 or Machine = 3.
@@ -36,7 +38,7 @@ class SysReg<string name, bits<12> op> {
 def SysRegsList : GenericTable {
   let FilterClass = "SysReg";
   // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
-  let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ];
+  let Fields = [ "Name", "Encoding", "AltName", "FeaturesRequired", "isRV32Only" ];
 
   let PrimaryKey = [ "Encoding" ];
   let PrimaryKeyName = "lookupSysRegByEncoding";
@@ -47,6 +49,11 @@ def lookupSysRegByName : SearchIndex {
   let Key = [ "Name" ];
 }
 
+def lookupSysRegByAltName : SearchIndex {
+  let Table = SysRegsList;
+  let Key = [ "AltName" ];
+}
+
 // The following CSR encodings match those given in Tables 2.2,
 // 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
@@ -346,4 +353,8 @@ def : SysReg<"tdata3", 0x7A3>;
 //===-----------------------------------------------
 def : SysReg<"dcsr", 0x7B0>;
 def : SysReg<"dpc", 0x7B1>;
-def : SysReg<"dscratch", 0x7B2>;
+// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
+// drafts of the RISC-V debug spec
+let AltName = "dscratch" in
+def : SysReg<"dscratch0", 0x7B2>;
+def : SysReg<"dscratch1", 0x7B3>;

diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
index d36c528..2aa1b23 100644 (file)
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -157,6 +157,7 @@ namespace RISCVSysReg {
 struct SysReg {
   const char *Name;
   unsigned Encoding;
+  const char *AltName;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read, Write, Read-Only.
   // unsigned ReadWrite;

diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index 3932ebc..6467b04 100644 (file)
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -397,20 +397,48 @@ csrrs t1, dpc, zero
 # uimm12
 csrrs t2, 0x7B1, zero
 
+# dscratch0
+# name
+# CHECK-INST: csrrs t1, dscratch0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch0
+# uimm12
+# CHECK-INST: csrrs t2, dscratch0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch0
+# name
+csrrs t1, dscratch0, zero
+# uimm12
+csrrs t2, 0x7B2, zero
+
 # dscratch
 # name
-# CHECK-INST: csrrs t1, dscratch, zero
+# CHECK-INST: csrrs t1, dscratch0, zero
 # CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dscratch
+# CHECK-INST-ALIAS: csrr t1, dscratch0
 # uimm12
-# CHECK-INST: csrrs t2, dscratch, zero
+# CHECK-INST: csrrs t2, dscratch0, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dscratch
+# CHECK-INST-ALIAS: csrr t2, dscratch0
 # name
 csrrs t1, dscratch, zero
 # uimm12
 csrrs t2, 0x7B2, zero
 
+# dscratch1
+# name
+# CHECK-INST: csrrs t1, dscratch1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch1
+# uimm12
+# CHECK-INST: csrrs t2, dscratch1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch1
+# name
+csrrs t1, dscratch1, zero
+# uimm12
+csrrs t2, 0x7B3, zero
+
 # mhpmcounter3
 # name
 # CHECK-INST: csrrs t1, mhpmcounter3, zero