projects
/
platform
/
upstream
/
llvm.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
338def1
)
ARM: tLDR_postidx should be marked mayLoad
author
Matthias Braun
<matze@braunis.de>
Fri, 20 Jan 2017 18:30:28 +0000
(18:30 +0000)
committer
Matthias Braun
<matze@braunis.de>
Fri, 20 Jan 2017 18:30:28 +0000
(18:30 +0000)
This fixes -verify-machineinstrs complaints.
llvm-svn: 292629
llvm/lib/Target/ARM/ARMInstrThumb.td
patch
|
blob
|
history
diff --git
a/llvm/lib/Target/ARM/ARMInstrThumb.td
b/llvm/lib/Target/ARM/ARMInstrThumb.td
index
a681f64
..
b0bfae4
100644
(file)
--- a/
llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/
llvm/lib/Target/ARM/ARMInstrThumb.td
@@
-1477,7
+1477,7
@@
def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;
// post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
// different to how ISel expects them for a post-inc load, so use a pseudo
// and expand it just after ISel.
-let usesCustomInserter = 1,
+let usesCustomInserter = 1,
mayLoad =1,
Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in
def tLDR_postidx: tPseudoInst<(outs rGPR:$Rt, rGPR:$Rn_wb),
(ins rGPR:$Rn, pred:$p),