i965/gen6: Move scissor state to state streaming.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 748a750..0876c3e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -668,7 +668,6 @@ struct brw_context
       struct brw_sf_prog_data *prog_data;
 
       drm_intel_bo *prog_bo;
-      drm_intel_bo *state_bo;
       uint32_t state_offset;
       uint32_t vp_offset;
    } sf;

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 0ddd61b..c0ed6f7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -166,7 +166,6 @@ static void prepare_psp_urb_cbs(struct brw_context *brw)
    brw_add_validated_bo(brw, brw->vs.state_bo);
    brw_add_validated_bo(brw, brw->gs.state_bo);
    brw_add_validated_bo(brw, brw->clip.state_bo);
-   brw_add_validated_bo(brw, brw->sf.state_bo);
 }
 
 static void upload_psp_urb_cbs(struct brw_context *brw )

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 0fa1dc9..78b22c4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -39,7 +39,7 @@
 static void upload_sf_vp(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &intel->ctx;
    const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
    struct brw_sf_viewport *sfv;
    GLfloat y_scale, y_bias;

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 78d6f50..f1f51c8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -103,7 +103,6 @@ extern const struct brw_tracked_state gen6_depth_stencil_state;
 extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_scissor_state;
-extern const struct brw_tracked_state gen6_scissor_state_pointers;
 extern const struct brw_tracked_state gen6_sf_state;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index e148577..7d215f5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -149,7 +149,6 @@ static const struct brw_tracked_state *gen6_atoms[] =
    &gen6_wm_state,
 
    &gen6_scissor_state,
-   &gen6_scissor_state_pointers,
 
    &brw_state_base_address,
 

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 36c1cc8..b1b2e42 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -84,7 +84,6 @@ static void brw_destroy_context( struct intel_context *intel )
    dri_bo_release(&brw->clip.prog_bo);
    dri_bo_release(&brw->clip.state_bo);
    dri_bo_release(&brw->sf.prog_bo);
-   dri_bo_release(&brw->sf.state_bo);
    dri_bo_release(&brw->wm.prog_bo);
    dri_bo_release(&brw->wm.const_bo);
    dri_bo_release(&brw->cc.prog_bo);

diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index 12b6582..d0b37a0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -31,11 +31,15 @@
 #include "intel_batchbuffer.h"
 
 static void
-prepare_scissor_state(struct brw_context *brw)
+gen6_prepare_scissor_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &intel->ctx;
    const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
-   struct gen6_scissor_rect scissor;
+   struct gen6_scissor_rect *scissor;
+   uint32_t scissor_state_offset;
+
+   scissor = brw_state_batch(brw, sizeof(*scissor), 32, &scissor_state_offset);
 
    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
 
@@ -54,62 +58,37 @@ prepare_scissor_state(struct brw_context *brw)
        * anything.  Instead, just provide a min > max scissor inside
        * the bounds, which produces the expected no rendering.
        */
-      scissor.xmin = 1;
-      scissor.xmax = 0;
-      scissor.ymin = 1;
-      scissor.ymax = 0;
+      scissor->xmin = 1;
+      scissor->xmax = 0;
+      scissor->ymin = 1;
+      scissor->ymax = 0;
    } else if (render_to_fbo) {
       /* texmemory: Y=0=bottom */
-      scissor.xmin = ctx->DrawBuffer->_Xmin;
-      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
-      scissor.ymin = ctx->DrawBuffer->_Ymin;
-      scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
+      scissor->xmin = ctx->DrawBuffer->_Xmin;
+      scissor->xmax = ctx->DrawBuffer->_Xmax - 1;
+      scissor->ymin = ctx->DrawBuffer->_Ymin;
+      scissor->ymax = ctx->DrawBuffer->_Ymax - 1;
    }
    else {
       /* memory: Y=0=top */
-      scissor.xmin = ctx->DrawBuffer->_Xmin;
-      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
-      scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
-      scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
+      scissor->xmin = ctx->DrawBuffer->_Xmin;
+      scissor->xmax = ctx->DrawBuffer->_Xmax - 1;
+      scissor->ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
+      scissor->ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
    }
 
-   drm_intel_bo_unreference(brw->sf.state_bo);
-   brw->sf.state_bo = brw_cache_data(&brw->cache, BRW_SF_UNIT,
-                                    &scissor, sizeof(scissor));
-}
-
-const struct brw_tracked_state gen6_scissor_state = {
-   .dirty = {
-      .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
-      .brw = 0,
-      .cache = 0,
-   },
-   .prepare = prepare_scissor_state,
-};
-
-static void upload_scissor_state_pointers(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
-
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
-   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+            scissor_state_offset);
    ADVANCE_BATCH();
-
 }
 
-
-static void prepare_scissor_state_pointers(struct brw_context *brw)
-{
-   brw_add_validated_bo(brw, brw->sf.state_bo);
-}
-
-const struct brw_tracked_state gen6_scissor_state_pointers = {
+const struct brw_tracked_state gen6_scissor_state = {
    .dirty = {
-      .mesa = 0,
+      .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
       .brw = BRW_NEW_BATCH,
-      .cache = CACHE_NEW_SF_UNIT
+      .cache = 0,
    },
-   .prepare = prepare_scissor_state_pointers,
-   .emit = upload_scissor_state_pointers,
+   .prepare = gen6_prepare_scissor_state,
 };