The .code16gcc directive was added to binutils back in 1999:
---
'.code16gcc' provides experimental support for generating 16-bit code
from gcc, and differs from '.code16' in that 'call', 'ret', 'enter',
'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf'
instructions default to 32-bit size. This is so that the stack pointer
is manipulated in the same way over function calls, allowing access to
function parameters at the same stack offsets as in 32-bit mode.
'.code16gcc' also automatically adds address size prefixes where
necessary to use the 32-bit addressing modes that gcc generates.
---
It encodes 32-bit assembly instructions generated by GCC in 16-bit format
so that GCC can be used to generate 16-bit instructions. To do that, the
.code16gcc directive must be placed at the very beginning of the assembly
code. This patch adds -m16 to x86 backend by:
1. Add -m16 and make it mutually exclusive with -m32, -m64 and -mx32.
2. Treat -m16 like -m32 so that --32 is passed to assembler.
3. Output .code16gcc at the very beginning of the assembly code.
4. Turn off 64-bit ISA when -m16 is used.
PR target/59672
* config/i386/gnu-user64.h (SPEC_32): Add "m16|" to "m32".
(SPEC_X32): Likewise.
(SPEC_64): Likewise.
* config/i386/i386.c (ix86_option_override_internal): Turn off
OPTION_MASK_ISA_64BIT, OPTION_MASK_ABI_X32 and OPTION_MASK_ABI_64
for TARGET_16BIT.
(x86_file_start): Output .code16gcc for TARGET_16BIT.
* config/i386/i386.h (TARGET_16BIT): New macro.
(TARGET_16BIT_P): Likewise.
* config/i386/i386.opt: Add m16.
* doc/invoke.texi: Document -m16.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207196
138bc75d-0d04-0410-961f-
82ee72b054a4
+2014-01-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/59672
+ * config/i386/gnu-user64.h (SPEC_32): Add "m16|" to "m32".
+ (SPEC_X32): Likewise.
+ (SPEC_64): Likewise.
+ * config/i386/i386.c (ix86_option_override_internal): Turn off
+ OPTION_MASK_ISA_64BIT, OPTION_MASK_ABI_X32 and OPTION_MASK_ABI_64
+ for TARGET_16BIT.
+ (x86_file_start): Output .code16gcc for TARGET_16BIT.
+ * config/i386/i386.h (TARGET_16BIT): New macro.
+ (TARGET_16BIT_P): Likewise.
+ * config/i386/i386.opt: Add m16.
+ * doc/invoke.texi: Document -m16.
+
2014-01-28 Jakub Jelinek <jakub@redhat.com>
PR preprocessor/59935
done. */
#if TARGET_64BIT_DEFAULT
-#define SPEC_32 "m32"
+#define SPEC_32 "m16|m32"
#if TARGET_BI_ARCH == 2
#define SPEC_64 "m64"
-#define SPEC_X32 "m32|m64:;"
+#define SPEC_X32 "m16|m32|m64:;"
#else
-#define SPEC_64 "m32|mx32:;"
+#define SPEC_64 "m16|m32|mx32:;"
#define SPEC_X32 "mx32"
#endif
#else
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_64BIT;
opts->x_ix86_isa_flags &= ~OPTION_MASK_ABI_64;
}
+ else if (TARGET_16BIT_P (opts->x_ix86_isa_flags))
+ opts->x_ix86_isa_flags &= ~(OPTION_MASK_ISA_64BIT
+ | OPTION_MASK_ABI_X32
+ | OPTION_MASK_ABI_64);
else if (TARGET_LP64_P (opts->x_ix86_isa_flags))
{
/* Always turn on OPTION_MASK_ISA_64BIT and turn off
x86_file_start (void)
{
default_file_start ();
+ if (TARGET_16BIT)
+ fputs ("\t.code16gcc\n", asm_out_file);
#if TARGET_MACHO
darwin_file_start ();
#endif
#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
#define TARGET_X32 TARGET_ABI_X32
#define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
+#define TARGET_16BIT TARGET_CODE16
+#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
/* SSE4.1 defines round instructions */
#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
Generate 64bit x86-64 code
mx32
-Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
+Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
Generate 32bit x86-64 code
+m16
+Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
+Generate 16bit i386 code
+
mmmx
Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
Support MMX built-in functions
-mpc32 -mpc64 -mpc80 -mstackrealign @gol
-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
-mcmodel=@var{code-model} -mabi=@var{name} -maddress-mode=@var{mode} @gol
--m32 -m64 -mx32 -mlarge-data-threshold=@var{num} @gol
+-m32 -m64 -mx32 -m16 -mlarge-data-threshold=@var{num} @gol
-msse2avx -mfentry -m8bit-idiv @gol
-mavx256-split-unaligned-load -mavx256-split-unaligned-store @gol
-mstack-protector-guard=@var{guard}}
@item -m32
@itemx -m64
@itemx -mx32
+@itemx -m16
@opindex m32
@opindex m64
@opindex mx32
-Generate code for a 32-bit or 64-bit environment.
+@opindex m16
+Generate code for a 16-bit, 32-bit or 64-bit environment.
The @option{-m32} option sets @code{int}, @code{long}, and pointer types
to 32 bits, and
generates code that runs on any i386 system.
to 32 bits, and
generates code for the x86-64 architecture.
+The @option{-m16} option is the same as @option{-m32}, except for that
+it outputs the @code{.code16gcc} assembly directive at the beginning of
+the assembly output so that the binary can run in 16-bit mode.
+
@item -mno-red-zone
@opindex mno-red-zone
Do not use a so-called ``red zone'' for x86-64 code. The red zone is mandated
projects / platform / upstream / linaro-gcc.git / commitdiff