ARM: dts: sama7g5: Add USB and UTMI DT nodes

Define the USB and UTMI DT nodes for the sama7g5 SoC's. Since these have
not yet been defined in upstream Linux, place them in the U-Boot specific
DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
index d294ddb..f563071 100644 (file)
--- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
+++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
@@ -10,13 +10,87 @@
  *
  */
 
+#include <dt-bindings/reset/sama7g5-reset.h>
+#include <dt-bindings/clock/at91.h>
+
 / {
        chosen {
                u-boot,dm-pre-reloc;
        };
 
+       utmi {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               usb_phy0: phy@0 {
+                       compatible = "microchip,sama7g5-usb-phy";
+                       sfr-phandle = <&sfr>;
+                       reg = <0>;
+                       clocks = <&utmi_clk USB_UTMI1>;
+                       clock-names = "utmi_clk";
+                       status = "disabled";
+                       #phy-cells = <0>;
+               };
+
+               usb_phy1: phy@1 {
+                       compatible = "microchip,sama7g5-usb-phy";
+                       sfr-phandle = <&sfr>;
+                       reg = <1>;
+                       clocks = <&utmi_clk USB_UTMI2>;
+                       clock-names = "utmi_clk";
+                       status = "disabled";
+                       #phy-cells = <0>;
+               };
+
+               usb_phy2: phy@2 {
+                       compatible = "microchip,sama7g5-usb-phy";
+                       sfr-phandle = <&sfr>;
+                       reg = <2>;
+                       clocks = <&utmi_clk USB_UTMI3>;
+                       clock-names = "utmi_clk";
+                       status = "disabled";
+                       #phy-cells = <0>;
+               };
+       };
+
+       utmi_clk: utmi-clk {
+               compatible = "microchip,sama7g5-utmi-clk";
+               sfr-phandle = <&sfr>;
+               #clock-cells = <1>;
+               clocks = <&pmc PMC_TYPE_CORE 27>;
+               clock-names = "utmi_clk";
+               resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
+                        <&reset_controller SAMA7G5_RESET_USB_PHY2>,
+                        <&reset_controller SAMA7G5_RESET_USB_PHY3>;
+               reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+       };
+
        soc {
                u-boot,dm-pre-reloc;
+
+               usb2: usb@400000 {
+                       compatible = "microchip,sama7g5-ohci", "usb-ohci";
+                       reg = <0x00400000 0x100000>;
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
+                       clock-names = "ohci_clk", "hclk", "uhpck";
+                       status = "disabled";
+               };
+
+               usb3: usb@500000 {
+                       compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                       reg = <0x00500000 0x100000>;
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
+                       clock-names = "usb_clk", "ehci_clk";
+                       status = "disabled";
+               };
+
+               sfr: sfr@e1624000 {
+                       compatible = "microchip,sama7g5-sfr", "syscon";
+                       reg = <0xe1624000 0x4000>;
+               };
        };
 };
 
@@ -59,4 +133,3 @@
 &uart3 {
        u-boot,dm-pre-reloc;
 };
-