wifi: rtw89: coex: Fix wrong Wi-Fi role info and FDDT parameter members
authorChing-Te Ku <ku920601@realtek.com>
Mon, 18 Dec 2023 06:13:31 +0000 (14:13 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 5 Feb 2024 20:14:24 +0000 (20:14 +0000)
[ Upstream commit acc55d7dd4de525ac07e43e90ea3cc630677ec8a ]

The Wi-Fi firmware 29.29.X should use version 2 role info format. FDDT
mechanism version 5 use the same cell members to judge traffic situation,
don't need to add another new format.

Signed-off-by: Ching-Te Ku <ku920601@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20231218061341.51255-2-pkshih@realtek.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/wireless/realtek/rtw89/coex.c
drivers/net/wireless/realtek/rtw89/core.h

index 4ba8b3d..6ab1b6f 100644 (file)
@@ -131,7 +131,7 @@ static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = {
         .fcxbtcrpt = 105, .fcxtdma = 3,    .fcxslots = 1, .fcxcysta = 5,
         .fcxstep = 3,   .fcxnullsta = 2, .fcxmreg = 2,  .fcxgpiodbg = 1,
         .fcxbtver = 1,  .fcxbtscan = 2,  .fcxbtafh = 2, .fcxbtdevinfo = 1,
-        .fwlrole = 1,   .frptmap = 3,    .fcxctrl = 1,
+        .fwlrole = 2,   .frptmap = 3,    .fcxctrl = 1,
         .info_buf = 1800, .max_role_num = 6,
        },
        {RTL8852C, RTW89_FW_VER_CODE(0, 27, 57, 0),
@@ -159,7 +159,7 @@ static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = {
         .fcxbtcrpt = 105, .fcxtdma = 3,  .fcxslots = 1, .fcxcysta = 5,
         .fcxstep = 3,   .fcxnullsta = 2, .fcxmreg = 2,  .fcxgpiodbg = 1,
         .fcxbtver = 1,  .fcxbtscan = 2,  .fcxbtafh = 2, .fcxbtdevinfo = 1,
-        .fwlrole = 1,   .frptmap = 3,    .fcxctrl = 1,
+        .fwlrole = 2,   .frptmap = 3,    .fcxctrl = 1,
         .info_buf = 1800, .max_role_num = 6,
        },
        {RTL8852B, RTW89_FW_VER_CODE(0, 29, 14, 0),
index 04ce221..ee6ae2a 100644 (file)
@@ -2230,12 +2230,6 @@ struct rtw89_btc_fbtc_fddt_cell_status {
        u8 state_phase; /* [0:3] train state, [4:7] train phase */
 } __packed;
 
-struct rtw89_btc_fbtc_fddt_cell_status_v5 {
-       s8 wl_tx_pwr;
-       s8 bt_tx_pwr;
-       s8 bt_rx_gain;
-} __packed;
-
 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
        u8 fver;
        u8 rsvd;
@@ -2299,9 +2293,9 @@ struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
        struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
        struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
        struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
-       struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION]
-                                                           [FDD_TRAIN_WL_RSSI_LEVEL]
-                                                           [FDD_TRAIN_BT_RSSI_LEVEL];
+       struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
+                                                        [FDD_TRAIN_WL_RSSI_LEVEL]
+                                                        [FDD_TRAIN_BT_RSSI_LEVEL];
        __le32 except_map;
 } __packed;