MIPS: Emulate the new MIPS R6 BALC instruction
authorMarkos Chandras <markos.chandras@imgtec.com>
Wed, 26 Nov 2014 15:43:11 +0000 (15:43 +0000)
committerMarkos Chandras <markos.chandras@imgtec.com>
Tue, 17 Feb 2015 15:37:35 +0000 (15:37 +0000)
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/include/uapi/asm/inst.h
arch/mips/kernel/branch.c
arch/mips/math-emu/cp1emu.c

index 7833541..32063c5 100644 (file)
@@ -33,7 +33,7 @@ enum major_op {
        sdl_op, sdr_op, swr_op, cache_op,
        ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
        lld_op, ldc1_op, ldc2_op, ld_op,
-       sc_op, swc1_op, swc2_op, major_3b_op,
+       sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
        scd_op, sdc1_op, sdc2_op, sd_op
 };
 
index 37c7527..1f28724 100644 (file)
@@ -789,6 +789,16 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                }
                regs->cp0_epc += 8;
                break;
+       case balc6_op:
+               if (!cpu_has_mips_r6) {
+                       ret = -SIGILL;
+                       break;
+               }
+               /* Compact branch: BALC */
+               regs->regs[31] = epc + 4;
+               epc += 4 + (insn.i_format.simmediate << 2);
+               regs->cp0_epc = epc;
+               break;
 #endif
        case cbcond0_op:
        case cbcond1_op:
index 0d8407b..d732100 100644 (file)
@@ -671,6 +671,14 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                        dec_insn.next_pc_inc;
 
                return 1;
+       case balc6_op:
+               if (!cpu_has_mips_r6)
+                       break;
+               regs->regs[31] = regs->cp0_epc + 4;
+               *contpc = regs->cp0_epc + dec_insn.pc_inc +
+                       dec_insn.next_pc_inc;
+
+               return 1;
 #endif
        case cop0_op:
        case cop1_op: