"frsp %0,%1"
[(set_attr "type" "fp")])
+(define_insn "aux_truncdfsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
+ "! TARGET_POWERPC && TARGET_HARD_FLOAT"
+ "frsp %0,%1"
+ [(set_attr "type" "fp")])
+
(define_insn "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
/* If operands[1] is a register, it may have double-precision data
in it, so truncate it to single precision. We need not do
this for POWERPC. */
- if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
+ if (! TARGET_POWERPC && TARGET_HARD_FLOAT
+ && GET_CODE (operands[1]) == REG)
{
- rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
- emit_insn (gen_truncdfsf2 (newreg,
- gen_rtx (SUBREG, DFmode, operands[1], 0)));
+ rtx newreg
+ = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
+ emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
operands[1] = newreg;
}